Lines Matching +full:fail +full:- +full:fast
10 * - Data structures and the address mapping for all peripherals
11 * - Peripheral's registers declarations and bits definition
12 * - Macros to access peripheral's registers hardware
17 * Copyright (c) 2020-2021 STMicroelectronics.
22 * If no LICENSE file comes with this software, it is provided AS-IS.
55 /****** Cortex-M4 Processor Exceptions Numbers ***************************************************…
56 …NonMaskableInt_IRQn = -14, /*!< Non Maskable Interrupt …
57 …HardFault_IRQn = -13, /*!< Cortex-M4 Hard Fault Interrupt …
58 …MemoryManagement_IRQn = -12, /*!< Cortex-M4 Memory Management Interrupt …
59 …BusFault_IRQn = -11, /*!< Cortex-M4 Bus Fault Interrupt …
60 …UsageFault_IRQn = -10, /*!< Cortex-M4 Usage Fault Interrupt …
61 …SVCall_IRQn = -5, /*!< Cortex-M4 SV Call Interrupt …
62 …DebugMonitor_IRQn = -4, /*!< Cortex-M4 Debug Monitor Interrupt …
63 …PendSV_IRQn = -2, /*!< Cortex-M4 Pend SV Interrupt …
64 …SysTick_IRQn = -1, /*!< Cortex-M4 System Tick Interrupt …
135 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
144 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
179 … uint32_t RESERVED3[4]; /*!< Reserved, 0x30 - 0x3C */
181 … uint32_t RESERVED4[23];/*!< Reserved, 0x44 - 0x9C */
184 … uint32_t RESERVED5[3]; /*!< Reserved, 0xA8 - 0xB0 */
262 …__IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address o…
263 …__IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address o…
264 …__IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address o…
268 …__IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address o…
269 …__IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address o…
270 …__IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address o…
289 …uint32_t RESERVED1[13]; /*!< Reserved, 0x08-0x38 …
348 …4]; /*!< Reserved, Address offset: 0x10 - 0x1C */
353 …4]; /*!< Reserved, Address offset: 0x30 - 0x3C */
354 …8]; /*!< Reserved, Address offset: 0x40 - 0x5C */
355 …8]; /*!< Reserved, Address offset: 0x60 - 0x7C */
358 …2]; /*!< Reserved, Address offset: 0x88 - 0x8C */
393 …__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
398 …__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
407 …__IO uint32_t R[16]; /*!< HSEM 2-step write lock and read back registers, Address offset: 00h…
408 …_t Reserved1[16]; /*!< Reserved Address offset: 40h-7Ch */
409 …__IO uint32_t RLR[16]; /*!< HSEM 1-step read lock registers, Address offset: 80h…
410 …_t Reserved2[16]; /*!< Reserved Address offset: C0h-FCh */
415 …_t Reserved[12]; /*!< Reserved Address offset: 110h-13Ch*/
429 * @brief Inter-integrated Circuit Interface
484 …uint32_t Reserved1[253]; /*!< Reserved Address offset: 0x000C-0x03F…
485 …__IO uint32_t RAM[894]; /*!< PKA RAM, Address offset: 0x0400-0x11F…
501 …__IO uint32_t PUCRA; /*!< PWR Pull-Up Control Register of port A, Address offset:…
502 …__IO uint32_t PDCRA; /*!< PWR Pull-Down Control Register of port A, Address offset:…
503 …__IO uint32_t PUCRB; /*!< PWR Pull-Up Control Register of port B, Address offset:…
504 …__IO uint32_t PDCRB; /*!< PWR Pull-Down Control Register of port B, Address offset:…
505 …__IO uint32_t PUCRC; /*!< PWR Pull-Up Control Register of port C, Address offset:…
506 …__IO uint32_t PDCRC; /*!< PWR Pull-Down Control Register of port C, Address offset:…
507 …t RESERVED0[8]; /*!< Reserved, Address offset: 0x38-0x54 */
508 …__IO uint32_t PUCRH; /*!< PWR Pull-Up Control Register of port H, Address offset:…
509 …__IO uint32_t PDCRH; /*!< PWR Pull-Down Control Register of port H, Address offset:…
510 …t RESERVED1[10];/*!< Reserved, Address offset: 0x60-0x84 */
559 … Address offset: 0x98-0x104 */
582 * @brief Real-Time Clock
600 …__IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x…
638 …SCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
643 …served, Address offset: 0x28-0x204 */
663 …uint32_t RESERVED2[47];/*!< Reserved, Address offset: 0x54 - 0xFC */
702 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
708 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
776 … (SYSTEM_FLASH_BASE + 0x00007000UL) /*!< OTP area : 1kB (0x1FFF7000 - 0x1FFF73FF) */
777 …SE (SYSTEM_FLASH_BASE + 0x00007400UL) /*!< Engi Bytes : 1kB (0x1FFF7400 - 0x1FFF77FF) */
778 …BASE (SYSTEM_FLASH_BASE + 0x00007800UL) /*!< Option Bytes : 2kB (0x1FFF7800 - 0x1FFF7FFF) */
782 #define UID64_BASE (ENGI_BYTES_BASE + 0x00000180UL) /*!< 64-bit Unique device Identifi…
786 #define SYSTEM_MEMORY_END_ADDR (0x1FFF6FFFUL) /*!< System Memory : 28KB (0x1FFF0000 - 0x1FFF6FFF…
787 #define OTP_AREA_END_ADDR (0x1FFF73FFUL) /*!< OTP area : 1KB (0x1FFF7000 - 0x1FFF73FF) …
788 #define ENGI_BYTE_END_ADDR (0x1FFF77FFUL) /*!< Engi Bytes : 1kB (0x1FFF7400 - 0x1FFF77FF) …
789 #define OPTION_BYTE_END_ADDR (0x1FFF7FFFUL) /*!< Option Bytes : 2KB (0x1FFF7800 - 0x1FFF7FFF) …
1678 … ADC_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */
1835 #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-…
1840 #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-…
1845 #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-b…
1850 #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-…
1855 #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-…
1860 #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-b…
2151 #define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - B…
2160 … USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
2185 #define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - B…
2205 #define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit …
2249 #define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate …
2252 … USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
2257 #define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-O…
2271 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power …
2274 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Sel…
2313 … USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
2367 #define USART_RQR_ABRRQ ((uint16_t)0x0001) /*!< Auto-Baud Rate …
2418 #define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate …
2421 #define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate …
2538 … CRC_IDR_IDR_Msk /*!< General-purpose 8-bits data regist…
3708 #define FLASH_SR_MISERR FLASH_SR_MISERR_Msk /*!< Fast programmin…
3711 #define FLASH_SR_FASTERR FLASH_SR_FASTERR_Msk /*!< Fast programmin…
3752 #define FLASH_CR_FSTPG FLASH_CR_FSTPG_Msk /*!< Fast programmin…
3775 …CC FLASH_ECCR_ADDR_ECC_Msk /*!< double-word address ECC fail …
3778 … FLASH_ECCR_SYSF_ECC_Msk /*!< System flash ECC fail …
5106 #define PKA_MONTGOMERY_PARAM_IN_MOD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input modul…
5107 #define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input modul…
5110 #define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x594U - PKA_RAM_OFFSET)>>2) /*!< Output Mont…
5113 #define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Input expon…
5114 #define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
5115 #define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x594U - PKA_RAM_OFFSET)>>2) /*!< Input stora…
5116 #define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input base …
5117 #define PKA_MODULAR_EXP_IN_EXPONENT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Input expon…
5118 #define PKA_MODULAR_EXP_IN_MODULUS ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input modul…
5121 #define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x594U - PKA_RAM_OFFSET)>>2) /*!< Output stor…
5122 #define PKA_MODULAR_EXP_OUT_SM_ALGO_ACC1 ((0x724U - PKA_RAM_OFFSET)>>2) /*!< Output SM a…
5123 #define PKA_MODULAR_EXP_OUT_SM_ALGO_ACC2 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Output SM a…
5124 #define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Output base…
5125 #define PKA_MODULAR_EXP_OUT_SM_ALGO_ACC3 ((0xE3CU - PKA_RAM_OFFSET)>>2) /*!< Output SM a…
5128 #define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Input expon…
5129 #define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
5130 #define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x408U - PKA_RAM_OFFSET)>>2) /*!< Input sign …
5131 #define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x40CU - PKA_RAM_OFFSET)>>2) /*!< Input ECC c…
5132 #define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x460U - PKA_RAM_OFFSET)>>2) /*!< Input modul…
5133 #define PKA_ECC_SCALAR_MUL_IN_MONTGOMERY_PARAM ((0x4B4U - PKA_RAM_OFFSET)>>2) /*!< Input stora…
5134 #define PKA_ECC_SCALAR_MUL_IN_K ((0x508U - PKA_RAM_OFFSET)>>2) /*!< Input 'k' o…
5135 #define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x55CU - PKA_RAM_OFFSET)>>2) /*!< Input initi…
5136 #define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Input initi…
5139 #define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x55CU - PKA_RAM_OFFSET)>>2) /*!< Output resu…
5140 #define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Output resu…
5141 #define PKA_ECC_SCALAR_MUL_OUT_LAST_DOUBLE_X1 ((0xDE8U - PKA_RAM_OFFSET)>>2) /*!< Output last…
5142 #define PKA_ECC_SCALAR_MUL_OUT_LAST_DOUBLE_Y1 ((0xE3CU - PKA_RAM_OFFSET)>>2) /*!< Output last…
5143 #define PKA_ECC_SCALAR_MUL_OUT_LAST_DOUBLE_Z1 ((0xE90U - PKA_RAM_OFFSET)>>2) /*!< Output last…
5144 #define PKA_ECC_SCALAR_MUL_OUT_CHECK_POINT_X2 ((0xEE4U - PKA_RAM_OFFSET)>>2) /*!< Output chec…
5145 #define PKA_ECC_SCALAR_MUL_OUT_CHECK_POINT_Y2 ((0xF38U - PKA_RAM_OFFSET)>>2) /*!< Output chec…
5146 #define PKA_ECC_SCALAR_MUL_OUT_CHECK_POINT_Z2 ((0xF8CU - PKA_RAM_OFFSET)>>2) /*!< Output chec…
5149 #define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input modul…
5150 #define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x408U - PKA_RAM_OFFSET)>>2) /*!< Input sign …
5151 #define PKA_POINT_CHECK_IN_A_COEFF ((0x40CU - PKA_RAM_OFFSET)>>2) /*!< Input ECC c…
5152 #define PKA_POINT_CHECK_IN_B_COEFF ((0x7FCU - PKA_RAM_OFFSET)>>2) /*!< Input ECC c…
5153 #define PKA_POINT_CHECK_IN_MOD_GF ((0x460U - PKA_RAM_OFFSET)>>2) /*!< Input modul…
5154 #define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x55CU - PKA_RAM_OFFSET)>>2) /*!< Input initi…
5155 #define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Input initi…
5158 #define PKA_POINT_CHECK_OUT_ERROR ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Output erro…
5161 #define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Input order…
5162 #define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input modul…
5163 #define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x408U - PKA_RAM_OFFSET)>>2) /*!< Input sign …
5164 #define PKA_ECDSA_SIGN_IN_A_COEFF ((0x40CU - PKA_RAM_OFFSET)>>2) /*!< Input ECC c…
5165 #define PKA_ECDSA_SIGN_IN_MOD_GF ((0x460U - PKA_RAM_OFFSET)>>2) /*!< Input modul…
5166 #define PKA_ECDSA_SIGN_IN_K ((0x508U - PKA_RAM_OFFSET)>>2) /*!< Input k val…
5167 #define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x55CU - PKA_RAM_OFFSET)>>2) /*!< Input initi…
5168 #define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Input initi…
5169 #define PKA_ECDSA_SIGN_IN_HASH_E ((0xDE8U - PKA_RAM_OFFSET)>>2) /*!< Input e, ha…
5170 #define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0xE3CU - PKA_RAM_OFFSET)>>2) /*!< Input d, pr…
5171 #define PKA_ECDSA_SIGN_IN_ORDER_N ((0xE94U - PKA_RAM_OFFSET)>>2) /*!< Input n, or…
5174 #define PKA_ECDSA_SIGN_OUT_ERROR ((0xEE8U - PKA_RAM_OFFSET)>>2) /*!< Output erro…
5175 #define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x700U - PKA_RAM_OFFSET)>>2) /*!< Output sign…
5176 #define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x754U - PKA_RAM_OFFSET)>>2) /*!< Output sign…
5177 #define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x103CU - PKA_RAM_OFFSET)>>2) /*!< Output fin…
5178 #define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1090U - PKA_RAM_OFFSET)>>2) /*!< Output fin…
5181 #define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input order…
5182 #define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x4B4U - PKA_RAM_OFFSET)>>2) /*!< Input modul…
5183 #define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x45CU - PKA_RAM_OFFSET)>>2) /*!< Input sign …
5184 #define PKA_ECDSA_VERIF_IN_A_COEFF ((0x460U - PKA_RAM_OFFSET)>>2) /*!< Input ECC c…
5185 #define PKA_ECDSA_VERIF_IN_MOD_GF ((0x4B8U - PKA_RAM_OFFSET)>>2) /*!< Input modul…
5186 #define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x5E8U - PKA_RAM_OFFSET)>>2) /*!< Input initi…
5187 #define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x63CU - PKA_RAM_OFFSET)>>2) /*!< Input initi…
5188 #define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0xF40U - PKA_RAM_OFFSET)>>2) /*!< Input publi…
5189 #define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0xF94U - PKA_RAM_OFFSET)>>2) /*!< Input publi…
5190 #define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x1098U - PKA_RAM_OFFSET)>>2) /*!< Input r, p…
5191 #define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input s, pa…
5192 #define PKA_ECDSA_VERIF_IN_HASH_E ((0xFE8U - PKA_RAM_OFFSET)>>2) /*!< Input e, ha…
5193 #define PKA_ECDSA_VERIF_IN_ORDER_N ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input n, or…
5196 #define PKA_ECDSA_VERIF_OUT_RESULT ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Output resu…
5199 #define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
5200 #define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x65CU - PKA_RAM_OFFSET)>>2) /*!< Input Dp CR…
5201 #define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Input Dq CR…
5202 #define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x7ECU - PKA_RAM_OFFSET)>>2) /*!< Input qInv …
5203 #define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x97CU - PKA_RAM_OFFSET)>>2) /*!< Input Prime…
5204 #define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input Prime…
5205 #define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0xEECU - PKA_RAM_OFFSET)>>2) /*!< Input base …
5208 #define PKA_RSA_CRT_EXP_OUT_RESULT ((0x724U - PKA_RAM_OFFSET)>>2) /*!< Output resu…
5211 #define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
5212 #define PKA_MODULAR_REDUC_IN_OPERAND ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
5213 #define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input modul…
5214 #define PKA_MODULAR_REDUC_IN_MODULUS ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input modul…
5217 #define PKA_MODULAR_REDUC_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output resu…
5220 #define PKA_ARITHMETIC_ADD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
5221 #define PKA_ARITHMETIC_ADD_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
5222 #define PKA_ARITHMETIC_ADD_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
5225 #define PKA_ARITHMETIC_ADD_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output resu…
5228 #define PKA_ARITHMETIC_SUB_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
5229 #define PKA_ARITHMETIC_SUB_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
5230 #define PKA_ARITHMETIC_SUB_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
5233 #define PKA_ARITHMETIC_SUB_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output resu…
5236 #define PKA_ARITHMETIC_MUL_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
5237 #define PKA_ARITHMETIC_MUL_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
5238 #define PKA_ARITHMETIC_MUL_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
5241 #define PKA_ARITHMETIC_MUL_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output resu…
5244 #define PKA_COMPARISON_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
5245 #define PKA_COMPARISON_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
5246 #define PKA_COMPARISON_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
5249 #define PKA_COMPARISON_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output resu…
5252 #define PKA_MODULAR_ADD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
5253 #define PKA_MODULAR_ADD_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
5254 #define PKA_MODULAR_ADD_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
5255 #define PKA_MODULAR_ADD_IN_OP3_MOD ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input opera…
5258 #define PKA_MODULAR_ADD_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output resu…
5261 #define PKA_MODULAR_INV_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
5262 #define PKA_MODULAR_INV_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
5263 #define PKA_MODULAR_INV_IN_OP2_MOD ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
5266 #define PKA_MODULAR_INV_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output resu…
5269 #define PKA_MODULAR_SUB_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
5270 #define PKA_MODULAR_SUB_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
5271 #define PKA_MODULAR_SUB_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
5272 #define PKA_MODULAR_SUB_IN_OP3_MOD ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input opera…
5275 #define PKA_MODULAR_SUB_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output resu…
5278 #define PKA_MONTGOMERY_MUL_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
5279 #define PKA_MONTGOMERY_MUL_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
5280 #define PKA_MONTGOMERY_MUL_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
5281 #define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input modul…
5284 #define PKA_MONTGOMERY_MUL_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output resu…
5287 #define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
5288 #define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
5289 #define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
5290 #define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input opera…
5293 #define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output resu…
5311 #define PWR_CR1_SUBGHZSPINSSSEL PWR_CR1_SUBGHZSPINSSSEL_Msk /*!< Sub-GHz radio S…
5333 #define PWR_CR1_LPR PWR_CR1_LPR_Msk /*!< Regulator Low-P…
5354 … PWR_CR3_EWUP_Msk /*!< Enable all external Wake-Up lines */
5379 … PWR_CR3_APC_Msk /*!< Apply pull-up and pull-down configurat…
5383 … PWR_CR3_EWRFBUSY_Msk /*!< Enable Radio busy IRQ and wake-up for CPU1 */
5386 … PWR_CR3_EWRFIRQ_Msk /*!< Enable Radio IRQ[2:0] and wake-up for CPU1 */
5390 #define PWR_CR3_EIWUL PWR_CR3_EIWUL_Msk /*!< Internal Wake-U…
5395 #define PWR_CR4_WP1 PWR_CR4_WP1_Msk /*!< Wake-Up Pin 1 […
5398 #define PWR_CR4_WP2 PWR_CR4_WP2_Msk /*!< Wake-Up Pin 2 […
5401 #define PWR_CR4_WP3 PWR_CR4_WP3_Msk /*!< Wake-Up Pin 3 […
5412 #define PWR_CR4_WRFBUSYP PWR_CR4_WRFBUSYP_Msk /*!< Wake-up radio b…
5470 #define PWR_SR2_REGLPS PWR_SR2_REGLPS_Msk /*!< Low-power regul…
5473 #define PWR_SR2_REGLPF PWR_SR2_REGLPF_Msk /*!< Low-power regul…
5489 #define PWR_SCR_CWUF PWR_SCR_CWUF_Msk /*!< Clear Wake-up F…
5492 #define PWR_SCR_CWUF1 PWR_SCR_CWUF1_Msk /*!< Clear Wake-up P…
5495 #define PWR_SCR_CWUF2 PWR_SCR_CWUF2_Msk /*!< Clear Wake-up P…
5498 #define PWR_SCR_CWUF3 PWR_SCR_CWUF3_Msk /*!< Clear Wake-up P…
5520 #define PWR_PUCRA_PA0 PWR_PUCRA_PA0_Msk /*!< Pin PA0 Pull-Up…
5523 #define PWR_PUCRA_PA1 PWR_PUCRA_PA1_Msk /*!< Pin PA1 Pull-Up…
5526 #define PWR_PUCRA_PA2 PWR_PUCRA_PA2_Msk /*!< Pin PA2 Pull-Up…
5529 #define PWR_PUCRA_PA3 PWR_PUCRA_PA3_Msk /*!< Pin PA3 Pull-Up…
5532 #define PWR_PUCRA_PA4 PWR_PUCRA_PA4_Msk /*!< Pin PA4 Pull-Up…
5535 #define PWR_PUCRA_PA5 PWR_PUCRA_PA5_Msk /*!< Pin PA5 Pull-Up…
5538 #define PWR_PUCRA_PA6 PWR_PUCRA_PA6_Msk /*!< Pin PA6 Pull-Up…
5541 #define PWR_PUCRA_PA7 PWR_PUCRA_PA7_Msk /*!< Pin PA7 Pull-Up…
5544 #define PWR_PUCRA_PA8 PWR_PUCRA_PA8_Msk /*!< Pin PA8 Pull-Up…
5547 #define PWR_PUCRA_PA9 PWR_PUCRA_PA9_Msk /*!< Pin PA9 Pull-Up…
5550 #define PWR_PUCRA_PA10 PWR_PUCRA_PA10_Msk /*!< Pin PA10 Pull-U…
5553 #define PWR_PUCRA_PA11 PWR_PUCRA_PA11_Msk /*!< Pin PA11 Pull-U…
5556 #define PWR_PUCRA_PA12 PWR_PUCRA_PA12_Msk /*!< Pin PA12 Pull-U…
5559 #define PWR_PUCRA_PA13 PWR_PUCRA_PA13_Msk /*!< Pin PA13 Pull-U…
5562 #define PWR_PUCRA_PA14 PWR_PUCRA_PA14_Msk /*!< Pin PA14 Pull-U…
5565 #define PWR_PUCRA_PA15 PWR_PUCRA_PA15_Msk /*!< Pin PA15 Pull-U…
5570 #define PWR_PDCRA_PA0 PWR_PDCRA_PA0_Msk /*!< Pin PA0 Pull-Do…
5573 #define PWR_PDCRA_PA1 PWR_PDCRA_PA1_Msk /*!< Pin PA1 Pull-Do…
5576 #define PWR_PDCRA_PA2 PWR_PDCRA_PA2_Msk /*!< Pin PA2 Pull-Do…
5579 #define PWR_PDCRA_PA3 PWR_PDCRA_PA3_Msk /*!< Pin PA3 Pull-Do…
5582 #define PWR_PDCRA_PA4 PWR_PDCRA_PA4_Msk /*!< Pin PA4 Pull-Do…
5585 #define PWR_PDCRA_PA5 PWR_PDCRA_PA5_Msk /*!< Pin PA5 Pull-Do…
5588 #define PWR_PDCRA_PA6 PWR_PDCRA_PA6_Msk /*!< Pin PA6 Pull-Do…
5591 #define PWR_PDCRA_PA7 PWR_PDCRA_PA7_Msk /*!< Pin PA7 Pull-Do…
5594 #define PWR_PDCRA_PA8 PWR_PDCRA_PA8_Msk /*!< Pin PA8 Pull-Do…
5597 #define PWR_PDCRA_PA9 PWR_PDCRA_PA9_Msk /*!< Pin PA9 Pull-Do…
5600 #define PWR_PDCRA_PA10 PWR_PDCRA_PA10_Msk /*!< Pin PA10 Pull-D…
5603 #define PWR_PDCRA_PA11 PWR_PDCRA_PA11_Msk /*!< Pin PA11 Pull-D…
5606 #define PWR_PDCRA_PA12 PWR_PDCRA_PA12_Msk /*!< Pin PA12 Pull-D…
5609 #define PWR_PDCRA_PA13 PWR_PDCRA_PA13_Msk /*!< Pin PA13 Pull-D…
5612 #define PWR_PDCRA_PA14 PWR_PDCRA_PA14_Msk /*!< Pin PA14 Pull-D…
5615 #define PWR_PDCRA_PA15 PWR_PDCRA_PA15_Msk /*!< Pin PA15 Pull-D…
5620 #define PWR_PUCRB_PB0 PWR_PUCRB_PB0_Msk /*!< Pin PB0 Pull-Up…
5623 #define PWR_PUCRB_PB1 PWR_PUCRB_PB1_Msk /*!< Pin PB1 Pull-Up…
5626 #define PWR_PUCRB_PB2 PWR_PUCRB_PB2_Msk /*!< Pin PB2 Pull-Up…
5629 #define PWR_PUCRB_PB3 PWR_PUCRB_PB3_Msk /*!< Pin PB3 Pull-Up…
5632 #define PWR_PUCRB_PB4 PWR_PUCRB_PB4_Msk /*!< Pin PB4 Pull-Up…
5635 #define PWR_PUCRB_PB5 PWR_PUCRB_PB5_Msk /*!< Pin PB5 Pull-Up…
5638 #define PWR_PUCRB_PB6 PWR_PUCRB_PB6_Msk /*!< Pin PB6 Pull-Up…
5641 #define PWR_PUCRB_PB7 PWR_PUCRB_PB7_Msk /*!< Pin PB7 Pull-Up…
5644 #define PWR_PUCRB_PB8 PWR_PUCRB_PB8_Msk /*!< Pin PB8 Pull-Up…
5647 #define PWR_PUCRB_PB9 PWR_PUCRB_PB9_Msk /*!< Pin PB9 Pull-Up…
5650 #define PWR_PUCRB_PB10 PWR_PUCRB_PB10_Msk /*!< Pin PB10 Pull-U…
5653 #define PWR_PUCRB_PB11 PWR_PUCRB_PB11_Msk /*!< Pin PB11 Pull-U…
5656 #define PWR_PUCRB_PB12 PWR_PUCRB_PB12_Msk /*!< Pin PB12 Pull-U…
5659 #define PWR_PUCRB_PB13 PWR_PUCRB_PB13_Msk /*!< Pin PB13 Pull-U…
5662 #define PWR_PUCRB_PB14 PWR_PUCRB_PB14_Msk /*!< Pin PB14 Pull-U…
5665 #define PWR_PUCRB_PB15 PWR_PUCRB_PB15_Msk /*!< Pin PB15 Pull-U…
5670 #define PWR_PDCRB_PB0 PWR_PDCRB_PB0_Msk /*!< Pin PB0 Pull-Do…
5673 #define PWR_PDCRB_PB1 PWR_PDCRB_PB1_Msk /*!< Pin PB1 Pull-Do…
5676 #define PWR_PDCRB_PB2 PWR_PDCRB_PB2_Msk /*!< Pin PB2 Pull-Do…
5679 #define PWR_PDCRB_PB3 PWR_PDCRB_PB3_Msk /*!< Pin PB3 Pull-Do…
5682 #define PWR_PDCRB_PB4 PWR_PDCRB_PB4_Msk /*!< Pin PB4 Pull-Do…
5685 #define PWR_PDCRB_PB5 PWR_PDCRB_PB5_Msk /*!< Pin PB5 Pull-Do…
5688 #define PWR_PDCRB_PB6 PWR_PDCRB_PB6_Msk /*!< Pin PB6 Pull-Do…
5691 #define PWR_PDCRB_PB7 PWR_PDCRB_PB7_Msk /*!< Pin PB7 Pull-Do…
5694 #define PWR_PDCRB_PB8 PWR_PDCRB_PB8_Msk /*!< Pin PB8 Pull-Do…
5697 #define PWR_PDCRB_PB9 PWR_PDCRB_PB9_Msk /*!< Pin PB9 Pull-Do…
5700 #define PWR_PDCRB_PB10 PWR_PDCRB_PB10_Msk /*!< Pin PB10 Pull-D…
5703 #define PWR_PDCRB_PB11 PWR_PDCRB_PB11_Msk /*!< Pin PB11 Pull-D…
5706 #define PWR_PDCRB_PB12 PWR_PDCRB_PB12_Msk /*!< Pin PB12 Pull-D…
5709 #define PWR_PDCRB_PB13 PWR_PDCRB_PB13_Msk /*!< Pin PB13 Pull-D…
5712 #define PWR_PDCRB_PB14 PWR_PDCRB_PB14_Msk /*!< Pin PB14 Pull-D…
5715 #define PWR_PDCRB_PB15 PWR_PDCRB_PB15_Msk /*!< Pin PB15 Pull-D…
5720 #define PWR_PUCRC_PC0 PWR_PUCRC_PC0_Msk /*!< Pin PC0 Pull-Up…
5723 #define PWR_PUCRC_PC1 PWR_PUCRC_PC1_Msk /*!< Pin PC1 Pull-Up…
5726 #define PWR_PUCRC_PC2 PWR_PUCRC_PC2_Msk /*!< Pin PC2 Pull-Up…
5729 #define PWR_PUCRC_PC3 PWR_PUCRC_PC3_Msk /*!< Pin PC3 Pull-Up…
5732 #define PWR_PUCRC_PC4 PWR_PUCRC_PC4_Msk /*!< Pin PC4 Pull-Up…
5735 #define PWR_PUCRC_PC5 PWR_PUCRC_PC5_Msk /*!< Pin PC5 Pull-Up…
5738 #define PWR_PUCRC_PC6 PWR_PUCRC_PC6_Msk /*!< Pin PC6 Pull-Up…
5741 #define PWR_PUCRC_PC13 PWR_PUCRC_PC13_Msk /*!< Pin PC13 Pull-U…
5744 #define PWR_PUCRC_PC14 PWR_PUCRC_PC14_Msk /*!< Pin PC14 Pull-U…
5747 #define PWR_PUCRC_PC15 PWR_PUCRC_PC15_Msk /*!< Pin PC15 Pull-U…
5752 #define PWR_PDCRC_PC0 PWR_PDCRC_PC0_Msk /*!< Pin PC0 Pull-Do…
5755 #define PWR_PDCRC_PC1 PWR_PDCRC_PC1_Msk /*!< Pin PC1 Pull-Do…
5758 #define PWR_PDCRC_PC2 PWR_PDCRC_PC2_Msk /*!< Pin PC2 Pull-Do…
5761 #define PWR_PDCRC_PC3 PWR_PDCRC_PC3_Msk /*!< Pin PC3 Pull-Do…
5764 #define PWR_PDCRC_PC4 PWR_PDCRC_PC4_Msk /*!< Pin PC4 Pull-Do…
5767 #define PWR_PDCRC_PC5 PWR_PDCRC_PC5_Msk /*!< Pin PC5 Pull-Do…
5770 #define PWR_PDCRC_PC6 PWR_PDCRC_PC6_Msk /*!< Pin PC6 Pull-Do…
5773 #define PWR_PDCRC_PC13 PWR_PDCRC_PC13_Msk /*!< Pin PC13 Pull-D…
5776 #define PWR_PDCRC_PC14 PWR_PDCRC_PC14_Msk /*!< Pin PC14 Pull-D…
5779 #define PWR_PDCRC_PC15 PWR_PDCRC_PC15_Msk /*!< Pin PC15 Pull-D…
5784 #define PWR_PUCRH_PH3 PWR_PUCRH_PH3_Msk /*!< Pin PH3 Pull-Up…
5789 #define PWR_PDCRH_PH3 PWR_PDCRH_PH3_Msk /*!< Pin PH3 Pull-Do…
5813 #define PWR_SUBGHZSPICR_NSS PWR_SUBGHZSPICR_NSS_Msk /*!< Sub-GHz radio…
6726 /* Real-Time Clock (RTC) */
6880 …PALRM_PU RTC_CR_TAMPALRM_PU_Msk /*!<TAMPALARM output pull-up config */
7864 …6_FMP SYSCFG_CFGR1_I2C_PB6_FMP_Msk /*!< Fast-mode Plus (Fm+) dri…
7867 …7_FMP SYSCFG_CFGR1_I2C_PB7_FMP_Msk /*!< Fast-mode Plus (Fm+) dri…
7870 …8_FMP SYSCFG_CFGR1_I2C_PB8_FMP_Msk /*!< Fast-mode Plus (Fm+) dri…
7873 …9_FMP SYSCFG_CFGR1_I2C_PB9_FMP_Msk /*!< Fast-mode Plus (Fm+) dri…
7876 … SYSCFG_CFGR1_I2C1_FMP_Msk /*!< I2C1 Fast-mode Plus (Fm+) dri…
7879 … SYSCFG_CFGR1_I2C2_FMP_Msk /*!< I2C2 Fast-mode Plus (Fm+) dri…
7882 … SYSCFG_CFGR1_I2C3_FMP_Msk /*!< I2C3 Fast-mode Plus (Fm+) dri…
8077 …E0_Msk /*!< SRAM2 Write protection page 0 (0x20008000 - 0x200083FF) */
8080 …E1_Msk /*!< SRAM2 Write protection page 1 (0x20008400 - 0x200087FF) */
8083 …E2_Msk /*!< SRAM2 Write protection page 2 (0x20008800 - 0x20008BFF) */
8086 …E3_Msk /*!< SRAM2 Write protection page 3 (0x20008C00 - 0x20008FFF) */
8089 …E4_Msk /*!< SRAM2 Write protection page 4 (0x20009000 - 0x200093FF) */
8092 …E5_Msk /*!< SRAM2 Write protection page 5 (0x20009400 - 0x200097FF) */
8095 …E6_Msk /*!< SRAM2 Write protection page 6 (0x20009800 - 0x20009BFF) */
8098 …E7_Msk /*!< SRAM2 Write protection page 7 (0x20009C00 - 0x20009FFF) */
8101 …E8_Msk /*!< SRAM2 Write protection page 8 (0x2000A000 - 0x2000A3FF) */
8104 …E9_Msk /*!< SRAM2 Write protection page 9 (0x2000A400 - 0x2000A7FF) */
8107 …E10_Msk /*!< SRAM2 Write protection page 10 (0x2000A800 - 0x2000ABFF) */
8110 …E11_Msk /*!< SRAM2 Write protection page 11 (0x2000AC00 - 0x2000AFFF) */
8113 …E12_Msk /*!< SRAM2 Write protection page 12 (0x2000B000 - 0x2000B3FF) */
8116 …E13_Msk /*!< SRAM2 Write protection page 13 (0x2000B400 - 0x2000B7FF) */
8119 …E14_Msk /*!< SRAM2 Write protection page 14 (0x2000B800 - 0x2000BBFF) */
8122 …E15_Msk /*!< SRAM2 Write protection page 15 (0x2000BC00 - 0x2000BFFF) */
8125 …E16_Msk /*!< SRAM2 Write protection page 16 (0x2000C000 - 0x2000C3FF) */
8128 …E17_Msk /*!< SRAM2 Write protection page 17 (0x2000C400 - 0x2000C7FF) */
8131 …E18_Msk /*!< SRAM2 Write protection page 18 (0x2000C800 - 0x2000CBFF) */
8134 …E19_Msk /*!< SRAM2 Write protection page 19 (0x2000CC00 - 0x2000CFFF) */
8137 …E20_Msk /*!< SRAM2 Write protection page 20 (0x2000D000 - 0x2000D3FF) */
8140 …E21_Msk /*!< SRAM2 Write protection page 21 (0x2000D400 - 0x2000D7FF) */
8143 …E22_Msk /*!< SRAM2 Write protection page 22 (0x2000D800 - 0x2000DBFF) */
8146 …E23_Msk /*!< SRAM2 Write protection page 23 (0x2000DC00 - 0x2000DFFF) */
8149 …E24_Msk /*!< SRAM2 Write protection page 24 (0x2000E000 - 0x2000E3FF) */
8152 …E25_Msk /*!< SRAM2 Write protection page 25 (0x2000E400 - 0x2000E7FF) */
8155 …E26_Msk /*!< SRAM2 Write protection page 26 (0x2000E800 - 0x2000EBFF) */
8158 …E27_Msk /*!< SRAM2 Write protection page 27 (0x2000EC00 - 0x2000EFFF) */
8161 …E28_Msk /*!< SRAM2 Write protection page 28 (0x2000F000 - 0x2000F3FF) */
8164 …E29_Msk /*!< SRAM2 Write protection page 29 (0x2000F400 - 0x2000F7FF) */
8167 …E30_Msk /*!< SRAM2 Write protection page 30 (0x2000F800 - 0x2000FBFF) */
8170 …E31_Msk /*!< SRAM2 Write protection page 31 (0x2000FC00 - 0x2000FFFF) */
8184 /* Inter-integrated Circuit Interface (I2C) */
8258 #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressi…
8261 #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address …
8290 …AR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
8452 #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive d…
8457 #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit …
8532 #define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-B…
8548 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-b…
8668 … TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selectio…
8674 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload prel…
8926 …R1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
8951 …R1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
8968 /*----------------------------------------------------------------------------*/
9006 …R2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
9031 …R2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
9048 /*----------------------------------------------------------------------------*/
9080 …R3_OC5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */
9099 …R3_OC6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 6 Fast enable */
9191 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<Actual auto-relo…
9240 … TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
9258 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Select…
9261 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Select…
9292 …BDTR_BKDSRM TIM_BDTR_BKDSRM_Msk /*!<Break disarming/re-arming */
9295 …DTR_BK2DSRM TIM_BDTR_BK2DSRM_Msk /*!<Break2 disarming/re-arming */
9707 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
9789 /******************** UART Instances : Half-Duplex mode **********************/
9798 /******************** UART Instances : Wake-up from Stop mode **********************/