/** ****************************************************************************** * @file stm32wle4xx.h * @author MCD Application Team * @brief CMSIS Cortex Device Peripheral Access Layer Header File. * This file contains all the peripheral register's definitions, bits * definitions and memory mapping for stm32wle4xx devices. * * This file contains:selected * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention * * Copyright (c) 2020-2021 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /** @addtogroup CMSIS_Device * @{ */ /** @addtogroup stm32wle4xx * @{ */ #ifndef __STM32WLE4xx_H #define __STM32WLE4xx_H #ifdef __cplusplus extern "C" { #endif /* __cplusplus */ /** @addtogroup Peripheral_interrupt_number_definition * @{ */ /** * @brief stm32wle4xx Interrupt Number Definition, according to the selected device * in @ref Library_configuration_section */ /*!< Interrupt Number Definition for M4 */ typedef enum { /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ NonMaskableInt_IRQn = -14, /*!< Non Maskable Interrupt */ HardFault_IRQn = -13, /*!< Cortex-M4 Hard Fault Interrupt */ MemoryManagement_IRQn = -12, /*!< Cortex-M4 Memory Management Interrupt */ BusFault_IRQn = -11, /*!< Cortex-M4 Bus Fault Interrupt */ UsageFault_IRQn = -10, /*!< Cortex-M4 Usage Fault Interrupt */ SVCall_IRQn = -5, /*!< Cortex-M4 SV Call Interrupt */ DebugMonitor_IRQn = -4, /*!< Cortex-M4 Debug Monitor Interrupt */ PendSV_IRQn = -2, /*!< Cortex-M4 Pend SV Interrupt */ SysTick_IRQn = -1, /*!< Cortex-M4 System Tick Interrupt */ /************* STM32WLxx specific Interrupt Numbers on M4 core ************************************************/ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ PVD_PVM_IRQn = 1, /*!< PVD and PVM detector */ TAMP_STAMP_LSECSS_SSRU_IRQn = 2, /*!< RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU Interrupts */ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup Interrupt */ FLASH_IRQn = 4, /*!< FLASH (CFI) global Interrupt */ RCC_IRQn = 5, /*!< RCC Interrupt */ EXTI0_IRQn = 6, /*!< EXTI Line 0 Interrupt */ EXTI1_IRQn = 7, /*!< EXTI Line 1 Interrupt */ EXTI2_IRQn = 8, /*!< EXTI Line 2 Interrupt */ EXTI3_IRQn = 9, /*!< EXTI Line 3 Interrupt */ EXTI4_IRQn = 10, /*!< EXTI Line 4 Interrupt */ DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */ DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */ DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */ DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */ DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */ DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */ ADC_IRQn = 18, /*!< ADC Interrupt */ DAC_IRQn = 19, /*!< DAC Interrupt */ COMP_IRQn = 21, /*!< COMP1 and COMP2 Interrupts */ EXTI9_5_IRQn = 22, /*!< EXTI Lines [9:5] Interrupt */ TIM1_BRK_IRQn = 23, /*!< TIM1 Break Interrupt */ TIM1_UP_IRQn = 24, /*!< TIM1 Update Interrupt */ TIM1_TRG_COM_IRQn = 25, /*!< TIM1 Trigger and Communication Interrupts */ TIM1_CC_IRQn = 26, /*!< TIM1 Capture Compare Interrupt */ TIM2_IRQn = 27, /*!< TIM2 Global Interrupt */ TIM16_IRQn = 28, /*!< TIM16 Global Interrupt */ TIM17_IRQn = 29, /*!< TIM17 Global Interrupt */ I2C1_EV_IRQn = 30, /*!< I2C1 Event Interrupt */ I2C1_ER_IRQn = 31, /*!< I2C1 Error Interrupt */ I2C2_EV_IRQn = 32, /*!< I2C2 Event Interrupt */ I2C2_ER_IRQn = 33, /*!< I2C2 Error Interrupt */ SPI1_IRQn = 34, /*!< SPI1 Interrupt */ SPI2_IRQn = 35, /*!< SPI2 Interrupt */ USART1_IRQn = 36, /*!< USART1 Interrupt */ USART2_IRQn = 37, /*!< USART2 Interrupt */ LPUART1_IRQn = 38, /*!< LPUART1 Interrupt */ LPTIM1_IRQn = 39, /*!< LPTIM1 Global Interrupt */ LPTIM2_IRQn = 40, /*!< LPTIM2 Global Interrupt */ EXTI15_10_IRQn = 41, /*!< EXTI Lines [15:10] Interrupt */ RTC_Alarm_IRQn = 42, /*!< RTC Alarms (A and B) Interrupt */ LPTIM3_IRQn = 43, /*!< LPTIM3 Global Interrupt */ SUBGHZSPI_IRQn = 44, /*!< SUBGHZSPI Interrupt */ HSEM_IRQn = 47, /*!< HSEM Interrupt */ I2C3_EV_IRQn = 48, /*!< I2C3 Event Interrupt */ I2C3_ER_IRQn = 49, /*!< I2C3 Error Interrupt */ SUBGHZ_Radio_IRQn = 50, /*!< SUBGHZ Radio Interrupt */ AES_IRQn = 51, /*!< AES Interrupt */ RNG_IRQn = 52, /*!< RNG Interrupt */ PKA_IRQn = 53, /*!< PKA Interrupt */ DMA2_Channel1_IRQn = 54, /*!< DMA2 Channel 1 Interrupt */ DMA2_Channel2_IRQn = 55, /*!< DMA2 Channel 2 Interrupt */ DMA2_Channel3_IRQn = 56, /*!< DMA2 Channel 3 Interrupt */ DMA2_Channel4_IRQn = 57, /*!< DMA2 Channel 4 Interrupt */ DMA2_Channel5_IRQn = 58, /*!< DMA2 Channel 5 Interrupt */ DMA2_Channel6_IRQn = 59, /*!< DMA2 Channel 6 Interrupt */ DMA2_Channel7_IRQn = 60, /*!< DMA2 Channel 7 Interrupt */ DMAMUX1_OVR_IRQn = 61 /*!< DMAMUX1 overrun Interrupt */ } IRQn_Type; /** * @} */ /** @addtogroup Configuration_section_for_CMSIS * @{ */ /** * @brief Configuration of the Cortex-M4 Processor and Core Peripherals */ #define __CM4_REV 1U /*!< Core Revision r0p1 */ #define __MPU_PRESENT 1U /*!< M4 provides an MPU */ #define __VTOR_PRESENT 1U /*!< Vector Table Register supported */ #define __NVIC_PRIO_BITS 4U /*!< STM32WLxx uses 4 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ #define __FPU_PRESENT 0U /*!< FPU not present */ #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ #include "system_stm32wlxx.h" #include /** * @} */ /** @addtogroup Peripheral_registers_structures * @{ */ /** * @brief Analog to Digital Converter */ typedef struct { __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ __IO uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x0C */ __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ __IO uint32_t SMPR; /*!< ADC sampling time register, Address offset: 0x14 */ uint32_t RESERVED1; /*!< Reserved, 0x18 */ uint32_t RESERVED2; /*!< Reserved, 0x1C */ __IO uint32_t AWD1TR; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ __IO uint32_t AWD2TR; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */ __IO uint32_t CHSELR; /*!< ADC group regular sequencer register, Address offset: 0x28 */ __IO uint32_t AWD3TR; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x2C */ uint32_t RESERVED3[4]; /*!< Reserved, 0x30 - 0x3C */ __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ uint32_t RESERVED4[23];/*!< Reserved, 0x44 - 0x9C */ __IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */ __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 configuration register, Address offset: 0xA4 */ uint32_t RESERVED5[3]; /*!< Reserved, 0xA8 - 0xB0 */ __IO uint32_t CALFACT; /*!< ADC Calibration factor register, Address offset: 0xB4 */ } ADC_TypeDef; typedef struct { __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC base address + 0x308 */ } ADC_Common_TypeDef; /* Legacy registers naming */ #define TR1 AWD1TR #define TR2 AWD2TR #define TR3 AWD3TR /** * @brief AES hardware accelerator */ typedef struct { __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */ __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */ __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */ __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */ __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */ __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */ __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */ __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */ __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */ __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */ __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */ __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */ __IO uint32_t KEYR4; /*!< AES key register 4, Address offset: 0x30 */ __IO uint32_t KEYR5; /*!< AES key register 5, Address offset: 0x34 */ __IO uint32_t KEYR6; /*!< AES key register 6, Address offset: 0x38 */ __IO uint32_t KEYR7; /*!< AES key register 7, Address offset: 0x3C */ __IO uint32_t SUSP0R; /*!< AES Suspend register 0, Address offset: 0x40 */ __IO uint32_t SUSP1R; /*!< AES Suspend register 1, Address offset: 0x44 */ __IO uint32_t SUSP2R; /*!< AES Suspend register 2, Address offset: 0x48 */ __IO uint32_t SUSP3R; /*!< AES Suspend register 3, Address offset: 0x4C */ __IO uint32_t SUSP4R; /*!< AES Suspend register 4, Address offset: 0x50 */ __IO uint32_t SUSP5R; /*!< AES Suspend register 5, Address offset: 0x54 */ __IO uint32_t SUSP6R; /*!< AES Suspend register 6, Address offset: 0x58 */ __IO uint32_t SUSP7R; /*!< AES Suspend register 7, Address offset: 0x6C */ } AES_TypeDef; /** * @brief Comparator */ typedef struct { __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */ } COMP_TypeDef; typedef struct { __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ } COMP_Common_TypeDef; /** * @brief CRC calculation unit */ typedef struct { __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ uint32_t RESERVED2; /*!< Reserved, 0x0C */ __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ } CRC_TypeDef; /** * @brief Digital to Analog Converter */ typedef struct { __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ uint32_t RESERVED1; /*!< Reserved Address offset: 0x14 */ uint32_t RESERVED2; /*!< Reserved Address offset: 0x18 */ uint32_t RESERVED3; /*!< Reserved Address offset: 0x1C */ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ uint32_t RESERVED4; /*!< Reserved Address offset: 0x30 */ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ uint32_t RESERVED5; /*!< Reserved Address offset: 0x44 */ __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ } DAC_TypeDef; /** * @brief Debug MCU */ typedef struct { __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ uint32_t RESERVED1[13]; /*!< Reserved, 0x08-0x38 */ __IO uint32_t APB1FZR1; /*!< Debug MCU CPU1 APB1 freeze register, Address offset: 0x3C */ uint32_t RESERVED2; /*!< Reserved, Address offset: 0x40 */ __IO uint32_t APB1FZR2; /*!< Debug MCU CPU1 APB1 freeze register, Address offset: 0x44 */ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x48 */ __IO uint32_t APB2FZR; /*!< Debug MCU CPU1 APB2 freeze register, Address offset: 0x4C */ } DBGMCU_TypeDef; /** * @brief DMA Controller */ typedef struct { __IO uint32_t CCR; /*!< DMA channel x configuration register */ __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ __IO uint32_t CMAR; /*!< DMA channel x memory address register */ } DMA_Channel_TypeDef; typedef struct { __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ } DMA_TypeDef; /** * @brief DMA Multiplexer */ typedef struct { __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */ }DMAMUX_Channel_TypeDef; typedef struct { __IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */ __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */ }DMAMUX_ChannelStatus_TypeDef; typedef struct { __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */ }DMAMUX_RequestGen_TypeDef; typedef struct { __IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */ __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */ }DMAMUX_RequestGenStatus_TypeDef; /** * @brief Async Interrupts and Events Controller */ typedef struct { __IO uint32_t RTSR1; /*!< EXTI rising trigger selection register [31:0], Address offset: 0x00 */ __IO uint32_t FTSR1; /*!< EXTI falling trigger selection register [31:0], Address offset: 0x04 */ __IO uint32_t SWIER1; /*!< EXTI software interrupt event register [31:0], Address offset: 0x08 */ __IO uint32_t PR1; /*!< EXTI pending register [31:0], Address offset: 0x0C */ __IO uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x10 - 0x1C */ __IO uint32_t RTSR2; /*!< EXTI rising trigger selection register [31:0], Address offset: 0x20 */ __IO uint32_t FTSR2; /*!< EXTI falling trigger selection register [31:0], Address offset: 0x24 */ __IO uint32_t SWIER2; /*!< EXTI software interrupt event register [31:0], Address offset: 0x28 */ __IO uint32_t PR2; /*!< EXTI pending register [31:0], Address offset: 0x2C */ __IO uint32_t RESERVED2[4]; /*!< Reserved, Address offset: 0x30 - 0x3C */ __IO uint32_t RESERVED3[8]; /*!< Reserved, Address offset: 0x40 - 0x5C */ __IO uint32_t RESERVED4[8]; /*!< Reserved, Address offset: 0x60 - 0x7C */ __IO uint32_t IMR1; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */ __IO uint32_t EMR1; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x84 */ __IO uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x88 - 0x8C */ __IO uint32_t IMR2; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */ __IO uint32_t EMR2; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x94 */ }EXTI_TypeDef; /** * @brief FLASH Registers */ typedef struct { __IO uint32_t ACR; /*!< FLASH Access control register, Address offset: 0x00 */ uint32_t RESERVED0; /*!< Reserved, Address offset: 0x04 */ __IO uint32_t KEYR; /*!< FLASH Key register, Address offset: 0x08 */ __IO uint32_t OPTKEYR; /*!< FLASH Option Key register, Address offset: 0x0C */ __IO uint32_t SR; /*!< FLASH Status register, Address offset: 0x10 */ __IO uint32_t CR; /*!< FLASH Control register, Address offset: 0x14 */ __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */ uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */ __IO uint32_t OPTR; /*!< FLASH Option register, Address offset: 0x20 */ __IO uint32_t PCROP1ASR; /*!< FLASH Bank 1 PCROP area A Start address register, Address offset: 0x24 */ __IO uint32_t PCROP1AER; /*!< FLASH Bank 1 PCROP area A End address register, Address offset: 0x28 */ __IO uint32_t WRP1AR; /*!< FLASH Bank 1 WRP area A address register, Address offset: 0x2C */ __IO uint32_t WRP1BR; /*!< FLASH Bank 1 WRP area B address register, Address offset: 0x30 */ __IO uint32_t PCROP1BSR; /*!< FLASH Bank 1 PCROP area B Start address register, Address offset: 0x34 */ __IO uint32_t PCROP1BER; /*!< FLASH Bank 1 PCROP area B End address register, Address offset: 0x38 */ } FLASH_TypeDef; /** * @brief General Purpose I/O */ typedef struct { __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ } GPIO_TypeDef; /** * @brief HW Semaphore HSEM */ typedef struct { __IO uint32_t R[16]; /*!< HSEM 2-step write lock and read back registers, Address offset: 00h-3Ch */ uint32_t Reserved1[16]; /*!< Reserved Address offset: 40h-7Ch */ __IO uint32_t RLR[16]; /*!< HSEM 1-step read lock registers, Address offset: 80h-BCh */ uint32_t Reserved2[16]; /*!< Reserved Address offset: C0h-FCh */ __IO uint32_t C1IER; /*!< HSEM CPU1 interrupt enable register , Address offset: 100h */ __IO uint32_t C1ICR; /*!< HSEM CPU1 interrupt clear register , Address offset: 104h */ __IO uint32_t C1ISR; /*!< HSEM CPU1 interrupt status register , Address offset: 108h */ __IO uint32_t C1MISR; /*!< HSEM CPU1 masked interrupt status register , Address offset: 10Ch */ uint32_t Reserved[12]; /*!< Reserved Address offset: 110h-13Ch*/ __IO uint32_t CR; /*!< HSEM Semaphore clear register , Address offset: 140h */ __IO uint32_t KEYR; /*!< HSEM Semaphore clear key register , Address offset: 144h */ } HSEM_TypeDef; typedef struct { __IO uint32_t IER; /*!< HSEM interrupt enable register , Address offset: 0h */ __IO uint32_t ICR; /*!< HSEM interrupt clear register , Address offset: 4h */ __IO uint32_t ISR; /*!< HSEM interrupt status register , Address offset: 8h */ __IO uint32_t MISR; /*!< HSEM masked interrupt status register , Address offset: Ch */ } HSEM_Common_TypeDef; /** * @brief Inter-integrated Circuit Interface */ typedef struct { __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ } I2C_TypeDef; /** * @brief Independent WATCHDOG */ typedef struct { __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ } IWDG_TypeDef; /** * @brief LPTIMER */ typedef struct { __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */ __IO uint32_t RESERVED; /*!< Reserved, Address offset: 0x24 */ __IO uint32_t RCR; /*!< LPTIM repetition register, Address offset: 0x28 */ } LPTIM_TypeDef; /** * @brief Public Key Accelerator (PKA) */ typedef struct { __IO uint32_t CR; /*!< PKA control register, Address offset: 0x00 */ __IO uint32_t SR; /*!< PKA status register, Address offset: 0x04 */ __IO uint32_t CLRFR; /*!< PKA clear flag register, Address offset: 0x08 */ uint32_t Reserved1[253]; /*!< Reserved Address offset: 0x000C-0x03FC*/ __IO uint32_t RAM[894]; /*!< PKA RAM, Address offset: 0x0400-0x11F4 */ } PKA_TypeDef; /** * @brief Power Control */ typedef struct { __IO uint32_t CR1; /*!< PWR Power Control Register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< PWR Power Control Register 2, Address offset: 0x04 */ __IO uint32_t CR3; /*!< PWR Power Control Register 3, Address offset: 0x08 */ __IO uint32_t CR4; /*!< PWR Power Control Register 4, Address offset: 0x0C */ __IO uint32_t SR1; /*!< PWR Power Status Register 1, Address offset: 0x10 */ __IO uint32_t SR2; /*!< PWR Power Status Register 2, Address offset: 0x14 */ __IO uint32_t SCR; /*!< PWR Power Status Reset Register, Address offset: 0x18 */ __IO uint32_t CR5; /*!< PWR Power Control Register 5, Address offset: 0x1C */ __IO uint32_t PUCRA; /*!< PWR Pull-Up Control Register of port A, Address offset: 0x20 */ __IO uint32_t PDCRA; /*!< PWR Pull-Down Control Register of port A, Address offset: 0x24 */ __IO uint32_t PUCRB; /*!< PWR Pull-Up Control Register of port B, Address offset: 0x28 */ __IO uint32_t PDCRB; /*!< PWR Pull-Down Control Register of port B, Address offset: 0x2C */ __IO uint32_t PUCRC; /*!< PWR Pull-Up Control Register of port C, Address offset: 0x30 */ __IO uint32_t PDCRC; /*!< PWR Pull-Down Control Register of port C, Address offset: 0x34 */ uint32_t RESERVED0[8]; /*!< Reserved, Address offset: 0x38-0x54 */ __IO uint32_t PUCRH; /*!< PWR Pull-Up Control Register of port H, Address offset: 0x58 */ __IO uint32_t PDCRH; /*!< PWR Pull-Down Control Register of port H, Address offset: 0x5C */ uint32_t RESERVED1[10];/*!< Reserved, Address offset: 0x60-0x84 */ __IO uint32_t EXTSCR; /*!< PWR Power Status Reset Register for CPU2, Address offset: 0x88 */ uint32_t RESERVED2; /*!< Reserved, Address offset: 0x8C */ __IO uint32_t SUBGHZSPICR; /*!< PWR SUBGHZSPI Control Register, Address offset: 0x90 */ } PWR_TypeDef; /** * @brief Reset and Clock Control */ typedef struct { __IO uint32_t CR; /*!< RCC clock Control Register, Address offset: 0x00 */ __IO uint32_t ICSCR; /*!< RCC Internal Clock Sources Calibration Register, Address offset: 0x04 */ __IO uint32_t CFGR; /*!< RCC Clocks Configuration Register, Address offset: 0x08 */ __IO uint32_t PLLCFGR; /*!< RCC System PLL configuration Register, Address offset: 0x0C */ uint32_t RESERVED0; /*!< Reserved, Address offset: 0x10 */ uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ __IO uint32_t CIER; /*!< RCC Clock Interrupt Enable Register, Address offset: 0x18 */ __IO uint32_t CIFR; /*!< RCC Clock Interrupt Flag Register, Address offset: 0x1C */ __IO uint32_t CICR; /*!< RCC Clock Interrupt Clear Register, Address offset: 0x20 */ uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */ __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */ __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x30 */ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x34 */ __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */ __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */ __IO uint32_t APB3RSTR; /*!< RCC APB3 peripheral reset register, Address offset: 0x44 */ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */ __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */ __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x50 */ uint32_t RESERVED4; /*!< Reserved, Address offset: 0x54 */ __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */ __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */ __IO uint32_t APB3ENR; /*!< RCC APB3 peripheral clocks enable register, Address offset: 0x64 */ __IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */ __IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */ __IO uint32_t AHB3SMENR; /*!< RCC AHB3 & AHB4 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */ uint32_t RESERVED5; /*!< Reserved, Address offset: 0x74 */ __IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */ __IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */ __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */ __IO uint32_t APB3SMENR; /*!< RCC APB3 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x84 */ __IO uint32_t CCIPR; /*!< RCC Peripherals Clock Configuration Independent Register, Address offset: 0x88 */ uint32_t RESERVED6; /*!< Reserved, Address offset: 0x8C */ __IO uint32_t BDCR; /*!< RCC Backup Domain Control Register, Address offset: 0x90 */ __IO uint32_t CSR; /*!< RCC Control and Status Register, Address offset: 0x94 */ uint32_t RESERVED7[28]; /*!< Reserved, Address offset: 0x98-0x104 */ __IO uint32_t EXTCFGR; /*!< RCC Extended Clock Recovery Register, Address offset: 0x108 */ } RCC_TypeDef; /** * @brief RNG */ typedef struct { __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ uint32_t RESERVED0; /*!< Reserved, Address offset: 0x0C */ __IO uint32_t HTCR; /*!< RNG health test control register, Address offset: 0x10 */ } RNG_TypeDef; /** * @brief RTC Specific device feature definitions */ #define RTC_BACKUP_NB 20u #define RTC_TAMP_NB 3u /** * @brief Real-Time Clock */ typedef struct { __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ uint32_t RESERVED0; /*!< Reserved, Address offset: 0x1C */ uint32_t RESERVED1; /*!< Reserved, Address offset: 0x20 */ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ uint32_t RESERVED2; /*!< Reserved, Address offset: 0x3C */ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x58 */ __IO uint32_t SCR; /*!< RTC status Clear register, Address offset: 0x5C */ uint32_t RESERVED4[4];/*!< Reserved, Address offset: 0x58 */ __IO uint32_t ALRABINR;/*!< RTC alarm A binary mode register, Address offset: 0x70 */ __IO uint32_t ALRBBINR;/*!< RTC alarm B binary mode register, Address offset: 0x74 */ } RTC_TypeDef; /** * @brief Serial Peripheral Interface */ typedef struct { __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */ __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */ __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ } SPI_TypeDef; /** * @brief System configuration controller */ typedef struct { __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register Address offset: 0x00 */ __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ __IO uint32_t SCSR; /*!< SYSCFG SRAM2 control and status register, Address offset: 0x18 */ __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */ __IO uint32_t SWPR; /*!< SYSCFG SRAM2 write protection register part, Address offset: 0x20 */ __IO uint32_t SKR; /*!< SYSCFG SRAM2 key register, Address offset: 0x24 */ uint32_t RESERVED1[120]; /*!< Reserved, Address offset: 0x28-0x204 */ __IO uint32_t RFDCR; /*!< SYSCFG CPU2 radio debug control register, Address offset: 0x208 */ } SYSCFG_TypeDef; /** * @brief Tamper and backup registers */ typedef struct { __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ __IO uint32_t CR3; /*!< TAMP configuration register 3, Address offset: 0x08 */ __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ uint32_t RESERVED0[7];/*!< Reserved, Address offset: 0x10 */ __IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */ __IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */ __IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */ uint32_t RESERVED1; /*!< Reserved, Address offset: 0x38 */ __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ __IO uint32_t COUNTR; /*!< TAMP monotonic counter register, Address offset: 0x40 */ uint32_t RESERVED2[47];/*!< Reserved, Address offset: 0x54 - 0xFC */ __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ } TAMP_TypeDef; /** * @brief TIM */ typedef struct { __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ __IO uint32_t OR1; /*!< TIM option register Address offset: 0x50 */ __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ __IO uint32_t AF1; /*!< TIM Alternate function option register 1, Address offset: 0x60 */ __IO uint32_t AF2; /*!< TIM Alternate function option register 2, Address offset: 0x64 */ } TIM_TypeDef; /** * @brief Universal Synchronous Asynchronous Receiver Transmitter */ typedef struct { __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ } USART_TypeDef; /** * @brief VREFBUF */ typedef struct { __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ } VREFBUF_TypeDef; /** * @brief Window WATCHDOG */ typedef struct { __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ } WWDG_TypeDef; /** * @} */ /** @addtogroup Peripheral_memory_map * @{ */ /*!< Boundary memory map */ #define FLASH_BASE 0x08000000UL /*!< FLASH(up to 256 KB) base address */ #define SYSTEM_FLASH_BASE 0x1FFF0000UL /*!< System FLASH(28Kb) base address */ #define SRAM1_BASE 0x20000000UL /*!< SRAM1(up to 32 KB) base address */ #define SRAM2_BASE 0x20008000UL /*!< SRAM2(up to 32 KB) base address */ #define PERIPH_BASE 0x40000000UL /*!< Peripheral base address */ #define FLASH_SIZE (((*((uint32_t *)FLASHSIZE_BASE)) & 0xFFFFU) << 10U) #define SRAM1_SIZE 0x00008000UL /*!< SRAM1 default size : 32 kB */ #define SRAM2_SIZE 0x00008000UL /*!< SRAM2 default size : 32 kB */ /*!< Memory, OTP and Option bytes */ #define OTP_AREA_BASE (SYSTEM_FLASH_BASE + 0x00007000UL) /*!< OTP area : 1kB (0x1FFF7000 - 0x1FFF73FF) */ #define ENGI_BYTES_BASE (SYSTEM_FLASH_BASE + 0x00007400UL) /*!< Engi Bytes : 1kB (0x1FFF7400 - 0x1FFF77FF) */ #define OPTION_BYTES_BASE (SYSTEM_FLASH_BASE + 0x00007800UL) /*!< Option Bytes : 2kB (0x1FFF7800 - 0x1FFF7FFF) */ /*!< Device Electronic Signature */ #define PACKAGE_BASE (ENGI_BYTES_BASE + 0x00000100UL) /*!< Package data register base address */ #define UID64_BASE (ENGI_BYTES_BASE + 0x00000180UL) /*!< 64-bit Unique device Identification */ #define UID_BASE (ENGI_BYTES_BASE + 0x00000190UL) /*!< Unique device ID register base address */ #define FLASHSIZE_BASE (ENGI_BYTES_BASE + 0x000001E0UL) /*!< Flash size data register base address */ #define SYSTEM_MEMORY_END_ADDR (0x1FFF6FFFUL) /*!< System Memory : 28KB (0x1FFF0000 - 0x1FFF6FFF) */ #define OTP_AREA_END_ADDR (0x1FFF73FFUL) /*!< OTP area : 1KB (0x1FFF7000 - 0x1FFF73FF) */ #define ENGI_BYTE_END_ADDR (0x1FFF77FFUL) /*!< Engi Bytes : 1kB (0x1FFF7400 - 0x1FFF77FF) */ #define OPTION_BYTE_END_ADDR (0x1FFF7FFFUL) /*!< Option Bytes : 2KB (0x1FFF7800 - 0x1FFF7FFF) */ /*!< Peripheral memory map */ #define APB1PERIPH_BASE PERIPH_BASE #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) #define AHB3PERIPH_BASE (PERIPH_BASE + 0x18000000UL) #define APB3PERIPH_BASE (PERIPH_BASE + 0x18010000UL) /*!< APB1 peripherals */ #define TIM2_BASE (APB1PERIPH_BASE + 0x00000000UL) #define RTC_BASE (APB1PERIPH_BASE + 0x00002800UL) #define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00UL) #define IWDG_BASE (APB1PERIPH_BASE + 0x00003000UL) #define SPI2_BASE (APB1PERIPH_BASE + 0x00003800UL) #define USART2_BASE (APB1PERIPH_BASE + 0x00004400UL) #define I2C1_BASE (APB1PERIPH_BASE + 0x00005400UL) #define I2C2_BASE (APB1PERIPH_BASE + 0x00005800UL) #define I2C3_BASE (APB1PERIPH_BASE + 0x00005C00UL) #define DAC_BASE (APB1PERIPH_BASE + 0x00007400UL) #define LPTIM1_BASE (APB1PERIPH_BASE + 0x00007C00UL) #define LPUART1_BASE (APB1PERIPH_BASE + 0x00008000UL) #define LPTIM2_BASE (APB1PERIPH_BASE + 0x00009400UL) #define LPTIM3_BASE (APB1PERIPH_BASE + 0x00009800UL) #define TAMP_BASE (APB1PERIPH_BASE + 0x0000B000UL) /*!< APB2 peripherals */ #define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000UL) #define VREFBUF_BASE (APB2PERIPH_BASE + 0x00000030UL) #define COMP1_BASE (APB2PERIPH_BASE + 0x00000200UL) #define COMP2_BASE (APB2PERIPH_BASE + 0x00000204UL) #define ADC_BASE (APB2PERIPH_BASE + 0x00002400UL) #define ADC_COMMON_BASE (APB2PERIPH_BASE + 0x00002708UL) #define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00UL) #define SPI1_BASE (APB2PERIPH_BASE + 0x00003000UL) #define USART1_BASE (APB2PERIPH_BASE + 0x00003800UL) #define TIM16_BASE (APB2PERIPH_BASE + 0x00004400UL) #define TIM17_BASE (APB2PERIPH_BASE + 0x00004800UL) /*!< AHB1 peripherals */ #define DMA1_BASE (AHB1PERIPH_BASE + 0x00000000UL) #define DMA2_BASE (AHB1PERIPH_BASE + 0x00000400UL) #define DMAMUX1_BASE (AHB1PERIPH_BASE + 0x00000800UL) #define CRC_BASE (AHB1PERIPH_BASE + 0x00003000UL) #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL) #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL) #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL) #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL) #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL) #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL) #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL) #define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008UL) #define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001CUL) #define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030UL) #define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044UL) #define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058UL) #define DMA2_Channel6_BASE (DMA2_BASE + 0x0000006CUL) #define DMA2_Channel7_BASE (DMA2_BASE + 0x00000080UL) #define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) #define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x00000004UL) #define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x00000008UL) #define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x0000000CUL) #define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x00000010UL) #define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x00000014UL) #define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x00000018UL) #define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x0000001CUL) #define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x00000020UL) #define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x00000024UL) #define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x00000028UL) #define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x0000002CUL) #define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x00000030UL) #define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x00000034UL) #define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x00000100UL) #define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x00000104UL) #define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x00000108UL) #define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x0000010CUL) #define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x00000080UL) #define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x00000140UL) /*!< AHB2 peripherals */ #define IOPORT_BASE (AHB2PERIPH_BASE + 0x00000000UL) #define GPIOA_BASE (IOPORT_BASE + 0x00000000UL) #define GPIOB_BASE (IOPORT_BASE + 0x00000400UL) #define GPIOC_BASE (IOPORT_BASE + 0x00000800UL) #define GPIOH_BASE (IOPORT_BASE + 0x00001C00UL) /*!< AHB3 peripherals */ #define PWR_BASE (AHB3PERIPH_BASE + 0x00000400UL) #define EXTI_BASE (AHB3PERIPH_BASE + 0x00000800UL) #define RCC_BASE (AHB3PERIPH_BASE + 0x00000000UL) #define RNG_BASE (AHB3PERIPH_BASE + 0x00001000UL) #define HSEM_BASE (AHB3PERIPH_BASE + 0x00001400UL) #define AES_BASE (AHB3PERIPH_BASE + 0x00001800UL) #define PKA_BASE (AHB3PERIPH_BASE + 0x00002000UL) #define FLASH_REG_BASE (AHB3PERIPH_BASE + 0x00004000UL) /*!< APB3 peripherals */ #define SUBGHZSPI_BASE (APB3PERIPH_BASE + 0x00000000UL) /*!< Peripherals available on CPU1 external PPB bus */ #define DBGMCU_BASE (0xE0042000UL) /** * @} */ /** @addtogroup Peripheral_declaration * @{ */ /* Peripherals available on APB1 bus */ #define TIM2 ((TIM_TypeDef *) TIM2_BASE) #define IWDG ((IWDG_TypeDef *) IWDG_BASE) #define WWDG ((WWDG_TypeDef *) WWDG_BASE) #define DAC ((DAC_TypeDef *) DAC_BASE) #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) #define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE) #define LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE) #define RTC ((RTC_TypeDef *) RTC_BASE) #define SPI2 ((SPI_TypeDef *) SPI2_BASE) #define I2C1 ((I2C_TypeDef *) I2C1_BASE) #define I2C2 ((I2C_TypeDef *) I2C2_BASE) #define I2C3 ((I2C_TypeDef *) I2C3_BASE) #define TAMP ((TAMP_TypeDef *) TAMP_BASE) #define USART2 ((USART_TypeDef *) USART2_BASE) #define LPUART1 ((USART_TypeDef *) LPUART1_BASE) /* Peripherals available on APB2 bus */ #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) #define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE) #define COMP1 ((COMP_TypeDef *) COMP1_BASE) #define COMP2 ((COMP_TypeDef *) COMP2_BASE) #define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE) #define TIM1 ((TIM_TypeDef *) TIM1_BASE) #define SPI1 ((SPI_TypeDef *) SPI1_BASE) #define ADC ((ADC_TypeDef *) ADC_BASE) #define ADC_COMMON ((ADC_Common_TypeDef *) ADC_COMMON_BASE) #define TIM16 ((TIM_TypeDef *) TIM16_BASE) #define TIM17 ((TIM_TypeDef *) TIM17_BASE) #define USART1 ((USART_TypeDef *) USART1_BASE) /* Peripherals available on AHB1 bus */ #define DMA1 ((DMA_TypeDef *) DMA1_BASE) #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) #define DMA2 ((DMA_TypeDef *) DMA2_BASE) #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) #define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE) #define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE) #define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) #define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) #define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE) #define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE) #define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE) #define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE) #define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE) #define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE) #define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE) #define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE) #define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE) #define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE) #define DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE) #define DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE) #define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE) #define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE) #define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE) #define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE) #define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE) #define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE) #define CRC ((CRC_TypeDef *) CRC_BASE) /* Peripherals available on AHB2 bus */ #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) /* Peripherals available on AH3 bus */ #define AES ((AES_TypeDef *) AES_BASE) #define EXTI ((EXTI_TypeDef *) EXTI_BASE) #define RCC ((RCC_TypeDef *) RCC_BASE) #define PWR ((PWR_TypeDef *) PWR_BASE) #define RNG ((RNG_TypeDef *) RNG_BASE) #define HSEM ((HSEM_TypeDef *) HSEM_BASE) #define HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100U)) #define PKA ((PKA_TypeDef *) PKA_BASE) #define FLASH ((FLASH_TypeDef *) FLASH_REG_BASE) /* Peripherals available on APB3 bus */ #define SUBGHZSPI ((SPI_TypeDef *) SUBGHZSPI_BASE) /* Peripherals available on CPU1 external PPB bus */ #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) /** * @} */ /** @addtogroup Exported_constants * @{ */ /** @addtogroup Hardware_Constant_Definition * @{ */ #define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */ /** * @} */ /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ /******************************************************************************/ /* Peripheral Registers Bits Definition */ /******************************************************************************/ /******************************************************************************/ /* */ /* Analog to Digital Converter (ADC) */ /* */ /******************************************************************************/ /******************** Bit definition for ADC_ISR register *******************/ #define ADC_ISR_ADRDY_Pos (0U) #define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ #define ADC_ISR_EOSMP_Pos (1U) #define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ #define ADC_ISR_EOC_Pos (2U) #define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ #define ADC_ISR_EOS_Pos (3U) #define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ #define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ #define ADC_ISR_OVR_Pos (4U) #define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ #define ADC_ISR_AWD1_Pos (7U) #define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ #define ADC_ISR_AWD2_Pos (8U) #define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ #define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ #define ADC_ISR_AWD3_Pos (9U) #define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ #define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ #define ADC_ISR_EOCAL_Pos (11U) #define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */ #define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< ADC end of calibration flag */ #define ADC_ISR_CCRDY_Pos (13U) #define ADC_ISR_CCRDY_Msk (0x1UL << ADC_ISR_CCRDY_Pos) /*!< 0x00002000 */ #define ADC_ISR_CCRDY ADC_ISR_CCRDY_Msk /*!< ADC channel configuration ready flag */ /******************** Bit definition for ADC_IER register *******************/ #define ADC_IER_ADRDYIE_Pos (0U) #define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ #define ADC_IER_EOSMPIE_Pos (1U) #define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ #define ADC_IER_EOCIE_Pos (2U) #define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ #define ADC_IER_EOSIE_Pos (3U) #define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ #define ADC_IER_OVRIE_Pos (4U) #define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ #define ADC_IER_AWD1IE_Pos (7U) #define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ #define ADC_IER_AWD2IE_Pos (8U) #define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ #define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ #define ADC_IER_AWD3IE_Pos (9U) #define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ #define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ #define ADC_IER_EOCALIE_Pos (11U) #define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */ #define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< ADC end of calibration interrupt */ #define ADC_IER_CCRDYIE_Pos (13U) #define ADC_IER_CCRDYIE_Msk (0x1UL << ADC_IER_CCRDYIE_Pos) /*!< 0x00002000 */ #define ADC_IER_CCRDYIE ADC_IER_CCRDYIE_Msk /*!< ADC channel configuration ready interrupt */ /******************** Bit definition for ADC_CR register ********************/ #define ADC_CR_ADEN_Pos (0U) #define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ #define ADC_CR_ADDIS_Pos (1U) #define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ #define ADC_CR_ADSTART_Pos (2U) #define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ #define ADC_CR_ADSTP_Pos (4U) #define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ #define ADC_CR_ADVREGEN_Pos (28U) #define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ #define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ #define ADC_CR_ADCAL_Pos (31U) #define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ /******************** Bit definition for ADC_CFGR1 register *****************/ #define ADC_CFGR1_DMAEN_Pos (0U) #define ADC_CFGR1_DMAEN_Msk (0x1UL << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ #define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */ #define ADC_CFGR1_DMACFG_Pos (1U) #define ADC_CFGR1_DMACFG_Msk (0x1UL << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ #define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */ #define ADC_CFGR1_SCANDIR_Pos (2U) #define ADC_CFGR1_SCANDIR_Msk (0x1UL << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */ #define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */ #define ADC_CFGR1_RES_Pos (3U) #define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */ #define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC data resolution */ #define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ #define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */ #define ADC_CFGR1_ALIGN_Pos (5U) #define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ #define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignment */ #define ADC_CFGR1_EXTSEL_Pos (6U) #define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ #define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC group regular external trigger source */ #define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ #define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ #define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ #define ADC_CFGR1_EXTEN_Pos (10U) #define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ #define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC group regular external trigger polarity */ #define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ #define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ #define ADC_CFGR1_OVRMOD_Pos (12U) #define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ #define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC group regular overrun configuration */ #define ADC_CFGR1_CONT_Pos (13U) #define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ #define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC group regular continuous conversion mode */ #define ADC_CFGR1_WAIT_Pos (14U) #define ADC_CFGR1_WAIT_Msk (0x1UL << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */ #define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC low power auto wait */ #define ADC_CFGR1_AUTOFF_Pos (15U) #define ADC_CFGR1_AUTOFF_Msk (0x1UL << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */ #define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC low power auto power off */ #define ADC_CFGR1_DISCEN_Pos (16U) #define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ #define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ #define ADC_CFGR1_CHSELRMOD_Pos (21U) #define ADC_CFGR1_CHSELRMOD_Msk (0x1UL << ADC_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */ #define ADC_CFGR1_CHSELRMOD ADC_CFGR1_CHSELRMOD_Msk /*!< ADC group regular sequencer mode */ #define ADC_CFGR1_AWD1SGL_Pos (22U) #define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ #define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ #define ADC_CFGR1_AWD1EN_Pos (23U) #define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ #define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ #define ADC_CFGR1_AWD1CH_Pos (26U) #define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ #define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ #define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ #define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ #define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ #define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ #define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ /******************** Bit definition for ADC_CFGR2 register *****************/ #define ADC_CFGR2_OVSE_Pos (0U) #define ADC_CFGR2_OVSE_Msk (0x1UL << ADC_CFGR2_OVSE_Pos) /*!< 0x00000001 */ #define ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ #define ADC_CFGR2_OVSR_Pos (2U) #define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ #define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ #define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ #define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ #define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ #define ADC_CFGR2_OVSS_Pos (5U) #define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ #define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ #define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ #define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ #define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ #define ADC_CFGR2_TOVS_Pos (9U) #define ADC_CFGR2_TOVS_Msk (0x1UL << ADC_CFGR2_TOVS_Pos) /*!< 0x00000200 */ #define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ #define ADC_CFGR2_LFTRIG_Pos (29U) #define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */ #define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC low frequency trigger mode */ #define ADC_CFGR2_CKMODE_Pos (30U) #define ADC_CFGR2_CKMODE_Msk (0x3UL << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */ #define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< ADC clock source and prescaler (prescaler only for clock source synchronous) */ #define ADC_CFGR2_CKMODE_1 (0x2UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */ #define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */ /******************** Bit definition for ADC_SMPR register ******************/ #define ADC_SMPR_SMP1_Pos (0U) #define ADC_SMPR_SMP1_Msk (0x7UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000007 */ #define ADC_SMPR_SMP1 ADC_SMPR_SMP1_Msk /*!< ADC group of channels sampling time 1 */ #define ADC_SMPR_SMP1_0 (0x1UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000001 */ #define ADC_SMPR_SMP1_1 (0x2UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000002 */ #define ADC_SMPR_SMP1_2 (0x4UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000004 */ #define ADC_SMPR_SMP2_Pos (4U) #define ADC_SMPR_SMP2_Msk (0x7UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000070 */ #define ADC_SMPR_SMP2 ADC_SMPR_SMP2_Msk /*!< ADC group of channels sampling time 2 */ #define ADC_SMPR_SMP2_0 (0x1UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000010 */ #define ADC_SMPR_SMP2_1 (0x2UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000020 */ #define ADC_SMPR_SMP2_2 (0x4UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000040 */ #define ADC_SMPR_SMPSEL_Pos (8U) #define ADC_SMPR_SMPSEL_Msk (0x3FFFFUL << ADC_SMPR_SMPSEL_Pos) /*!< 0x03FFFF00 */ #define ADC_SMPR_SMPSEL ADC_SMPR_SMPSEL_Msk /*!< ADC all channels sampling time selection */ #define ADC_SMPR_SMPSEL0_Pos (8U) #define ADC_SMPR_SMPSEL0_Msk (0x1UL << ADC_SMPR_SMPSEL0_Pos) /*!< 0x00000100 */ #define ADC_SMPR_SMPSEL0 ADC_SMPR_SMPSEL0_Msk /*!< ADC channel 0 sampling time selection */ #define ADC_SMPR_SMPSEL1_Pos (9U) #define ADC_SMPR_SMPSEL1_Msk (0x1UL << ADC_SMPR_SMPSEL1_Pos) /*!< 0x00000200 */ #define ADC_SMPR_SMPSEL1 ADC_SMPR_SMPSEL1_Msk /*!< ADC channel 1 sampling time selection */ #define ADC_SMPR_SMPSEL2_Pos (10U) #define ADC_SMPR_SMPSEL2_Msk (0x1UL << ADC_SMPR_SMPSEL2_Pos) /*!< 0x00000400 */ #define ADC_SMPR_SMPSEL2 ADC_SMPR_SMPSEL2_Msk /*!< ADC channel 2 sampling time selection */ #define ADC_SMPR_SMPSEL3_Pos (11U) #define ADC_SMPR_SMPSEL3_Msk (0x1UL << ADC_SMPR_SMPSEL3_Pos) /*!< 0x00000800 */ #define ADC_SMPR_SMPSEL3 ADC_SMPR_SMPSEL3_Msk /*!< ADC channel 3 sampling time selection */ #define ADC_SMPR_SMPSEL4_Pos (12U) #define ADC_SMPR_SMPSEL4_Msk (0x1UL << ADC_SMPR_SMPSEL4_Pos) /*!< 0x00001000 */ #define ADC_SMPR_SMPSEL4 ADC_SMPR_SMPSEL4_Msk /*!< ADC channel 4 sampling time selection */ #define ADC_SMPR_SMPSEL5_Pos (13U) #define ADC_SMPR_SMPSEL5_Msk (0x1UL << ADC_SMPR_SMPSEL5_Pos) /*!< 0x00002000 */ #define ADC_SMPR_SMPSEL5 ADC_SMPR_SMPSEL5_Msk /*!< ADC channel 5 sampling time selection */ #define ADC_SMPR_SMPSEL6_Pos (14U) #define ADC_SMPR_SMPSEL6_Msk (0x1UL << ADC_SMPR_SMPSEL6_Pos) /*!< 0x00004000 */ #define ADC_SMPR_SMPSEL6 ADC_SMPR_SMPSEL6_Msk /*!< ADC channel 6 sampling time selection */ #define ADC_SMPR_SMPSEL7_Pos (15U) #define ADC_SMPR_SMPSEL7_Msk (0x1UL << ADC_SMPR_SMPSEL7_Pos) /*!< 0x00008000 */ #define ADC_SMPR_SMPSEL7 ADC_SMPR_SMPSEL7_Msk /*!< ADC channel 7 sampling time selection */ #define ADC_SMPR_SMPSEL8_Pos (16U) #define ADC_SMPR_SMPSEL8_Msk (0x1UL << ADC_SMPR_SMPSEL8_Pos) /*!< 0x00010000 */ #define ADC_SMPR_SMPSEL8 ADC_SMPR_SMPSEL8_Msk /*!< ADC channel 8 sampling time selection */ #define ADC_SMPR_SMPSEL9_Pos (17U) #define ADC_SMPR_SMPSEL9_Msk (0x1UL << ADC_SMPR_SMPSEL9_Pos) /*!< 0x00020000 */ #define ADC_SMPR_SMPSEL9 ADC_SMPR_SMPSEL9_Msk /*!< ADC channel 9 sampling time selection */ #define ADC_SMPR_SMPSEL10_Pos (18U) #define ADC_SMPR_SMPSEL10_Msk (0x1UL << ADC_SMPR_SMPSEL10_Pos) /*!< 0x00040000 */ #define ADC_SMPR_SMPSEL10 ADC_SMPR_SMPSEL10_Msk /*!< ADC channel 10 sampling time selection */ #define ADC_SMPR_SMPSEL11_Pos (19U) #define ADC_SMPR_SMPSEL11_Msk (0x1UL << ADC_SMPR_SMPSEL11_Pos) /*!< 0x00080000 */ #define ADC_SMPR_SMPSEL11 ADC_SMPR_SMPSEL11_Msk /*!< ADC channel 11 sampling time selection */ #define ADC_SMPR_SMPSEL12_Pos (20U) #define ADC_SMPR_SMPSEL12_Msk (0x1UL << ADC_SMPR_SMPSEL12_Pos) /*!< 0x00100000 */ #define ADC_SMPR_SMPSEL12 ADC_SMPR_SMPSEL12_Msk /*!< ADC channel 12 sampling time selection */ #define ADC_SMPR_SMPSEL13_Pos (21U) #define ADC_SMPR_SMPSEL13_Msk (0x1UL << ADC_SMPR_SMPSEL13_Pos) /*!< 0x00200000 */ #define ADC_SMPR_SMPSEL13 ADC_SMPR_SMPSEL13_Msk /*!< ADC channel 13 sampling time selection */ #define ADC_SMPR_SMPSEL14_Pos (22U) #define ADC_SMPR_SMPSEL14_Msk (0x1UL << ADC_SMPR_SMPSEL14_Pos) /*!< 0x00400000 */ #define ADC_SMPR_SMPSEL14 ADC_SMPR_SMPSEL14_Msk /*!< ADC channel 14 sampling time selection */ #define ADC_SMPR_SMPSEL15_Pos (23U) #define ADC_SMPR_SMPSEL15_Msk (0x1UL << ADC_SMPR_SMPSEL15_Pos) /*!< 0x00800000 */ #define ADC_SMPR_SMPSEL15 ADC_SMPR_SMPSEL15_Msk /*!< ADC channel 15 sampling time selection */ #define ADC_SMPR_SMPSEL16_Pos (24U) #define ADC_SMPR_SMPSEL16_Msk (0x1UL << ADC_SMPR_SMPSEL16_Pos) /*!< 0x01000000 */ #define ADC_SMPR_SMPSEL16 ADC_SMPR_SMPSEL16_Msk /*!< ADC channel 16 sampling time selection */ #define ADC_SMPR_SMPSEL17_Pos (25U) #define ADC_SMPR_SMPSEL17_Msk (0x1UL << ADC_SMPR_SMPSEL17_Pos) /*!< 0x02000000 */ #define ADC_SMPR_SMPSEL17 ADC_SMPR_SMPSEL17_Msk /*!< ADC channel 17 sampling time selection */ /******************** Bit definition for ADC_AWD1TR register ****************/ #define ADC_AWD1TR_LT1_Pos (0U) #define ADC_AWD1TR_LT1_Msk (0xFFFUL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000FFF */ #define ADC_AWD1TR_LT1 ADC_AWD1TR_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ #define ADC_AWD1TR_LT1_0 (0x001UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000001 */ #define ADC_AWD1TR_LT1_1 (0x002UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000002 */ #define ADC_AWD1TR_LT1_2 (0x004UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000004 */ #define ADC_AWD1TR_LT1_3 (0x008UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000008 */ #define ADC_AWD1TR_LT1_4 (0x010UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000010 */ #define ADC_AWD1TR_LT1_5 (0x020UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000020 */ #define ADC_AWD1TR_LT1_6 (0x040UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000040 */ #define ADC_AWD1TR_LT1_7 (0x080UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000080 */ #define ADC_AWD1TR_LT1_8 (0x100UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000100 */ #define ADC_AWD1TR_LT1_9 (0x200UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000200 */ #define ADC_AWD1TR_LT1_10 (0x400UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000400 */ #define ADC_AWD1TR_LT1_11 (0x800UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000800 */ #define ADC_AWD1TR_HT1_Pos (16U) #define ADC_AWD1TR_HT1_Msk (0xFFFUL << ADC_AWD1TR_HT1_Pos) /*!< 0x0FFF0000 */ #define ADC_AWD1TR_HT1 ADC_AWD1TR_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ #define ADC_AWD1TR_HT1_0 (0x001UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00010000 */ #define ADC_AWD1TR_HT1_1 (0x002UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00020000 */ #define ADC_AWD1TR_HT1_2 (0x004UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00040000 */ #define ADC_AWD1TR_HT1_3 (0x008UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00080000 */ #define ADC_AWD1TR_HT1_4 (0x010UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00100000 */ #define ADC_AWD1TR_HT1_5 (0x020UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00200000 */ #define ADC_AWD1TR_HT1_6 (0x040UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00400000 */ #define ADC_AWD1TR_HT1_7 (0x080UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00800000 */ #define ADC_AWD1TR_HT1_8 (0x100UL << ADC_AWD1TR_HT1_Pos) /*!< 0x01000000 */ #define ADC_AWD1TR_HT1_9 (0x200UL << ADC_AWD1TR_HT1_Pos) /*!< 0x02000000 */ #define ADC_AWD1TR_HT1_10 (0x400UL << ADC_AWD1TR_HT1_Pos) /*!< 0x04000000 */ #define ADC_AWD1TR_HT1_11 (0x800UL << ADC_AWD1TR_HT1_Pos) /*!< 0x08000000 */ /* Legacy definitions */ #define ADC_TR1_LT1 ADC_AWD1TR_LT1 #define ADC_TR1_LT1_0 ADC_AWD1TR_LT1_0 #define ADC_TR1_LT1_1 ADC_AWD1TR_LT1_1 #define ADC_TR1_LT1_2 ADC_AWD1TR_LT1_2 #define ADC_TR1_LT1_3 ADC_AWD1TR_LT1_3 #define ADC_TR1_LT1_4 ADC_AWD1TR_LT1_4 #define ADC_TR1_LT1_5 ADC_AWD1TR_LT1_5 #define ADC_TR1_LT1_6 ADC_AWD1TR_LT1_6 #define ADC_TR1_LT1_7 ADC_AWD1TR_LT1_7 #define ADC_TR1_LT1_8 ADC_AWD1TR_LT1_8 #define ADC_TR1_LT1_9 ADC_AWD1TR_LT1_9 #define ADC_TR1_LT1_10 ADC_AWD1TR_LT1_10 #define ADC_TR1_LT1_11 ADC_AWD1TR_LT1_11 #define ADC_TR1_HT1 ADC_AWD1TR_HT1 #define ADC_TR1_HT1_0 ADC_AWD1TR_HT1_0 #define ADC_TR1_HT1_1 ADC_AWD1TR_HT1_1 #define ADC_TR1_HT1_2 ADC_AWD1TR_HT1_2 #define ADC_TR1_HT1_3 ADC_AWD1TR_HT1_3 #define ADC_TR1_HT1_4 ADC_AWD1TR_HT1_4 #define ADC_TR1_HT1_5 ADC_AWD1TR_HT1_5 #define ADC_TR1_HT1_6 ADC_AWD1TR_HT1_6 #define ADC_TR1_HT1_7 ADC_AWD1TR_HT1_7 #define ADC_TR1_HT1_8 ADC_AWD1TR_HT1_8 #define ADC_TR1_HT1_9 ADC_AWD1TR_HT1_9 #define ADC_TR1_HT1_10 ADC_AWD1TR_HT1_10 #define ADC_TR1_HT1_11 ADC_AWD1TR_HT1_11 /******************** Bit definition for ADC_AWD2TR register *******************/ #define ADC_AWD2TR_LT2_Pos (0U) #define ADC_AWD2TR_LT2_Msk (0xFFFUL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000FFF */ #define ADC_AWD2TR_LT2 ADC_AWD2TR_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ #define ADC_AWD2TR_LT2_0 (0x001UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000001 */ #define ADC_AWD2TR_LT2_1 (0x002UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000002 */ #define ADC_AWD2TR_LT2_2 (0x004UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000004 */ #define ADC_AWD2TR_LT2_3 (0x008UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000008 */ #define ADC_AWD2TR_LT2_4 (0x010UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000010 */ #define ADC_AWD2TR_LT2_5 (0x020UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000020 */ #define ADC_AWD2TR_LT2_6 (0x040UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000040 */ #define ADC_AWD2TR_LT2_7 (0x080UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000080 */ #define ADC_AWD2TR_LT2_8 (0x100UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000100 */ #define ADC_AWD2TR_LT2_9 (0x200UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000200 */ #define ADC_AWD2TR_LT2_10 (0x400UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000400 */ #define ADC_AWD2TR_LT2_11 (0x800UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000800 */ #define ADC_AWD2TR_HT2_Pos (16U) #define ADC_AWD2TR_HT2_Msk (0xFFFUL << ADC_AWD2TR_HT2_Pos) /*!< 0x0FFF0000 */ #define ADC_AWD2TR_HT2 ADC_AWD2TR_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ #define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */ #define ADC_AWD2TR_HT2_1 (0x002UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00020000 */ #define ADC_AWD2TR_HT2_2 (0x004UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00040000 */ #define ADC_AWD2TR_HT2_3 (0x008UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00080000 */ #define ADC_AWD2TR_HT2_4 (0x010UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00100000 */ #define ADC_AWD2TR_HT2_5 (0x020UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00200000 */ #define ADC_AWD2TR_HT2_6 (0x040UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00400000 */ #define ADC_AWD2TR_HT2_7 (0x080UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00800000 */ #define ADC_AWD2TR_HT2_8 (0x100UL << ADC_AWD2TR_HT2_Pos) /*!< 0x01000000 */ #define ADC_AWD2TR_HT2_9 (0x200UL << ADC_AWD2TR_HT2_Pos) /*!< 0x02000000 */ #define ADC_AWD2TR_HT2_10 (0x400UL << ADC_AWD2TR_HT2_Pos) /*!< 0x04000000 */ #define ADC_AWD2TR_HT2_11 (0x800UL << ADC_AWD2TR_HT2_Pos) /*!< 0x08000000 */ /* Legacy definitions */ #define ADC_TR2_LT2 ADC_AWD2TR_LT2 #define ADC_TR2_LT2_0 ADC_AWD2TR_LT2_0 #define ADC_TR2_LT2_1 ADC_AWD2TR_LT2_1 #define ADC_TR2_LT2_2 ADC_AWD2TR_LT2_2 #define ADC_TR2_LT2_3 ADC_AWD2TR_LT2_3 #define ADC_TR2_LT2_4 ADC_AWD2TR_LT2_4 #define ADC_TR2_LT2_5 ADC_AWD2TR_LT2_5 #define ADC_TR2_LT2_6 ADC_AWD2TR_LT2_6 #define ADC_TR2_LT2_7 ADC_AWD2TR_LT2_7 #define ADC_TR2_LT2_8 ADC_AWD2TR_LT2_8 #define ADC_TR2_LT2_9 ADC_AWD2TR_LT2_9 #define ADC_TR2_LT2_10 ADC_AWD2TR_LT2_10 #define ADC_TR2_LT2_11 ADC_AWD2TR_LT2_11 #define ADC_TR2_HT2 ADC_AWD2TR_HT2 #define ADC_TR2_HT2_0 ADC_AWD2TR_HT2_0 #define ADC_TR2_HT2_1 ADC_AWD2TR_HT2_1 #define ADC_TR2_HT2_2 ADC_AWD2TR_HT2_2 #define ADC_TR2_HT2_3 ADC_AWD2TR_HT2_3 #define ADC_TR2_HT2_4 ADC_AWD2TR_HT2_4 #define ADC_TR2_HT2_5 ADC_AWD2TR_HT2_5 #define ADC_TR2_HT2_6 ADC_AWD2TR_HT2_6 #define ADC_TR2_HT2_7 ADC_AWD2TR_HT2_7 #define ADC_TR2_HT2_8 ADC_AWD2TR_HT2_8 #define ADC_TR2_HT2_9 ADC_AWD2TR_HT2_9 #define ADC_TR2_HT2_10 ADC_AWD2TR_HT2_10 #define ADC_TR2_HT2_11 ADC_AWD2TR_HT2_11 /******************** Bit definition for ADC_CHSELR register ****************/ #define ADC_CHSELR_CHSEL_Pos (0U) #define ADC_CHSELR_CHSEL_Msk (0x3FFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0003FFFF */ #define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */ #define ADC_CHSELR_CHSEL17_Pos (17U) #define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */ #define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */ #define ADC_CHSELR_CHSEL16_Pos (16U) #define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */ #define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */ #define ADC_CHSELR_CHSEL15_Pos (15U) #define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */ #define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */ #define ADC_CHSELR_CHSEL14_Pos (14U) #define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */ #define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */ #define ADC_CHSELR_CHSEL13_Pos (13U) #define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */ #define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */ #define ADC_CHSELR_CHSEL12_Pos (12U) #define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ #define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */ #define ADC_CHSELR_CHSEL11_Pos (11U) #define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ #define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */ #define ADC_CHSELR_CHSEL10_Pos (10U) #define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */ #define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */ #define ADC_CHSELR_CHSEL9_Pos (9U) #define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ #define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */ #define ADC_CHSELR_CHSEL8_Pos (8U) #define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ #define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */ #define ADC_CHSELR_CHSEL7_Pos (7U) #define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ #define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */ #define ADC_CHSELR_CHSEL6_Pos (6U) #define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ #define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */ #define ADC_CHSELR_CHSEL5_Pos (5U) #define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ #define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */ #define ADC_CHSELR_CHSEL4_Pos (4U) #define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ #define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */ #define ADC_CHSELR_CHSEL3_Pos (3U) #define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ #define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */ #define ADC_CHSELR_CHSEL2_Pos (2U) #define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ #define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */ #define ADC_CHSELR_CHSEL1_Pos (1U) #define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ #define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */ #define ADC_CHSELR_CHSEL0_Pos (0U) #define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ #define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */ #define ADC_CHSELR_SQ_ALL_Pos (0U) #define ADC_CHSELR_SQ_ALL_Msk (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */ #define ADC_CHSELR_SQ_ALL ADC_CHSELR_SQ_ALL_Msk /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */ #define ADC_CHSELR_SQ8_Pos (28U) #define ADC_CHSELR_SQ8_Msk (0xFUL << ADC_CHSELR_SQ8_Pos) /*!< 0xF0000000 */ #define ADC_CHSELR_SQ8 ADC_CHSELR_SQ8_Msk /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */ #define ADC_CHSELR_SQ8_0 (0x1UL << ADC_CHSELR_SQ8_Pos) /*!< 0x10000000 */ #define ADC_CHSELR_SQ8_1 (0x2UL << ADC_CHSELR_SQ8_Pos) /*!< 0x20000000 */ #define ADC_CHSELR_SQ8_2 (0x4UL << ADC_CHSELR_SQ8_Pos) /*!< 0x40000000 */ #define ADC_CHSELR_SQ8_3 (0x8UL << ADC_CHSELR_SQ8_Pos) /*!< 0x80000000 */ #define ADC_CHSELR_SQ7_Pos (24U) #define ADC_CHSELR_SQ7_Msk (0xFUL << ADC_CHSELR_SQ7_Pos) /*!< 0x0F000000 */ #define ADC_CHSELR_SQ7 ADC_CHSELR_SQ7_Msk /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */ #define ADC_CHSELR_SQ7_0 (0x1UL << ADC_CHSELR_SQ7_Pos) /*!< 0x01000000 */ #define ADC_CHSELR_SQ7_1 (0x2UL << ADC_CHSELR_SQ7_Pos) /*!< 0x02000000 */ #define ADC_CHSELR_SQ7_2 (0x4UL << ADC_CHSELR_SQ7_Pos) /*!< 0x04000000 */ #define ADC_CHSELR_SQ7_3 (0x8UL << ADC_CHSELR_SQ7_Pos) /*!< 0x08000000 */ #define ADC_CHSELR_SQ6_Pos (20U) #define ADC_CHSELR_SQ6_Msk (0xFUL << ADC_CHSELR_SQ6_Pos) /*!< 0x00F00000 */ #define ADC_CHSELR_SQ6 ADC_CHSELR_SQ6_Msk /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */ #define ADC_CHSELR_SQ6_0 (0x1UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00100000 */ #define ADC_CHSELR_SQ6_1 (0x2UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00200000 */ #define ADC_CHSELR_SQ6_2 (0x4UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00400000 */ #define ADC_CHSELR_SQ6_3 (0x8UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00800000 */ #define ADC_CHSELR_SQ5_Pos (16U) #define ADC_CHSELR_SQ5_Msk (0xFUL << ADC_CHSELR_SQ5_Pos) /*!< 0x000F0000 */ #define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */ #define ADC_CHSELR_SQ5_0 (0x1UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00010000 */ #define ADC_CHSELR_SQ5_1 (0x2UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00020000 */ #define ADC_CHSELR_SQ5_2 (0x4UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00040000 */ #define ADC_CHSELR_SQ5_3 (0x8UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00080000 */ #define ADC_CHSELR_SQ4_Pos (12U) #define ADC_CHSELR_SQ4_Msk (0xFUL << ADC_CHSELR_SQ4_Pos) /*!< 0x0000F000 */ #define ADC_CHSELR_SQ4 ADC_CHSELR_SQ4_Msk /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */ #define ADC_CHSELR_SQ4_0 (0x1UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00001000 */ #define ADC_CHSELR_SQ4_1 (0x2UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00002000 */ #define ADC_CHSELR_SQ4_2 (0x4UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00004000 */ #define ADC_CHSELR_SQ4_3 (0x8UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00008000 */ #define ADC_CHSELR_SQ3_Pos (8U) #define ADC_CHSELR_SQ3_Msk (0xFUL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000F00 */ #define ADC_CHSELR_SQ3 ADC_CHSELR_SQ3_Msk /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */ #define ADC_CHSELR_SQ3_0 (0x1UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000100 */ #define ADC_CHSELR_SQ3_1 (0x2UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000200 */ #define ADC_CHSELR_SQ3_2 (0x4UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000400 */ #define ADC_CHSELR_SQ3_3 (0x8UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000800 */ #define ADC_CHSELR_SQ2_Pos (4U) #define ADC_CHSELR_SQ2_Msk (0xFUL << ADC_CHSELR_SQ2_Pos) /*!< 0x000000F0 */ #define ADC_CHSELR_SQ2 ADC_CHSELR_SQ2_Msk /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */ #define ADC_CHSELR_SQ2_0 (0x1UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000010 */ #define ADC_CHSELR_SQ2_1 (0x2UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000020 */ #define ADC_CHSELR_SQ2_2 (0x4UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000040 */ #define ADC_CHSELR_SQ2_3 (0x8UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000080 */ #define ADC_CHSELR_SQ1_Pos (0U) #define ADC_CHSELR_SQ1_Msk (0xFUL << ADC_CHSELR_SQ1_Pos) /*!< 0x0000000F */ #define ADC_CHSELR_SQ1 ADC_CHSELR_SQ1_Msk /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */ #define ADC_CHSELR_SQ1_0 (0x1UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000001 */ #define ADC_CHSELR_SQ1_1 (0x2UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000002 */ #define ADC_CHSELR_SQ1_2 (0x4UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000004 */ #define ADC_CHSELR_SQ1_3 (0x8UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000008 */ /******************** Bit definition for ADC_AWD3TR register *******************/ #define ADC_AWD3TR_LT3_Pos (0U) #define ADC_AWD3TR_LT3_Msk (0xFFFUL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000FFF */ #define ADC_AWD3TR_LT3 ADC_AWD3TR_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ #define ADC_AWD3TR_LT3_0 (0x001UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000001 */ #define ADC_AWD3TR_LT3_1 (0x002UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000002 */ #define ADC_AWD3TR_LT3_2 (0x004UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000004 */ #define ADC_AWD3TR_LT3_3 (0x008UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000008 */ #define ADC_AWD3TR_LT3_4 (0x010UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000010 */ #define ADC_AWD3TR_LT3_5 (0x020UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000020 */ #define ADC_AWD3TR_LT3_6 (0x040UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000040 */ #define ADC_AWD3TR_LT3_7 (0x080UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000080 */ #define ADC_AWD3TR_LT3_8 (0x100UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000100 */ #define ADC_AWD3TR_LT3_9 (0x200UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000200 */ #define ADC_AWD3TR_LT3_10 (0x400UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000400 */ #define ADC_AWD3TR_LT3_11 (0x800UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000800 */ #define ADC_AWD3TR_HT3_Pos (16U) #define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */ #define ADC_AWD3TR_HT3 ADC_AWD3TR_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ #define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */ #define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */ #define ADC_AWD3TR_HT3_2 (0x004UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00040000 */ #define ADC_AWD3TR_HT3_3 (0x008UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00080000 */ #define ADC_AWD3TR_HT3_4 (0x010UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00100000 */ #define ADC_AWD3TR_HT3_5 (0x020UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00200000 */ #define ADC_AWD3TR_HT3_6 (0x040UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00400000 */ #define ADC_AWD3TR_HT3_7 (0x080UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00800000 */ #define ADC_AWD3TR_HT3_8 (0x100UL << ADC_AWD3TR_HT3_Pos) /*!< 0x01000000 */ #define ADC_AWD3TR_HT3_9 (0x200UL << ADC_AWD3TR_HT3_Pos) /*!< 0x02000000 */ #define ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos) /*!< 0x04000000 */ #define ADC_AWD3TR_HT3_11 (0x800UL << ADC_AWD3TR_HT3_Pos) /*!< 0x08000000 */ /* Legacy definitions */ #define ADC_TR3_LT3 ADC_AWD3TR_LT3 #define ADC_TR3_LT3_0 ADC_AWD3TR_LT3_0 #define ADC_TR3_LT3_1 ADC_AWD3TR_LT3_1 #define ADC_TR3_LT3_2 ADC_AWD3TR_LT3_2 #define ADC_TR3_LT3_3 ADC_AWD3TR_LT3_3 #define ADC_TR3_LT3_4 ADC_AWD3TR_LT3_4 #define ADC_TR3_LT3_5 ADC_AWD3TR_LT3_5 #define ADC_TR3_LT3_6 ADC_AWD3TR_LT3_6 #define ADC_TR3_LT3_7 ADC_AWD3TR_LT3_7 #define ADC_TR3_LT3_8 ADC_AWD3TR_LT3_8 #define ADC_TR3_LT3_9 ADC_AWD3TR_LT3_9 #define ADC_TR3_LT3_10 ADC_AWD3TR_LT3_10 #define ADC_TR3_LT3_11 ADC_AWD3TR_LT3_11 #define ADC_TR3_HT3 ADC_AWD3TR_HT3 #define ADC_TR3_HT3_0 ADC_AWD3TR_HT3_0 #define ADC_TR3_HT3_1 ADC_AWD3TR_HT3_1 #define ADC_TR3_HT3_2 ADC_AWD3TR_HT3_2 #define ADC_TR3_HT3_3 ADC_AWD3TR_HT3_3 #define ADC_TR3_HT3_4 ADC_AWD3TR_HT3_4 #define ADC_TR3_HT3_5 ADC_AWD3TR_HT3_5 #define ADC_TR3_HT3_6 ADC_AWD3TR_HT3_6 #define ADC_TR3_HT3_7 ADC_AWD3TR_HT3_7 #define ADC_TR3_HT3_8 ADC_AWD3TR_HT3_8 #define ADC_TR3_HT3_9 ADC_AWD3TR_HT3_9 #define ADC_TR3_HT3_10 ADC_AWD3TR_HT3_10 #define ADC_TR3_HT3_11 ADC_AWD3TR_HT3_11 /******************** Bit definition for ADC_DR register ********************/ #define ADC_DR_DATA_Pos (0U) #define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ #define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */ #define ADC_DR_DATA_0 (0x0001UL << ADC_DR_DATA_Pos) /*!< 0x00000001 */ #define ADC_DR_DATA_1 (0x0002UL << ADC_DR_DATA_Pos) /*!< 0x00000002 */ #define ADC_DR_DATA_2 (0x0004UL << ADC_DR_DATA_Pos) /*!< 0x00000004 */ #define ADC_DR_DATA_3 (0x0008UL << ADC_DR_DATA_Pos) /*!< 0x00000008 */ #define ADC_DR_DATA_4 (0x0010UL << ADC_DR_DATA_Pos) /*!< 0x00000010 */ #define ADC_DR_DATA_5 (0x0020UL << ADC_DR_DATA_Pos) /*!< 0x00000020 */ #define ADC_DR_DATA_6 (0x0040UL << ADC_DR_DATA_Pos) /*!< 0x00000040 */ #define ADC_DR_DATA_7 (0x0080UL << ADC_DR_DATA_Pos) /*!< 0x00000080 */ #define ADC_DR_DATA_8 (0x0100UL << ADC_DR_DATA_Pos) /*!< 0x00000100 */ #define ADC_DR_DATA_9 (0x0200UL << ADC_DR_DATA_Pos) /*!< 0x00000200 */ #define ADC_DR_DATA_10 (0x0400UL << ADC_DR_DATA_Pos) /*!< 0x00000400 */ #define ADC_DR_DATA_11 (0x0800UL << ADC_DR_DATA_Pos) /*!< 0x00000800 */ #define ADC_DR_DATA_12 (0x1000UL << ADC_DR_DATA_Pos) /*!< 0x00001000 */ #define ADC_DR_DATA_13 (0x2000UL << ADC_DR_DATA_Pos) /*!< 0x00002000 */ #define ADC_DR_DATA_14 (0x4000UL << ADC_DR_DATA_Pos) /*!< 0x00004000 */ #define ADC_DR_DATA_15 (0x8000UL << ADC_DR_DATA_Pos) /*!< 0x00008000 */ /******************** Bit definition for ADC_AWD2CR register ****************/ #define ADC_AWD2CR_AWD2CH_Pos (0U) #define ADC_AWD2CR_AWD2CH_Msk (0x3FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0003FFFF */ #define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ #define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ #define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ #define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ #define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ #define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ #define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ #define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ #define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ #define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ #define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ #define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ #define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ #define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ #define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ #define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ #define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ #define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ #define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ /******************** Bit definition for ADC_AWD3CR register ****************/ #define ADC_AWD3CR_AWD3CH_Pos (0U) #define ADC_AWD3CR_AWD3CH_Msk (0x3FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0003FFFF */ #define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ #define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ #define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ #define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ #define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ #define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ #define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ #define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ #define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ #define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ #define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ #define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ #define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ #define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ #define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ #define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ #define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ #define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ #define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ /******************** Bit definition for ADC_CALFACT register ***************/ #define ADC_CALFACT_CALFACT_Pos (0U) #define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ #define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */ #define ADC_CALFACT_CALFACT_0 (0x01UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000001 */ #define ADC_CALFACT_CALFACT_1 (0x02UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000002 */ #define ADC_CALFACT_CALFACT_2 (0x04UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000004 */ #define ADC_CALFACT_CALFACT_3 (0x08UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000008 */ #define ADC_CALFACT_CALFACT_4 (0x10UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000010 */ #define ADC_CALFACT_CALFACT_5 (0x20UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000020 */ #define ADC_CALFACT_CALFACT_6 (0x40UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000040 */ /************************* ADC Common registers *****************************/ /******************** Bit definition for ADC_CCR register *******************/ #define ADC_CCR_PRESC_Pos (18U) #define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ #define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ #define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ #define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ #define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ #define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ #define ADC_CCR_VREFEN_Pos (22U) #define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ #define ADC_CCR_TSEN_Pos (23U) #define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ #define ADC_CCR_VBATEN_Pos (24U) #define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ /******************************************************************************/ /* */ /* Analog Comparators (COMP) */ /* */ /******************************************************************************/ /********************** Bit definition for COMP_CSR register ****************/ #define COMP_CSR_EN_Pos (0U) #define COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos) /*!< 0x00000001 */ #define COMP_CSR_EN COMP_CSR_EN_Msk /*!< Comparator enable */ #define COMP_CSR_PWRMODE_Pos (2U) #define COMP_CSR_PWRMODE_Msk (0x3UL << COMP_CSR_PWRMODE_Pos) /*!< 0x0000000C */ #define COMP_CSR_PWRMODE COMP_CSR_PWRMODE_Msk /*!< Comparator power mode */ #define COMP_CSR_PWRMODE_0 (0x1UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00000004 */ #define COMP_CSR_PWRMODE_1 (0x2UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00000008 */ #define COMP_CSR_INMSEL_Pos (4U) #define COMP_CSR_INMSEL_Msk (0x7UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000070 */ #define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< Comparator input minus selection */ #define COMP_CSR_INMSEL_0 (0x1UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000010 */ #define COMP_CSR_INMSEL_1 (0x2UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000020 */ #define COMP_CSR_INMSEL_2 (0x4UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000040 */ #define COMP_CSR_INPSEL_Pos (7U) #define COMP_CSR_INPSEL_Msk (0x3UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000180 */ #define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< Comparator input plus selection */ #define COMP_CSR_INPSEL_0 (0x1UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000080 */ #define COMP_CSR_INPSEL_1 (0x2UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000100 */ #define COMP_CSR_WINMODE_Pos (9U) #define COMP_CSR_WINMODE_Msk (0x1UL << COMP_CSR_WINMODE_Pos) /*!< 0x00000200 */ #define COMP_CSR_WINMODE COMP_CSR_WINMODE_Msk /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */ #define COMP_CSR_POLARITY_Pos (15U) #define COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos) /*!< 0x00008000 */ #define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< Comparator output polarity */ #define COMP_CSR_HYST_Pos (16U) #define COMP_CSR_HYST_Msk (0x3UL << COMP_CSR_HYST_Pos) /*!< 0x00030000 */ #define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< Comparator hysteresis */ #define COMP_CSR_HYST_0 (0x1UL << COMP_CSR_HYST_Pos) /*!< 0x00010000 */ #define COMP_CSR_HYST_1 (0x2UL << COMP_CSR_HYST_Pos) /*!< 0x00020000 */ #define COMP_CSR_BLANKING_Pos (18U) #define COMP_CSR_BLANKING_Msk (0x7UL << COMP_CSR_BLANKING_Pos) /*!< 0x001C0000 */ #define COMP_CSR_BLANKING COMP_CSR_BLANKING_Msk /*!< Comparator blanking source */ #define COMP_CSR_BLANKING_0 (0x1UL << COMP_CSR_BLANKING_Pos) /*!< 0x00040000 */ #define COMP_CSR_BLANKING_1 (0x2UL << COMP_CSR_BLANKING_Pos) /*!< 0x00080000 */ #define COMP_CSR_BLANKING_2 (0x4UL << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */ #define COMP_CSR_BRGEN_Pos (22U) #define COMP_CSR_BRGEN_Msk (0x1UL << COMP_CSR_BRGEN_Pos) /*!< 0x00400000 */ #define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk /*!< Comparator voltage scaler enable */ #define COMP_CSR_SCALEN_Pos (23U) #define COMP_CSR_SCALEN_Msk (0x1UL << COMP_CSR_SCALEN_Pos) /*!< 0x00800000 */ #define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk /*!< Comparator scaler bridge enable */ #define COMP_CSR_INMESEL_Pos (25U) #define COMP_CSR_INMESEL_Msk (0x3UL << COMP_CSR_INMESEL_Pos) /*!< 0x06000000 */ #define COMP_CSR_INMESEL COMP_CSR_INMESEL_Msk /*!< Comparator input minus extended selection */ #define COMP_CSR_INMESEL_0 (0x1UL << COMP_CSR_INMESEL_Pos) /*!< 0x02000000 */ #define COMP_CSR_INMESEL_1 (0x2UL << COMP_CSR_INMESEL_Pos) /*!< 0x04000000 */ #define COMP_CSR_VALUE_Pos (30U) #define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */ #define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< Comparator output level */ #define COMP_CSR_LOCK_Pos (31U) #define COMP_CSR_LOCK_Msk (0x1UL << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */ #define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< Comparator lock */ /******************************************************************************/ /* */ /* Digital to Analog Converter */ /* */ /******************************************************************************/ /* * @brief Specific device feature definitions */ /******************** Bit definition for DAC_CR register ********************/ #define DAC_CR_EN1_Pos (0U) #define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/ #define DAC_CR_CEN1_Pos (14U) #define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ #define DAC_SWTRIGR_SWTRIG1_Pos (0U) #define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!>2) /*!< Input modulus number of bits */ #define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ /* Compute Montgomery parameter output data */ #define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x594U - PKA_RAM_OFFSET)>>2) /*!< Output Montgomery parameter */ /* Compute modular exponentiation input data */ #define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */ #define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ #define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x594U - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ #define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ #define PKA_MODULAR_EXP_IN_EXPONENT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process */ #define PKA_MODULAR_EXP_IN_MODULUS ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ /* Compute modular exponentiation output data */ #define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x594U - PKA_RAM_OFFSET)>>2) /*!< Output storage area for Montgomery parameter */ #define PKA_MODULAR_EXP_OUT_SM_ALGO_ACC1 ((0x724U - PKA_RAM_OFFSET)>>2) /*!< Output SM algorithm accumulator 1 */ #define PKA_MODULAR_EXP_OUT_SM_ALGO_ACC2 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Output SM algorithm accumulator 2 */ #define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Output base of the exponentiation */ #define PKA_MODULAR_EXP_OUT_SM_ALGO_ACC3 ((0xE3CU - PKA_RAM_OFFSET)>>2) /*!< Output SM algorithm accumulator 3 */ /* Compute ECC scalar multiplication input data */ #define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */ #define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ #define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x408U - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ #define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x40CU - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ #define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x460U - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ #define PKA_ECC_SCALAR_MUL_IN_MONTGOMERY_PARAM ((0x4B4U - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ #define PKA_ECC_SCALAR_MUL_IN_K ((0x508U - PKA_RAM_OFFSET)>>2) /*!< Input 'k' of KP */ #define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x55CU - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ #define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ /* Compute ECC scalar multiplication output data */ #define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x55CU - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ #define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ #define PKA_ECC_SCALAR_MUL_OUT_LAST_DOUBLE_X1 ((0xDE8U - PKA_RAM_OFFSET)>>2) /*!< Output last double X1 coordinate */ #define PKA_ECC_SCALAR_MUL_OUT_LAST_DOUBLE_Y1 ((0xE3CU - PKA_RAM_OFFSET)>>2) /*!< Output last double Y1 coordinate */ #define PKA_ECC_SCALAR_MUL_OUT_LAST_DOUBLE_Z1 ((0xE90U - PKA_RAM_OFFSET)>>2) /*!< Output last double Z1 coordinate */ #define PKA_ECC_SCALAR_MUL_OUT_CHECK_POINT_X2 ((0xEE4U - PKA_RAM_OFFSET)>>2) /*!< Output check point X2 coordinate */ #define PKA_ECC_SCALAR_MUL_OUT_CHECK_POINT_Y2 ((0xF38U - PKA_RAM_OFFSET)>>2) /*!< Output check point Y2 coordinate */ #define PKA_ECC_SCALAR_MUL_OUT_CHECK_POINT_Z2 ((0xF8CU - PKA_RAM_OFFSET)>>2) /*!< Output check point Z2 coordinate */ /* Point check input data */ #define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ #define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x408U - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ #define PKA_POINT_CHECK_IN_A_COEFF ((0x40CU - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ #define PKA_POINT_CHECK_IN_B_COEFF ((0x7FCU - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ #define PKA_POINT_CHECK_IN_MOD_GF ((0x460U - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ #define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x55CU - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ #define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ /* Point check output data */ #define PKA_POINT_CHECK_OUT_ERROR ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Output error */ /* ECDSA signature input data */ #define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ #define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ #define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x408U - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ #define PKA_ECDSA_SIGN_IN_A_COEFF ((0x40CU - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ #define PKA_ECDSA_SIGN_IN_MOD_GF ((0x460U - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ #define PKA_ECDSA_SIGN_IN_K ((0x508U - PKA_RAM_OFFSET)>>2) /*!< Input k value of the ECDSA */ #define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x55CU - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ #define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ #define PKA_ECDSA_SIGN_IN_HASH_E ((0xDE8U - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ #define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0xE3CU - PKA_RAM_OFFSET)>>2) /*!< Input d, private key */ #define PKA_ECDSA_SIGN_IN_ORDER_N ((0xE94U - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ /* ECDSA signature output data */ #define PKA_ECDSA_SIGN_OUT_ERROR ((0xEE8U - PKA_RAM_OFFSET)>>2) /*!< Output error */ #define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x700U - PKA_RAM_OFFSET)>>2) /*!< Output signature r */ #define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x754U - PKA_RAM_OFFSET)>>2) /*!< Output signature s */ #define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x103CU - PKA_RAM_OFFSET)>>2) /*!< Output final point kP X coordinate */ #define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1090U - PKA_RAM_OFFSET)>>2) /*!< Output final point kP Y coordinate */ /* ECDSA verification input data */ #define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ #define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x4B4U - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ #define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x45CU - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ #define PKA_ECDSA_VERIF_IN_A_COEFF ((0x460U - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ #define PKA_ECDSA_VERIF_IN_MOD_GF ((0x4B8U - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ #define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x5E8U - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ #define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x63CU - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ #define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0xF40U - PKA_RAM_OFFSET)>>2) /*!< Input public key point X coordinate */ #define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0xF94U - PKA_RAM_OFFSET)>>2) /*!< Input public key point Y coordinate */ #define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x1098U - PKA_RAM_OFFSET)>>2) /*!< Input r, part of the signature */ #define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input s, part of the signature */ #define PKA_ECDSA_VERIF_IN_HASH_E ((0xFE8U - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ #define PKA_ECDSA_VERIF_IN_ORDER_N ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ /* ECDSA verification output data */ #define PKA_ECDSA_VERIF_OUT_RESULT ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ /* RSA CRT exponentiation input data */ #define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operands number of bits */ #define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x65CU - PKA_RAM_OFFSET)>>2) /*!< Input Dp CRT parameter */ #define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Input Dq CRT parameter */ #define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x7ECU - PKA_RAM_OFFSET)>>2) /*!< Input qInv CRT parameter */ #define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x97CU - PKA_RAM_OFFSET)>>2) /*!< Input Prime p */ #define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input Prime q */ #define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0xEECU - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ /* RSA CRT exponentiation output data */ #define PKA_RSA_CRT_EXP_OUT_RESULT ((0x724U - PKA_RAM_OFFSET)>>2) /*!< Output result */ /* Modular reduction input data */ #define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Input operand length */ #define PKA_MODULAR_REDUC_IN_OPERAND ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand */ #define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input modulus length */ #define PKA_MODULAR_REDUC_IN_MODULUS ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ /* Modular reduction output data */ #define PKA_MODULAR_REDUC_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ /* Arithmetic addition input data */ #define PKA_ARITHMETIC_ADD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ #define PKA_ARITHMETIC_ADD_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ #define PKA_ARITHMETIC_ADD_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ /* Arithmetic addition output data */ #define PKA_ARITHMETIC_ADD_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ /* Arithmetic subtraction input data */ #define PKA_ARITHMETIC_SUB_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ #define PKA_ARITHMETIC_SUB_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ #define PKA_ARITHMETIC_SUB_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ /* Arithmetic subtraction output data */ #define PKA_ARITHMETIC_SUB_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ /* Arithmetic multiplication input data */ #define PKA_ARITHMETIC_MUL_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ #define PKA_ARITHMETIC_MUL_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ #define PKA_ARITHMETIC_MUL_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ /* Arithmetic multiplication output data */ #define PKA_ARITHMETIC_MUL_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ /* Comparison input data */ #define PKA_COMPARISON_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ #define PKA_COMPARISON_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ #define PKA_COMPARISON_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ /* Comparison output data */ #define PKA_COMPARISON_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ /* Modular addition input data */ #define PKA_MODULAR_ADD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ #define PKA_MODULAR_ADD_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ #define PKA_MODULAR_ADD_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ #define PKA_MODULAR_ADD_IN_OP3_MOD ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 (modulus) */ /* Modular addition output data */ #define PKA_MODULAR_ADD_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ /* Modular inversion input data */ #define PKA_MODULAR_INV_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ #define PKA_MODULAR_INV_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ #define PKA_MODULAR_INV_IN_OP2_MOD ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 (modulus) */ /* Modular inversion output data */ #define PKA_MODULAR_INV_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ /* Modular subtraction input data */ #define PKA_MODULAR_SUB_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ #define PKA_MODULAR_SUB_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ #define PKA_MODULAR_SUB_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ #define PKA_MODULAR_SUB_IN_OP3_MOD ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ /* Modular subtraction output data */ #define PKA_MODULAR_SUB_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ /* Montgomery multiplication input data */ #define PKA_MONTGOMERY_MUL_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ #define PKA_MONTGOMERY_MUL_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ #define PKA_MONTGOMERY_MUL_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ #define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ /* Montgomery multiplication output data */ #define PKA_MONTGOMERY_MUL_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ /* Generic Arithmetic input data */ #define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ #define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ #define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ #define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ /* Generic Arithmetic output data */ #define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ /******************************************************************************/ /* */ /* Power Control */ /* */ /******************************************************************************/ /******************** Bit definition for PWR_CR1 register ********************/ #define PWR_CR1_LPMS_Pos (0U) #define PWR_CR1_LPMS_Msk (0x7UL << PWR_CR1_LPMS_Pos) /*!< 0x00000007 */ #define PWR_CR1_LPMS PWR_CR1_LPMS_Msk /*!< Low Power Mode Selection for CPU1 */ #define PWR_CR1_LPMS_0 (0x1UL << PWR_CR1_LPMS_Pos) /*!< 0x00000001 */ #define PWR_CR1_LPMS_1 (0x2UL << PWR_CR1_LPMS_Pos) /*!< 0x00000002 */ #define PWR_CR1_LPMS_2 (0x4UL << PWR_CR1_LPMS_Pos) /*!< 0x00000004 */ #define PWR_CR1_SUBGHZSPINSSSEL_Pos (3U) #define PWR_CR1_SUBGHZSPINSSSEL_Msk (0x1UL << PWR_CR1_SUBGHZSPINSSSEL_Pos) /*!< 0x00000008 */ #define PWR_CR1_SUBGHZSPINSSSEL PWR_CR1_SUBGHZSPINSSSEL_Msk /*!< Sub-GHz radio SPI NSS source select */ #define PWR_CR1_FPDR_Pos (4U) #define PWR_CR1_FPDR_Msk (0x1UL << PWR_CR1_FPDR_Pos) /*!< 0x00000010 */ #define PWR_CR1_FPDR PWR_CR1_FPDR_Msk /*!< Flash power down mode during LPrun for CPU1 */ #define PWR_CR1_FPDS_Pos (5U) #define PWR_CR1_FPDS_Msk (0x1UL << PWR_CR1_FPDS_Pos) /*!< 0x00000020 */ #define PWR_CR1_FPDS PWR_CR1_FPDS_Msk /*!< Flash power down mode during LPsleep for CPU1 */ #define PWR_CR1_DBP_Pos (8U) #define PWR_CR1_DBP_Msk (0x1UL << PWR_CR1_DBP_Pos) /*!< 0x00000100 */ #define PWR_CR1_DBP PWR_CR1_DBP_Msk /*!< Disable Backup Domain write protection */ #define PWR_CR1_VOS_Pos (9U) #define PWR_CR1_VOS_Msk (0x3UL << PWR_CR1_VOS_Pos) /*!< 0x00000600 */ #define PWR_CR1_VOS PWR_CR1_VOS_Msk /*!< Voltage scaling range selection */ #define PWR_CR1_VOS_0 (0x1UL << PWR_CR1_VOS_Pos) /*!< 0x00000200 */ #define PWR_CR1_VOS_1 (0x2UL << PWR_CR1_VOS_Pos) /*!< 0x00000400 */ #define PWR_CR1_LPR_Pos (14U) #define PWR_CR1_LPR_Msk (0x1UL << PWR_CR1_LPR_Pos) /*!< 0x00004000 */ #define PWR_CR1_LPR PWR_CR1_LPR_Msk /*!< Regulator Low-Power Run mode */ /******************** Bit definition for PWR_CR2 register ********************/ #define PWR_CR2_PVDE_Pos (0U) #define PWR_CR2_PVDE_Msk (0x1UL << PWR_CR2_PVDE_Pos) /*!< 0x00000001 */ #define PWR_CR2_PVDE PWR_CR2_PVDE_Msk /*!< Power voltage detector enable */ #define PWR_CR2_PLS_Pos (1U) #define PWR_CR2_PLS_Msk (0x7UL << PWR_CR2_PLS_Pos) /*!< 0x0000000E */ #define PWR_CR2_PLS PWR_CR2_PLS_Msk /*!< Power voltage detector level selection */ #define PWR_CR2_PLS_0 (0x1UL << PWR_CR2_PLS_Pos) /*!< 0x00000002 */ #define PWR_CR2_PLS_1 (0x2UL << PWR_CR2_PLS_Pos) /*!< 0x00000004 */ #define PWR_CR2_PLS_2 (0x4UL << PWR_CR2_PLS_Pos) /*!< 0x00000008 */ #define PWR_CR2_PVME3_Pos (6U) #define PWR_CR2_PVME3_Msk (0x1UL << PWR_CR2_PVME3_Pos) /*!< 0x00000040 */ #define PWR_CR2_PVME3 PWR_CR2_PVME3_Msk /*!< Peripherical Voltage Monitor Vdda Enable */ /******************** Bit definition for PWR_CR3 register ********************/ #define PWR_CR3_EWUP_Pos (0U) #define PWR_CR3_EWUP_Msk (0x07UL << PWR_CR3_EWUP_Pos) /*!< 0x00000007 */ #define PWR_CR3_EWUP PWR_CR3_EWUP_Msk /*!< Enable all external Wake-Up lines */ #define PWR_CR3_EWUP1_Pos (0U) #define PWR_CR3_EWUP1_Msk (0x1UL << PWR_CR3_EWUP1_Pos) /*!< 0x00000001 */ #define PWR_CR3_EWUP1 PWR_CR3_EWUP1_Msk /*!< Enable external WKUP Pin 1 [line 0] */ #define PWR_CR3_EWUP2_Pos (1U) #define PWR_CR3_EWUP2_Msk (0x1UL << PWR_CR3_EWUP2_Pos) /*!< 0x00000002 */ #define PWR_CR3_EWUP2 PWR_CR3_EWUP2_Msk /*!< Enable external WKUP Pin 2 [line 1] */ #define PWR_CR3_EWUP3_Pos (2U) #define PWR_CR3_EWUP3_Msk (0x1UL << PWR_CR3_EWUP3_Pos) /*!< 0x00000004 */ #define PWR_CR3_EWUP3 PWR_CR3_EWUP3_Msk /*!< Enable external WKUP Pin 3 [line 2] */ #define PWR_CR3_ULPEN_Pos (7U) #define PWR_CR3_ULPEN_Msk (0x1UL << PWR_CR3_ULPEN_Pos) /*!< 0x00000080 */ #define PWR_CR3_ULPEN PWR_CR3_ULPEN_Msk /*!< Enable periodical sampling of supply voltage in Stop and Standby modes for detecting condition of PDR and BOR reset */ #define PWR_CR3_EWPVD_Pos (8U) #define PWR_CR3_EWPVD_Msk (0x1UL << PWR_CR3_EWPVD_Pos) /*!< 0x00000100 */ #define PWR_CR3_EWPVD PWR_CR3_EWPVD_Msk /*!< Enable wakeup PVD for CPU1 */ #define PWR_CR3_RRS_Pos (9U) #define PWR_CR3_RRS_Msk (0x1UL << PWR_CR3_RRS_Pos) /*!< 0x00000200 */ #define PWR_CR3_RRS PWR_CR3_RRS_Msk /*!< SRAM2 retention in STANDBY mode */ #define PWR_CR3_APC_Pos (10U) #define PWR_CR3_APC_Msk (0x1UL << PWR_CR3_APC_Pos) /*!< 0x00000400 */ #define PWR_CR3_APC PWR_CR3_APC_Msk /*!< Apply pull-up and pull-down configuration for CPU1 */ #define PWR_CR3_EWRFBUSY_Pos (11U) #define PWR_CR3_EWRFBUSY_Msk (0x1UL << PWR_CR3_EWRFBUSY_Pos) /*!< 0x00008000 */ #define PWR_CR3_EWRFBUSY PWR_CR3_EWRFBUSY_Msk /*!< Enable Radio busy IRQ and wake-up for CPU1 */ #define PWR_CR3_EWRFIRQ_Pos (13U) #define PWR_CR3_EWRFIRQ_Msk (0x1UL << PWR_CR3_EWRFIRQ_Pos) /*!< 0x00020000 */ #define PWR_CR3_EWRFIRQ PWR_CR3_EWRFIRQ_Msk /*!< Enable Radio IRQ[2:0] and wake-up for CPU1 */ #define PWR_CR3_EIWUL_Pos (15U) #define PWR_CR3_EIWUL_Msk (0x1UL << PWR_CR3_EIWUL_Pos) /*!< 0x00080000 */ #define PWR_CR3_EIWUL PWR_CR3_EIWUL_Msk /*!< Internal Wake-Up line interrupt for CPU1 */ /******************** Bit definition for PWR_CR4 register ********************/ #define PWR_CR4_WP1_Pos (0U) #define PWR_CR4_WP1_Msk (0x1UL << PWR_CR4_WP1_Pos) /*!< 0x00000001 */ #define PWR_CR4_WP1 PWR_CR4_WP1_Msk /*!< Wake-Up Pin 1 [line 0] polarity */ #define PWR_CR4_WP2_Pos (1U) #define PWR_CR4_WP2_Msk (0x1UL << PWR_CR4_WP2_Pos) /*!< 0x00000002 */ #define PWR_CR4_WP2 PWR_CR4_WP2_Msk /*!< Wake-Up Pin 2 [line 1] polarity */ #define PWR_CR4_WP3_Pos (2U) #define PWR_CR4_WP3_Msk (0x1UL << PWR_CR4_WP3_Pos) /*!< 0x00000004 */ #define PWR_CR4_WP3 PWR_CR4_WP3_Msk /*!< Wake-Up Pin 3 [line 2] polarity */ #define PWR_CR4_VBE_Pos (8U) #define PWR_CR4_VBE_Msk (0x1UL << PWR_CR4_VBE_Pos) /*!< 0x00000100 */ #define PWR_CR4_VBE PWR_CR4_VBE_Msk /*!< VBAT battery charging enable */ #define PWR_CR4_VBRS_Pos (9U) #define PWR_CR4_VBRS_Msk (0x1UL << PWR_CR4_VBRS_Pos) /*!< 0x00000200 */ #define PWR_CR4_VBRS PWR_CR4_VBRS_Msk /*!< VBAT battery charging resistor selection */ #define PWR_CR4_WRFBUSYP_Pos (11U) #define PWR_CR4_WRFBUSYP_Msk (0x1UL << PWR_CR4_WRFBUSYP_Pos) /*!< 0x00008000 */ #define PWR_CR4_WRFBUSYP PWR_CR4_WRFBUSYP_Msk /*!< Wake-up radio busy polarity */ /******************** Bit definition for PWR_SR1 register ********************/ #define PWR_SR1_WUF_Pos (0U) #define PWR_SR1_WUF_Msk (0x1FUL << PWR_SR1_WUF_Pos) /*!< 0x00000007 */ #define PWR_SR1_WUF PWR_SR1_WUF_Msk /*!< Wakeup Flags of all pins */ #define PWR_SR1_WUF1_Pos (0U) #define PWR_SR1_WUF1_Msk (0x1UL << PWR_SR1_WUF1_Pos) /*!< 0x00000001 */ #define PWR_SR1_WUF1 PWR_SR1_WUF1_Msk /*!< Wakeup Pin 1 [Flag 0] */ #define PWR_SR1_WUF2_Pos (1U) #define PWR_SR1_WUF2_Msk (0x1UL << PWR_SR1_WUF2_Pos) /*!< 0x00000002 */ #define PWR_SR1_WUF2 PWR_SR1_WUF2_Msk /*!< Wakeup Pin 2 [Flag 1] */ #define PWR_SR1_WUF3_Pos (2U) #define PWR_SR1_WUF3_Msk (0x1UL << PWR_SR1_WUF3_Pos) /*!< 0x00000004 */ #define PWR_SR1_WUF3 PWR_SR1_WUF3_Msk /*!< Wakeup Pin 3 [Flag 2] */ #define PWR_SR1_WPVDF_Pos (8U) #define PWR_SR1_WPVDF_Msk (0x1UL << PWR_SR1_WPVDF_Pos) /*!< 0x00000100 */ #define PWR_SR1_WPVDF PWR_SR1_WPVDF_Msk /*!< Wakeup PVD flag */ #define PWR_SR1_WRFBUSYF_Pos (11U) #define PWR_SR1_WRFBUSYF_Msk (0x1UL << PWR_SR1_WRFBUSYF_Pos) /*!< 0x00000800 */ #define PWR_SR1_WRFBUSYF PWR_SR1_WRFBUSYF_Msk /*!< Wakeup radio busy flag */ #define PWR_SR1_WUFI_Pos (15U) #define PWR_SR1_WUFI_Msk (0x1UL << PWR_SR1_WUFI_Pos) /*!< 0x00008000 */ #define PWR_SR1_WUFI PWR_SR1_WUFI_Msk /*!< Internal wakeup interrupt flag */ /******************** Bit definition for PWR_SR2 register ********************/ #define PWR_SR2_RFBUSYS_Pos (1U) #define PWR_SR2_RFBUSYS_Msk (0x1UL << PWR_SR2_RFBUSYS_Pos) /*!< 0x00000002 */ #define PWR_SR2_RFBUSYS PWR_SR2_RFBUSYS_Msk /*!< Radio busy signal status */ #define PWR_SR2_RFBUSYMS_Pos (2U) #define PWR_SR2_RFBUSYMS_Msk (0x1UL << PWR_SR2_RFBUSYMS_Pos) /*!< 0x00000004 */ #define PWR_SR2_RFBUSYMS PWR_SR2_RFBUSYMS_Msk /*!< Radio busy masked signal status */ #define PWR_SR2_SMPSRDY_Pos (3U) #define PWR_SR2_SMPSRDY_Msk (0x1UL << PWR_SR2_SMPSRDY_Pos) /*!< 0x00000008 */ #define PWR_SR2_SMPSRDY PWR_SR2_SMPSRDY_Msk /*!< SMPS ready flag */ #define PWR_SR2_LDORDY_Pos (4U) #define PWR_SR2_LDORDY_Msk (0x1UL << PWR_SR2_LDORDY_Pos) /*!< 0x00000010 */ #define PWR_SR2_LDORDY PWR_SR2_LDORDY_Msk /*!< LDO ready flag */ #define PWR_SR2_RFEOLF_Pos (5U) #define PWR_SR2_RFEOLF_Msk (0x1UL << PWR_SR2_RFEOLF_Pos) /*!< 0x00000020 */ #define PWR_SR2_RFEOLF PWR_SR2_RFEOLF_Msk /*!< Radio end of life flag */ #define PWR_SR2_REGMRS_Pos (6U) #define PWR_SR2_REGMRS_Msk (0x1UL << PWR_SR2_REGMRS_Pos) /*!< 0x00000040 */ #define PWR_SR2_REGMRS PWR_SR2_REGMRS_Msk /*!< Main regulator status */ #define PWR_SR2_FLASHRDY_Pos (7U) #define PWR_SR2_FLASHRDY_Msk (0x1UL << PWR_SR2_FLASHRDY_Pos) /*!< 0x00000080 */ #define PWR_SR2_FLASHRDY PWR_SR2_FLASHRDY_Msk /*!< Flash ready */ #define PWR_SR2_REGLPS_Pos (8U) #define PWR_SR2_REGLPS_Msk (0x1UL << PWR_SR2_REGLPS_Pos) /*!< 0x00000100 */ #define PWR_SR2_REGLPS PWR_SR2_REGLPS_Msk /*!< Low-power regulator ready */ #define PWR_SR2_REGLPF_Pos (9U) #define PWR_SR2_REGLPF_Msk (0x1UL << PWR_SR2_REGLPF_Pos) /*!< 0x00000200 */ #define PWR_SR2_REGLPF PWR_SR2_REGLPF_Msk /*!< Low-power regulator being used */ #define PWR_SR2_VOSF_Pos (10U) #define PWR_SR2_VOSF_Msk (0x1UL << PWR_SR2_VOSF_Pos) /*!< 0x00000400 */ #define PWR_SR2_VOSF PWR_SR2_VOSF_Msk /*!< Voltage scaling flag */ #define PWR_SR2_PVDO_Pos (11U) #define PWR_SR2_PVDO_Msk (0x1UL << PWR_SR2_PVDO_Pos) /*!< 0x00000800 */ #define PWR_SR2_PVDO PWR_SR2_PVDO_Msk /*!< Power voltage detector output */ #define PWR_SR2_PVMO3_Pos (14U) #define PWR_SR2_PVMO3_Msk (0x1UL << PWR_SR2_PVMO3_Pos) /*!< 0x00004000 */ #define PWR_SR2_PVMO3 PWR_SR2_PVMO3_Msk /*!< Peripheral voltage monitor output 3: VDDA vs. 1.62V */ /******************** Bit definition for PWR_SCR register ********************/ #define PWR_SCR_CWUF_Pos (0U) #define PWR_SCR_CWUF_Msk (0x7UL << PWR_SCR_CWUF_Pos) /*!< 0x00000007 */ #define PWR_SCR_CWUF PWR_SCR_CWUF_Msk /*!< Clear Wake-up Flags for all pins */ #define PWR_SCR_CWUF1_Pos (0U) #define PWR_SCR_CWUF1_Msk (0x1UL << PWR_SCR_CWUF1_Pos) /*!< 0x00000001 */ #define PWR_SCR_CWUF1 PWR_SCR_CWUF1_Msk /*!< Clear Wake-up Pin 1 [Flag 0] */ #define PWR_SCR_CWUF2_Pos (1U) #define PWR_SCR_CWUF2_Msk (0x1UL << PWR_SCR_CWUF2_Pos) /*!< 0x00000002 */ #define PWR_SCR_CWUF2 PWR_SCR_CWUF2_Msk /*!< Clear Wake-up Pin 2 [Flag 1] */ #define PWR_SCR_CWUF3_Pos (2U) #define PWR_SCR_CWUF3_Msk (0x1UL << PWR_SCR_CWUF3_Pos) /*!< 0x00000004 */ #define PWR_SCR_CWUF3 PWR_SCR_CWUF3_Msk /*!< Clear Wake-up Pin 3 [Flag 2] */ #define PWR_SCR_CWPVDF_Pos (8U) #define PWR_SCR_CWPVDF_Msk (0x1UL << PWR_SCR_CWPVDF_Pos) /*!< 0x00000100 */ #define PWR_SCR_CWPVDF PWR_SCR_CWPVDF_Msk /*!< Clear wakeup PVD interrupt flag */ #define PWR_SCR_CWRFBUSYF_Pos (11U) #define PWR_SCR_CWRFBUSYF_Msk (0x1UL << PWR_SCR_CWRFBUSYF_Pos) /*!< 0x00000800 */ #define PWR_SCR_CWRFBUSYF PWR_SCR_CWRFBUSYF_Msk /*!< Clear Radio busy interrupt flag */ /******************** Bit definition for PWR_CR5 register ********************/ #define PWR_CR5_RFEOLEN_Pos (14U) #define PWR_CR5_RFEOLEN_Msk (0x1UL << PWR_CR5_RFEOLEN_Pos) /*!< 0x00004000 */ #define PWR_CR5_RFEOLEN PWR_CR5_RFEOLEN_Msk /*!< Enable Radio End Of Life detector enabled */ #define PWR_CR5_SMPSEN_Pos (15U) #define PWR_CR5_SMPSEN_Msk (0x1UL << PWR_CR5_SMPSEN_Pos) /*!< 0x00008000 */ #define PWR_CR5_SMPSEN PWR_CR5_SMPSEN_Msk /*!< Enable SMPS Step Down converter SMPS mode enable */ /******************** Bit definition for PWR_PUCRA register *****************/ #define PWR_PUCRA_PA0_Pos (0U) #define PWR_PUCRA_PA0_Msk (0x1UL << PWR_PUCRA_PA0_Pos) /*!< 0x00000001 */ #define PWR_PUCRA_PA0 PWR_PUCRA_PA0_Msk /*!< Pin PA0 Pull-Up set */ #define PWR_PUCRA_PA1_Pos (1U) #define PWR_PUCRA_PA1_Msk (0x1UL << PWR_PUCRA_PA1_Pos) /*!< 0x00000002 */ #define PWR_PUCRA_PA1 PWR_PUCRA_PA1_Msk /*!< Pin PA1 Pull-Up set */ #define PWR_PUCRA_PA2_Pos (2U) #define PWR_PUCRA_PA2_Msk (0x1UL << PWR_PUCRA_PA2_Pos) /*!< 0x00000004 */ #define PWR_PUCRA_PA2 PWR_PUCRA_PA2_Msk /*!< Pin PA2 Pull-Up set */ #define PWR_PUCRA_PA3_Pos (3U) #define PWR_PUCRA_PA3_Msk (0x1UL << PWR_PUCRA_PA3_Pos) /*!< 0x00000008 */ #define PWR_PUCRA_PA3 PWR_PUCRA_PA3_Msk /*!< Pin PA3 Pull-Up set */ #define PWR_PUCRA_PA4_Pos (4U) #define PWR_PUCRA_PA4_Msk (0x1UL << PWR_PUCRA_PA4_Pos) /*!< 0x00000010 */ #define PWR_PUCRA_PA4 PWR_PUCRA_PA4_Msk /*!< Pin PA4 Pull-Up set */ #define PWR_PUCRA_PA5_Pos (5U) #define PWR_PUCRA_PA5_Msk (0x1UL << PWR_PUCRA_PA5_Pos) /*!< 0x00000020 */ #define PWR_PUCRA_PA5 PWR_PUCRA_PA5_Msk /*!< Pin PA5 Pull-Up set */ #define PWR_PUCRA_PA6_Pos (6U) #define PWR_PUCRA_PA6_Msk (0x1UL << PWR_PUCRA_PA6_Pos) /*!< 0x00000040 */ #define PWR_PUCRA_PA6 PWR_PUCRA_PA6_Msk /*!< Pin PA6 Pull-Up set */ #define PWR_PUCRA_PA7_Pos (7U) #define PWR_PUCRA_PA7_Msk (0x1UL << PWR_PUCRA_PA7_Pos) /*!< 0x00000080 */ #define PWR_PUCRA_PA7 PWR_PUCRA_PA7_Msk /*!< Pin PA7 Pull-Up set */ #define PWR_PUCRA_PA8_Pos (8U) #define PWR_PUCRA_PA8_Msk (0x1UL << PWR_PUCRA_PA8_Pos) /*!< 0x00000100 */ #define PWR_PUCRA_PA8 PWR_PUCRA_PA8_Msk /*!< Pin PA8 Pull-Up set */ #define PWR_PUCRA_PA9_Pos (9U) #define PWR_PUCRA_PA9_Msk (0x1UL << PWR_PUCRA_PA9_Pos) /*!< 0x00000200 */ #define PWR_PUCRA_PA9 PWR_PUCRA_PA9_Msk /*!< Pin PA9 Pull-Up set */ #define PWR_PUCRA_PA10_Pos (10U) #define PWR_PUCRA_PA10_Msk (0x1UL << PWR_PUCRA_PA10_Pos) /*!< 0x00000400 */ #define PWR_PUCRA_PA10 PWR_PUCRA_PA10_Msk /*!< Pin PA10 Pull-Up set */ #define PWR_PUCRA_PA11_Pos (11U) #define PWR_PUCRA_PA11_Msk (0x1UL << PWR_PUCRA_PA11_Pos) /*!< 0x00000800 */ #define PWR_PUCRA_PA11 PWR_PUCRA_PA11_Msk /*!< Pin PA11 Pull-Up set */ #define PWR_PUCRA_PA12_Pos (12U) #define PWR_PUCRA_PA12_Msk (0x1UL << PWR_PUCRA_PA12_Pos) /*!< 0x00001000 */ #define PWR_PUCRA_PA12 PWR_PUCRA_PA12_Msk /*!< Pin PA12 Pull-Up set */ #define PWR_PUCRA_PA13_Pos (13U) #define PWR_PUCRA_PA13_Msk (0x1UL << PWR_PUCRA_PA13_Pos) /*!< 0x00002000 */ #define PWR_PUCRA_PA13 PWR_PUCRA_PA13_Msk /*!< Pin PA13 Pull-Up set */ #define PWR_PUCRA_PA14_Pos (14U) #define PWR_PUCRA_PA14_Msk (0x1UL << PWR_PUCRA_PA14_Pos) /*!< 0x00004000 */ #define PWR_PUCRA_PA14 PWR_PUCRA_PA14_Msk /*!< Pin PA14 Pull-Up set */ #define PWR_PUCRA_PA15_Pos (15U) #define PWR_PUCRA_PA15_Msk (0x1UL << PWR_PUCRA_PA15_Pos) /*!< 0x00008000 */ #define PWR_PUCRA_PA15 PWR_PUCRA_PA15_Msk /*!< Pin PA15 Pull-Up set */ /******************** Bit definition for PWR_PDCRA register *****************/ #define PWR_PDCRA_PA0_Pos (0U) #define PWR_PDCRA_PA0_Msk (0x1UL << PWR_PDCRA_PA0_Pos) /*!< 0x00000001 */ #define PWR_PDCRA_PA0 PWR_PDCRA_PA0_Msk /*!< Pin PA0 Pull-Down set */ #define PWR_PDCRA_PA1_Pos (1U) #define PWR_PDCRA_PA1_Msk (0x1UL << PWR_PDCRA_PA1_Pos) /*!< 0x00000002 */ #define PWR_PDCRA_PA1 PWR_PDCRA_PA1_Msk /*!< Pin PA1 Pull-Down set */ #define PWR_PDCRA_PA2_Pos (2U) #define PWR_PDCRA_PA2_Msk (0x1UL << PWR_PDCRA_PA2_Pos) /*!< 0x00000004 */ #define PWR_PDCRA_PA2 PWR_PDCRA_PA2_Msk /*!< Pin PA2 Pull-Down set */ #define PWR_PDCRA_PA3_Pos (3U) #define PWR_PDCRA_PA3_Msk (0x1UL << PWR_PDCRA_PA3_Pos) /*!< 0x00000008 */ #define PWR_PDCRA_PA3 PWR_PDCRA_PA3_Msk /*!< Pin PA3 Pull-Down set */ #define PWR_PDCRA_PA4_Pos (4U) #define PWR_PDCRA_PA4_Msk (0x1UL << PWR_PDCRA_PA4_Pos) /*!< 0x00000010 */ #define PWR_PDCRA_PA4 PWR_PDCRA_PA4_Msk /*!< Pin PA4 Pull-Down set */ #define PWR_PDCRA_PA5_Pos (5U) #define PWR_PDCRA_PA5_Msk (0x1UL << PWR_PDCRA_PA5_Pos) /*!< 0x00000020 */ #define PWR_PDCRA_PA5 PWR_PDCRA_PA5_Msk /*!< Pin PA5 Pull-Down set */ #define PWR_PDCRA_PA6_Pos (6U) #define PWR_PDCRA_PA6_Msk (0x1UL << PWR_PDCRA_PA6_Pos) /*!< 0x00000040 */ #define PWR_PDCRA_PA6 PWR_PDCRA_PA6_Msk /*!< Pin PA6 Pull-Down set */ #define PWR_PDCRA_PA7_Pos (7U) #define PWR_PDCRA_PA7_Msk (0x1UL << PWR_PDCRA_PA7_Pos) /*!< 0x00000080 */ #define PWR_PDCRA_PA7 PWR_PDCRA_PA7_Msk /*!< Pin PA7 Pull-Down set */ #define PWR_PDCRA_PA8_Pos (8U) #define PWR_PDCRA_PA8_Msk (0x1UL << PWR_PDCRA_PA8_Pos) /*!< 0x00000100 */ #define PWR_PDCRA_PA8 PWR_PDCRA_PA8_Msk /*!< Pin PA8 Pull-Down set */ #define PWR_PDCRA_PA9_Pos (9U) #define PWR_PDCRA_PA9_Msk (0x1UL << PWR_PDCRA_PA9_Pos) /*!< 0x00000200 */ #define PWR_PDCRA_PA9 PWR_PDCRA_PA9_Msk /*!< Pin PA9 Pull-Down set */ #define PWR_PDCRA_PA10_Pos (10U) #define PWR_PDCRA_PA10_Msk (0x1UL << PWR_PDCRA_PA10_Pos) /*!< 0x00000400 */ #define PWR_PDCRA_PA10 PWR_PDCRA_PA10_Msk /*!< Pin PA10 Pull-Down set */ #define PWR_PDCRA_PA11_Pos (11U) #define PWR_PDCRA_PA11_Msk (0x1UL << PWR_PDCRA_PA11_Pos) /*!< 0x00000800 */ #define PWR_PDCRA_PA11 PWR_PDCRA_PA11_Msk /*!< Pin PA11 Pull-Down set */ #define PWR_PDCRA_PA12_Pos (12U) #define PWR_PDCRA_PA12_Msk (0x1UL << PWR_PDCRA_PA12_Pos) /*!< 0x00001000 */ #define PWR_PDCRA_PA12 PWR_PDCRA_PA12_Msk /*!< Pin PA12 Pull-Down set */ #define PWR_PDCRA_PA13_Pos (13U) #define PWR_PDCRA_PA13_Msk (0x1UL << PWR_PDCRA_PA13_Pos) /*!< 0x00002000 */ #define PWR_PDCRA_PA13 PWR_PDCRA_PA13_Msk /*!< Pin PA13 Pull-Down set */ #define PWR_PDCRA_PA14_Pos (14U) #define PWR_PDCRA_PA14_Msk (0x1UL << PWR_PDCRA_PA14_Pos) /*!< 0x00004000 */ #define PWR_PDCRA_PA14 PWR_PDCRA_PA14_Msk /*!< Pin PA14 Pull-Down set */ #define PWR_PDCRA_PA15_Pos (15U) #define PWR_PDCRA_PA15_Msk (0x1UL << PWR_PDCRA_PA15_Pos) /*!< 0x00008000 */ #define PWR_PDCRA_PA15 PWR_PDCRA_PA15_Msk /*!< Pin PA15 Pull-Down set */ /******************** Bit definition for PWR_PUCRB register *****************/ #define PWR_PUCRB_PB0_Pos (0U) #define PWR_PUCRB_PB0_Msk (0x1UL << PWR_PUCRB_PB0_Pos) /*!< 0x00000001 */ #define PWR_PUCRB_PB0 PWR_PUCRB_PB0_Msk /*!< Pin PB0 Pull-Up set */ #define PWR_PUCRB_PB1_Pos (1U) #define PWR_PUCRB_PB1_Msk (0x1UL << PWR_PUCRB_PB1_Pos) /*!< 0x00000002 */ #define PWR_PUCRB_PB1 PWR_PUCRB_PB1_Msk /*!< Pin PB1 Pull-Up set */ #define PWR_PUCRB_PB2_Pos (2U) #define PWR_PUCRB_PB2_Msk (0x1UL << PWR_PUCRB_PB2_Pos) /*!< 0x00000004 */ #define PWR_PUCRB_PB2 PWR_PUCRB_PB2_Msk /*!< Pin PB2 Pull-Up set */ #define PWR_PUCRB_PB3_Pos (3U) #define PWR_PUCRB_PB3_Msk (0x1UL << PWR_PUCRB_PB3_Pos) /*!< 0x00000008 */ #define PWR_PUCRB_PB3 PWR_PUCRB_PB3_Msk /*!< Pin PB3 Pull-Up set */ #define PWR_PUCRB_PB4_Pos (4U) #define PWR_PUCRB_PB4_Msk (0x1UL << PWR_PUCRB_PB4_Pos) /*!< 0x00000010 */ #define PWR_PUCRB_PB4 PWR_PUCRB_PB4_Msk /*!< Pin PB4 Pull-Up set */ #define PWR_PUCRB_PB5_Pos (5U) #define PWR_PUCRB_PB5_Msk (0x1UL << PWR_PUCRB_PB5_Pos) /*!< 0x00000020 */ #define PWR_PUCRB_PB5 PWR_PUCRB_PB5_Msk /*!< Pin PB5 Pull-Up set */ #define PWR_PUCRB_PB6_Pos (6U) #define PWR_PUCRB_PB6_Msk (0x1UL << PWR_PUCRB_PB6_Pos) /*!< 0x00000040 */ #define PWR_PUCRB_PB6 PWR_PUCRB_PB6_Msk /*!< Pin PB6 Pull-Up set */ #define PWR_PUCRB_PB7_Pos (7U) #define PWR_PUCRB_PB7_Msk (0x1UL << PWR_PUCRB_PB7_Pos) /*!< 0x00000080 */ #define PWR_PUCRB_PB7 PWR_PUCRB_PB7_Msk /*!< Pin PB7 Pull-Up set */ #define PWR_PUCRB_PB8_Pos (8U) #define PWR_PUCRB_PB8_Msk (0x1UL << PWR_PUCRB_PB8_Pos) /*!< 0x00000100 */ #define PWR_PUCRB_PB8 PWR_PUCRB_PB8_Msk /*!< Pin PB8 Pull-Up set */ #define PWR_PUCRB_PB9_Pos (9U) #define PWR_PUCRB_PB9_Msk (0x1UL << PWR_PUCRB_PB9_Pos) /*!< 0x00000200 */ #define PWR_PUCRB_PB9 PWR_PUCRB_PB9_Msk /*!< Pin PB9 Pull-Up set */ #define PWR_PUCRB_PB10_Pos (10U) #define PWR_PUCRB_PB10_Msk (0x1UL << PWR_PUCRB_PB10_Pos) /*!< 0x00000400 */ #define PWR_PUCRB_PB10 PWR_PUCRB_PB10_Msk /*!< Pin PB10 Pull-Up set */ #define PWR_PUCRB_PB11_Pos (11U) #define PWR_PUCRB_PB11_Msk (0x1UL << PWR_PUCRB_PB11_Pos) /*!< 0x00000800 */ #define PWR_PUCRB_PB11 PWR_PUCRB_PB11_Msk /*!< Pin PB11 Pull-Up set */ #define PWR_PUCRB_PB12_Pos (12U) #define PWR_PUCRB_PB12_Msk (0x1UL << PWR_PUCRB_PB12_Pos) /*!< 0x00001000 */ #define PWR_PUCRB_PB12 PWR_PUCRB_PB12_Msk /*!< Pin PB12 Pull-Up set */ #define PWR_PUCRB_PB13_Pos (13U) #define PWR_PUCRB_PB13_Msk (0x1UL << PWR_PUCRB_PB13_Pos) /*!< 0x00002000 */ #define PWR_PUCRB_PB13 PWR_PUCRB_PB13_Msk /*!< Pin PB13 Pull-Up set */ #define PWR_PUCRB_PB14_Pos (14U) #define PWR_PUCRB_PB14_Msk (0x1UL << PWR_PUCRB_PB14_Pos) /*!< 0x00004000 */ #define PWR_PUCRB_PB14 PWR_PUCRB_PB14_Msk /*!< Pin PB14 Pull-Up set */ #define PWR_PUCRB_PB15_Pos (15U) #define PWR_PUCRB_PB15_Msk (0x1UL << PWR_PUCRB_PB15_Pos) /*!< 0x00008000 */ #define PWR_PUCRB_PB15 PWR_PUCRB_PB15_Msk /*!< Pin PB15 Pull-Up set */ /******************** Bit definition for PWR_PDCRB register *****************/ #define PWR_PDCRB_PB0_Pos (0U) #define PWR_PDCRB_PB0_Msk (0x1UL << PWR_PDCRB_PB0_Pos) /*!< 0x00000001 */ #define PWR_PDCRB_PB0 PWR_PDCRB_PB0_Msk /*!< Pin PB0 Pull-Down set */ #define PWR_PDCRB_PB1_Pos (1U) #define PWR_PDCRB_PB1_Msk (0x1UL << PWR_PDCRB_PB1_Pos) /*!< 0x00000002 */ #define PWR_PDCRB_PB1 PWR_PDCRB_PB1_Msk /*!< Pin PB1 Pull-Down set */ #define PWR_PDCRB_PB2_Pos (2U) #define PWR_PDCRB_PB2_Msk (0x1UL << PWR_PDCRB_PB2_Pos) /*!< 0x00000004 */ #define PWR_PDCRB_PB2 PWR_PDCRB_PB2_Msk /*!< Pin PB2 Pull-Down set */ #define PWR_PDCRB_PB3_Pos (3U) #define PWR_PDCRB_PB3_Msk (0x1UL << PWR_PDCRB_PB3_Pos) /*!< 0x00000008 */ #define PWR_PDCRB_PB3 PWR_PDCRB_PB3_Msk /*!< Pin PB3 Pull-Down set */ #define PWR_PDCRB_PB4_Pos (4U) #define PWR_PDCRB_PB4_Msk (0x1UL << PWR_PDCRB_PB4_Pos) /*!< 0x00000010 */ #define PWR_PDCRB_PB4 PWR_PDCRB_PB4_Msk /*!< Pin PB4 Pull-Down set */ #define PWR_PDCRB_PB5_Pos (5U) #define PWR_PDCRB_PB5_Msk (0x1UL << PWR_PDCRB_PB5_Pos) /*!< 0x00000020 */ #define PWR_PDCRB_PB5 PWR_PDCRB_PB5_Msk /*!< Pin PB5 Pull-Down set */ #define PWR_PDCRB_PB6_Pos (6U) #define PWR_PDCRB_PB6_Msk (0x1UL << PWR_PDCRB_PB6_Pos) /*!< 0x00000040 */ #define PWR_PDCRB_PB6 PWR_PDCRB_PB6_Msk /*!< Pin PB6 Pull-Down set */ #define PWR_PDCRB_PB7_Pos (7U) #define PWR_PDCRB_PB7_Msk (0x1UL << PWR_PDCRB_PB7_Pos) /*!< 0x00000080 */ #define PWR_PDCRB_PB7 PWR_PDCRB_PB7_Msk /*!< Pin PB7 Pull-Down set */ #define PWR_PDCRB_PB8_Pos (8U) #define PWR_PDCRB_PB8_Msk (0x1UL << PWR_PDCRB_PB8_Pos) /*!< 0x00000100 */ #define PWR_PDCRB_PB8 PWR_PDCRB_PB8_Msk /*!< Pin PB8 Pull-Down set */ #define PWR_PDCRB_PB9_Pos (9U) #define PWR_PDCRB_PB9_Msk (0x1UL << PWR_PDCRB_PB9_Pos) /*!< 0x00000200 */ #define PWR_PDCRB_PB9 PWR_PDCRB_PB9_Msk /*!< Pin PB9 Pull-Down set */ #define PWR_PDCRB_PB10_Pos (10U) #define PWR_PDCRB_PB10_Msk (0x1UL << PWR_PDCRB_PB10_Pos) /*!< 0x00000400 */ #define PWR_PDCRB_PB10 PWR_PDCRB_PB10_Msk /*!< Pin PB10 Pull-Down set */ #define PWR_PDCRB_PB11_Pos (11U) #define PWR_PDCRB_PB11_Msk (0x1UL << PWR_PDCRB_PB11_Pos) /*!< 0x00000800 */ #define PWR_PDCRB_PB11 PWR_PDCRB_PB11_Msk /*!< Pin PB11 Pull-Down set */ #define PWR_PDCRB_PB12_Pos (12U) #define PWR_PDCRB_PB12_Msk (0x1UL << PWR_PDCRB_PB12_Pos) /*!< 0x00001000 */ #define PWR_PDCRB_PB12 PWR_PDCRB_PB12_Msk /*!< Pin PB12 Pull-Down set */ #define PWR_PDCRB_PB13_Pos (13U) #define PWR_PDCRB_PB13_Msk (0x1UL << PWR_PDCRB_PB13_Pos) /*!< 0x00002000 */ #define PWR_PDCRB_PB13 PWR_PDCRB_PB13_Msk /*!< Pin PB13 Pull-Down set */ #define PWR_PDCRB_PB14_Pos (14U) #define PWR_PDCRB_PB14_Msk (0x1UL << PWR_PDCRB_PB14_Pos) /*!< 0x00004000 */ #define PWR_PDCRB_PB14 PWR_PDCRB_PB14_Msk /*!< Pin PB14 Pull-Down set */ #define PWR_PDCRB_PB15_Pos (15U) #define PWR_PDCRB_PB15_Msk (0x1UL << PWR_PDCRB_PB15_Pos) /*!< 0x00008000 */ #define PWR_PDCRB_PB15 PWR_PDCRB_PB15_Msk /*!< Pin PB15 Pull-Down set */ /******************** Bit definition for PWR_PUCRC register *****************/ #define PWR_PUCRC_PC0_Pos (0U) #define PWR_PUCRC_PC0_Msk (0x1UL << PWR_PUCRC_PC0_Pos) /*!< 0x00000001 */ #define PWR_PUCRC_PC0 PWR_PUCRC_PC0_Msk /*!< Pin PC0 Pull-Up set */ #define PWR_PUCRC_PC1_Pos (1U) #define PWR_PUCRC_PC1_Msk (0x1UL << PWR_PUCRC_PC1_Pos) /*!< 0x00000002 */ #define PWR_PUCRC_PC1 PWR_PUCRC_PC1_Msk /*!< Pin PC1 Pull-Up set */ #define PWR_PUCRC_PC2_Pos (2U) #define PWR_PUCRC_PC2_Msk (0x1UL << PWR_PUCRC_PC2_Pos) /*!< 0x00000004 */ #define PWR_PUCRC_PC2 PWR_PUCRC_PC2_Msk /*!< Pin PC2 Pull-Up set */ #define PWR_PUCRC_PC3_Pos (3U) #define PWR_PUCRC_PC3_Msk (0x1UL << PWR_PUCRC_PC3_Pos) /*!< 0x00000008 */ #define PWR_PUCRC_PC3 PWR_PUCRC_PC3_Msk /*!< Pin PC3 Pull-Up set */ #define PWR_PUCRC_PC4_Pos (4U) #define PWR_PUCRC_PC4_Msk (0x1UL << PWR_PUCRC_PC4_Pos) /*!< 0x00000010 */ #define PWR_PUCRC_PC4 PWR_PUCRC_PC4_Msk /*!< Pin PC4 Pull-Up set */ #define PWR_PUCRC_PC5_Pos (5U) #define PWR_PUCRC_PC5_Msk (0x1UL << PWR_PUCRC_PC5_Pos) /*!< 0x00000020 */ #define PWR_PUCRC_PC5 PWR_PUCRC_PC5_Msk /*!< Pin PC5 Pull-Up set */ #define PWR_PUCRC_PC6_Pos (6U) #define PWR_PUCRC_PC6_Msk (0x1UL << PWR_PUCRC_PC6_Pos) /*!< 0x00000040 */ #define PWR_PUCRC_PC6 PWR_PUCRC_PC6_Msk /*!< Pin PC6 Pull-Up set */ #define PWR_PUCRC_PC13_Pos (13U) #define PWR_PUCRC_PC13_Msk (0x1UL << PWR_PUCRC_PC13_Pos) /*!< 0x00002000 */ #define PWR_PUCRC_PC13 PWR_PUCRC_PC13_Msk /*!< Pin PC13 Pull-Up set */ #define PWR_PUCRC_PC14_Pos (14U) #define PWR_PUCRC_PC14_Msk (0x1UL << PWR_PUCRC_PC14_Pos) /*!< 0x00004000 */ #define PWR_PUCRC_PC14 PWR_PUCRC_PC14_Msk /*!< Pin PC14 Pull-Up set */ #define PWR_PUCRC_PC15_Pos (15U) #define PWR_PUCRC_PC15_Msk (0x1UL << PWR_PUCRC_PC15_Pos) /*!< 0x00008000 */ #define PWR_PUCRC_PC15 PWR_PUCRC_PC15_Msk /*!< Pin PC15 Pull-Up set */ /******************** Bit definition for PWR_PDCRC register *****************/ #define PWR_PDCRC_PC0_Pos (0U) #define PWR_PDCRC_PC0_Msk (0x1UL << PWR_PDCRC_PC0_Pos) /*!< 0x00000001 */ #define PWR_PDCRC_PC0 PWR_PDCRC_PC0_Msk /*!< Pin PC0 Pull-Down set */ #define PWR_PDCRC_PC1_Pos (1U) #define PWR_PDCRC_PC1_Msk (0x1UL << PWR_PDCRC_PC1_Pos) /*!< 0x00000002 */ #define PWR_PDCRC_PC1 PWR_PDCRC_PC1_Msk /*!< Pin PC1 Pull-Down set */ #define PWR_PDCRC_PC2_Pos (2U) #define PWR_PDCRC_PC2_Msk (0x1UL << PWR_PDCRC_PC2_Pos) /*!< 0x00000004 */ #define PWR_PDCRC_PC2 PWR_PDCRC_PC2_Msk /*!< Pin PC2 Pull-Down set */ #define PWR_PDCRC_PC3_Pos (3U) #define PWR_PDCRC_PC3_Msk (0x1UL << PWR_PDCRC_PC3_Pos) /*!< 0x00000008 */ #define PWR_PDCRC_PC3 PWR_PDCRC_PC3_Msk /*!< Pin PC3 Pull-Down set */ #define PWR_PDCRC_PC4_Pos (4U) #define PWR_PDCRC_PC4_Msk (0x1UL << PWR_PDCRC_PC4_Pos) /*!< 0x00000010 */ #define PWR_PDCRC_PC4 PWR_PDCRC_PC4_Msk /*!< Pin PC4 Pull-Down set */ #define PWR_PDCRC_PC5_Pos (5U) #define PWR_PDCRC_PC5_Msk (0x1UL << PWR_PDCRC_PC5_Pos) /*!< 0x00000020 */ #define PWR_PDCRC_PC5 PWR_PDCRC_PC5_Msk /*!< Pin PC5 Pull-Down set */ #define PWR_PDCRC_PC6_Pos (6U) #define PWR_PDCRC_PC6_Msk (0x1UL << PWR_PDCRC_PC6_Pos) /*!< 0x00000040 */ #define PWR_PDCRC_PC6 PWR_PDCRC_PC6_Msk /*!< Pin PC6 Pull-Down set */ #define PWR_PDCRC_PC13_Pos (13U) #define PWR_PDCRC_PC13_Msk (0x1UL << PWR_PDCRC_PC13_Pos) /*!< 0x00002000 */ #define PWR_PDCRC_PC13 PWR_PDCRC_PC13_Msk /*!< Pin PC13 Pull-Down set */ #define PWR_PDCRC_PC14_Pos (14U) #define PWR_PDCRC_PC14_Msk (0x1UL << PWR_PDCRC_PC14_Pos) /*!< 0x00004000 */ #define PWR_PDCRC_PC14 PWR_PDCRC_PC14_Msk /*!< Pin PC14 Pull-Down set */ #define PWR_PDCRC_PC15_Pos (15U) #define PWR_PDCRC_PC15_Msk (0x1UL << PWR_PDCRC_PC15_Pos) /*!< 0x00008000 */ #define PWR_PDCRC_PC15 PWR_PDCRC_PC15_Msk /*!< Pin PC15 Pull-Down set */ /******************** Bit definition for PWR_PUCRH register *****************/ #define PWR_PUCRH_PH3_Pos (3U) #define PWR_PUCRH_PH3_Msk (0x1UL << PWR_PUCRH_PH3_Pos) /*!< 0x00000004 */ #define PWR_PUCRH_PH3 PWR_PUCRH_PH3_Msk /*!< Pin PH3 Pull-Up set */ /******************** Bit definition for PWR_PDCRH register *****************/ #define PWR_PDCRH_PH3_Pos (3U) #define PWR_PDCRH_PH3_Msk (0x1UL << PWR_PDCRH_PH3_Pos) /*!< 0x00000004 */ #define PWR_PDCRH_PH3 PWR_PDCRH_PH3_Msk /*!< Pin PH3 Pull-Down set */ /******************** Bit definition for PWR_EXTSCR register ********************/ #define PWR_EXTSCR_C1CSSF_Pos (0U) #define PWR_EXTSCR_C1CSSF_Msk (0x1UL << PWR_EXTSCR_C1CSSF_Pos) /*!< 0x00000001 */ #define PWR_EXTSCR_C1CSSF PWR_EXTSCR_C1CSSF_Msk /*!< Clear standby and stop flags for CPU1 */ #define PWR_EXTSCR_C1SBF_Pos (8U) #define PWR_EXTSCR_C1SBF_Msk (0x1UL << PWR_EXTSCR_C1SBF_Pos) /*!< 0x00000100 */ #define PWR_EXTSCR_C1SBF PWR_EXTSCR_C1SBF_Msk /*!< System standby flag for CPU1 */ #define PWR_EXTSCR_C1STOP2F_Pos (9U) #define PWR_EXTSCR_C1STOP2F_Msk (0x1UL << PWR_EXTSCR_C1STOP2F_Pos) /*!< 0x00000200 */ #define PWR_EXTSCR_C1STOP2F PWR_EXTSCR_C1STOP2F_Msk /*!< System stop2 flag for CPU1 */ #define PWR_EXTSCR_C1STOPF_Pos (10U) #define PWR_EXTSCR_C1STOPF_Msk (0x1UL << PWR_EXTSCR_C1STOPF_Pos) /*!< 0x00000400 */ #define PWR_EXTSCR_C1STOPF PWR_EXTSCR_C1STOPF_Msk /*!< System stop0 or stop1 flag for CPU1 */ #define PWR_EXTSCR_C1DS_Pos (14U) #define PWR_EXTSCR_C1DS_Msk (0x1UL << PWR_EXTSCR_C1DS_Pos) /*!< 0x00004000 */ #define PWR_EXTSCR_C1DS PWR_EXTSCR_C1DS_Msk /*!< CPU1 deepsleep mode flag */ /******************** Bit definition for PWR_SUBGHZSPICR register ********************/ #define PWR_SUBGHZSPICR_NSS_Pos (15U) #define PWR_SUBGHZSPICR_NSS_Msk (0x1UL << PWR_SUBGHZSPICR_NSS_Pos) /*!< 0x00008000 */ #define PWR_SUBGHZSPICR_NSS PWR_SUBGHZSPICR_NSS_Msk /*!< Sub-GHz radio SUBGHZSPI_NSS control */ /******************************************************************************/ /* */ /* Reset and Clock Control */ /* */ /******************************************************************************/ /******************** Bit definition for RCC_CR register *****************/ #define RCC_CR_MSION_Pos (0U) #define RCC_CR_MSION_Msk (0x1UL << RCC_CR_MSION_Pos) /*!< 0x00000001 */ #define RCC_CR_MSION RCC_CR_MSION_Msk /*!< Internal Multi Speed oscillator (MSI) clock enable */ #define RCC_CR_MSIRDY_Pos (1U) #define RCC_CR_MSIRDY_Msk (0x1UL << RCC_CR_MSIRDY_Pos) /*!< 0x00000002 */ #define RCC_CR_MSIRDY RCC_CR_MSIRDY_Msk /*!< Internal Multi Speed oscillator (MSI) clock ready flag */ #define RCC_CR_MSIPLLEN_Pos (2U) #define RCC_CR_MSIPLLEN_Msk (0x1UL << RCC_CR_MSIPLLEN_Pos) /*!< 0x00000004 */ #define RCC_CR_MSIPLLEN RCC_CR_MSIPLLEN_Msk /*!< Internal Multi Speed oscillator (MSI) PLL enable */ #define RCC_CR_MSIRGSEL_Pos (3U) #define RCC_CR_MSIRGSEL_Msk (0x1UL << RCC_CR_MSIRGSEL_Pos) /*!< 0x00000008 */ #define RCC_CR_MSIRGSEL RCC_CR_MSIRGSEL_Msk /*!< Internal Multi Speed oscillator (MSI) range selection */ /*!< MSIRANGE configuration : 12 frequency ranges available */ #define RCC_CR_MSIRANGE_Pos (4U) #define RCC_CR_MSIRANGE_Msk (0xFUL << RCC_CR_MSIRANGE_Pos) /*!< 0x000000F0 */ #define RCC_CR_MSIRANGE RCC_CR_MSIRANGE_Msk /*!< Internal Multi Speed oscillator (MSI) clock Range */ #define RCC_CR_MSIRANGE_0 (0x0UL << RCC_CR_MSIRANGE_Pos) /*!< 0x00000000 */ #define RCC_CR_MSIRANGE_1 (0x1UL << RCC_CR_MSIRANGE_Pos) /*!< 0x00000010 */ #define RCC_CR_MSIRANGE_2 (0x2UL << RCC_CR_MSIRANGE_Pos) /*!< 0x00000020 */ #define RCC_CR_MSIRANGE_3 (0x3UL << RCC_CR_MSIRANGE_Pos) /*!< 0x00000030 */ #define RCC_CR_MSIRANGE_4 (0x4UL << RCC_CR_MSIRANGE_Pos) /*!< 0x00000040 */ #define RCC_CR_MSIRANGE_5 (0x5UL << RCC_CR_MSIRANGE_Pos) /*!< 0x00000050 */ #define RCC_CR_MSIRANGE_6 (0x6UL << RCC_CR_MSIRANGE_Pos) /*!< 0x00000060 */ #define RCC_CR_MSIRANGE_7 (0x7UL << RCC_CR_MSIRANGE_Pos) /*!< 0x00000070 */ #define RCC_CR_MSIRANGE_8 (0x8UL << RCC_CR_MSIRANGE_Pos) /*!< 0x00000080 */ #define RCC_CR_MSIRANGE_9 (0x9UL << RCC_CR_MSIRANGE_Pos) /*!< 0x00000090 */ #define RCC_CR_MSIRANGE_10 (0xAUL << RCC_CR_MSIRANGE_Pos) /*!< 0x000000A0 */ #define RCC_CR_MSIRANGE_11 (0xBUL << RCC_CR_MSIRANGE_Pos) /*!< 0x000000B0 */ #define RCC_CR_HSION_Pos (8U) #define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000100 */ #define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed oscillator (HSI16) clock enable */ #define RCC_CR_HSIKERON_Pos (9U) #define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos) /*!< 0x00000200 */ #define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel */ #define RCC_CR_HSIRDY_Pos (10U) #define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000400 */ #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed oscillator (HSI16) clock ready flag */ #define RCC_CR_HSIASFS_Pos (11U) #define RCC_CR_HSIASFS_Msk (0x1UL << RCC_CR_HSIASFS_Pos) /*!< 0x00000800 */ #define RCC_CR_HSIASFS RCC_CR_HSIASFS_Msk /*!< HSI16 Automatic Start from Stop */ #define RCC_CR_HSIKERDY_Pos (12U) #define RCC_CR_HSIKERDY_Msk (0x1UL << RCC_CR_HSIKERDY_Pos) /*!< 0x00001000 */ #define RCC_CR_HSIKERDY RCC_CR_HSIKERDY_Msk /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel ready flag*/ #define RCC_CR_HSEON_Pos (16U) #define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */ #define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed oscillator (HSE) clock enable */ #define RCC_CR_HSERDY_Pos (17U) #define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */ #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed oscillator (HSE) clock ready */ #define RCC_CR_CSSON_Pos (19U) #define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos) /*!< 0x00080000 */ #define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< HSE Clock Security System enable */ #define RCC_CR_HSEPRE_Pos (20U) #define RCC_CR_HSEPRE_Msk (0x1UL << RCC_CR_HSEPRE_Pos) /*!< 0x00100000 */ #define RCC_CR_HSEPRE RCC_CR_HSEPRE_Msk /*!< HSE sysclk prescaler */ #define RCC_CR_HSEBYPPWR_Pos (21U) #define RCC_CR_HSEBYPPWR_Msk (0x1UL << RCC_CR_HSEBYPPWR_Pos) /*!< 0x00200000 */ #define RCC_CR_HSEBYPPWR RCC_CR_HSEBYPPWR_Msk /*!< Enable HSE32 VDDTCXO */ #define RCC_CR_PLLON_Pos (24U) #define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */ #define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< System PLL clock enable */ #define RCC_CR_PLLRDY_Pos (25U) #define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */ #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< System PLL clock ready */ /******************** Bit definition for RCC_ICSCR register ***************/ /*!< MSICAL configuration */ #define RCC_ICSCR_MSICAL_Pos (0U) #define RCC_ICSCR_MSICAL_Msk (0xFFUL << RCC_ICSCR_MSICAL_Pos) /*!< 0x000000FF */ #define RCC_ICSCR_MSICAL RCC_ICSCR_MSICAL_Msk /*!< MSICAL[7:0] bits */ /*!< MSITRIM configuration */ #define RCC_ICSCR_MSITRIM_Pos (8U) #define RCC_ICSCR_MSITRIM_Msk (0xFFUL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x0000FF00 */ #define RCC_ICSCR_MSITRIM RCC_ICSCR_MSITRIM_Msk /*!< MSITRIM[7:0] bits */ /*!< HSICAL configuration */ #define RCC_ICSCR_HSICAL_Pos (16U) #define RCC_ICSCR_HSICAL_Msk (0xFFUL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00FF0000 */ #define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< HSICAL[7:0] bits */ /*!< HSITRIM configuration */ #define RCC_ICSCR_HSITRIM_Pos (24U) #define RCC_ICSCR_HSITRIM_Msk (0x7FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x7F000000 */ #define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[6:0] bits */ /******************** Bit definition for RCC_CFGR register ******************/ /*!< SW configuration */ #define RCC_CFGR_SW_Pos (0U) #define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */ #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */ #define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */ #define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */ /*!< SWS configuration */ #define RCC_CFGR_SWS_Pos (2U) #define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */ #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */ #define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */ #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */ /*!< HPRE configuration */ #define RCC_CFGR_HPRE_Pos (4U) #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */ #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */ #define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */ #define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */ #define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */ #define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */ /*!< PPRE1 configuration */ #define RCC_CFGR_PPRE1_Pos (8U) #define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */ #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */ #define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */ #define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */ #define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */ /*!< PPRE2 configuration */ #define RCC_CFGR_PPRE2_Pos (11U) #define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */ #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */ #define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */ #define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */ #define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */ /*!< STOPWUCK configuration */ #define RCC_CFGR_STOPWUCK_Pos (15U) #define RCC_CFGR_STOPWUCK_Msk (0x1UL << RCC_CFGR_STOPWUCK_Pos) /*!< 0x00008000 */ #define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk /*!< Wake Up from stop and CSS backup clock selection */ /*!< HPREF configuration */ #define RCC_CFGR_HPREF_Pos (16U) #define RCC_CFGR_HPREF_Msk (0x1UL << RCC_CFGR_HPREF_Pos) /*!< 0x00010000 */ #define RCC_CFGR_HPREF RCC_CFGR_HPREF_Msk /*!< AHB prescaler flag */ /*!< PPRE1F configuration */ #define RCC_CFGR_PPRE1F_Pos (17U) #define RCC_CFGR_PPRE1F_Msk (0x1UL << RCC_CFGR_PPRE1F_Pos) /*!< 0x00020000 */ #define RCC_CFGR_PPRE1F RCC_CFGR_PPRE1F_Msk /*!< CPU1 APB1 prescaler flag */ /*!< PPRE2F configuration */ #define RCC_CFGR_PPRE2F_Pos (18U) #define RCC_CFGR_PPRE2F_Msk (0x1UL << RCC_CFGR_PPRE2F_Pos) /*!< 0x00040000 */ #define RCC_CFGR_PPRE2F RCC_CFGR_PPRE2F_Msk /*!< APB2 prescaler flag */ /*!< MCOSEL configuration */ #define RCC_CFGR_MCOSEL_Pos (24U) #define RCC_CFGR_MCOSEL_Msk (0xFUL << RCC_CFGR_MCOSEL_Pos) /*!< 0x0F000000 */ #define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCOSEL [3:0] bits (Clock output selection) */ #define RCC_CFGR_MCOSEL_0 (0x1UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */ #define RCC_CFGR_MCOSEL_1 (0x2UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */ #define RCC_CFGR_MCOSEL_2 (0x4UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */ #define RCC_CFGR_MCOSEL_3 (0x8UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x08000000 */ /*!< MCOPRE configuration */ #define RCC_CFGR_MCOPRE_Pos (28U) #define RCC_CFGR_MCOPRE_Msk (0x7UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */ #define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler */ #define RCC_CFGR_MCOPRE_0 (0x1UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */ #define RCC_CFGR_MCOPRE_1 (0x2UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */ #define RCC_CFGR_MCOPRE_2 (0x4UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */ /******************** Bit definition for RCC_PLLCFGR register ***************/ #define RCC_PLLCFGR_PLLSRC_Pos (0U) #define RCC_PLLCFGR_PLLSRC_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_Pos)/*!< 0x00000003 */ #define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk #define RCC_PLLCFGR_PLLSRC_0 (0x1UL << RCC_PLLCFGR_PLLSRC_Pos)/*!< 0x00000001 */ #define RCC_PLLCFGR_PLLSRC_1 (0x2UL << RCC_PLLCFGR_PLLSRC_Pos)/*!< 0x00000002 */ #define RCC_PLLCFGR_PLLM_Pos (4U) #define RCC_PLLCFGR_PLLM_Msk (0x7UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000070 */ #define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk #define RCC_PLLCFGR_PLLM_0 (0x1UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */ #define RCC_PLLCFGR_PLLM_1 (0x2UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */ #define RCC_PLLCFGR_PLLM_2 (0x4UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000040 */ #define RCC_PLLCFGR_PLLN_Pos (8U) #define RCC_PLLCFGR_PLLN_Msk (0x7FUL << RCC_PLLCFGR_PLLN_Pos)/*!< 0x00007F00 */ #define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk #define RCC_PLLCFGR_PLLN_0 (0x01UL << RCC_PLLCFGR_PLLN_Pos)/*!< 0x00000100 */ #define RCC_PLLCFGR_PLLN_1 (0x02UL << RCC_PLLCFGR_PLLN_Pos)/*!< 0x00000200 */ #define RCC_PLLCFGR_PLLN_2 (0x04UL << RCC_PLLCFGR_PLLN_Pos)/*!< 0x00000400 */ #define RCC_PLLCFGR_PLLN_3 (0x08UL << RCC_PLLCFGR_PLLN_Pos)/*!< 0x00000800 */ #define RCC_PLLCFGR_PLLN_4 (0x10UL << RCC_PLLCFGR_PLLN_Pos)/*!< 0x00001000 */ #define RCC_PLLCFGR_PLLN_5 (0x20UL << RCC_PLLCFGR_PLLN_Pos)/*!< 0x00002000 */ #define RCC_PLLCFGR_PLLN_6 (0x40UL << RCC_PLLCFGR_PLLN_Pos)/*!< 0x00004000 */ #define RCC_PLLCFGR_PLLPEN_Pos (16U) #define RCC_PLLCFGR_PLLPEN_Msk (0x1UL << RCC_PLLCFGR_PLLPEN_Pos)/*!< 0x00010000 */ #define RCC_PLLCFGR_PLLPEN RCC_PLLCFGR_PLLPEN_Msk #define RCC_PLLCFGR_PLLP_Pos (17U) #define RCC_PLLCFGR_PLLP_Msk (0x1FUL << RCC_PLLCFGR_PLLP_Pos)/*!< 0x003E0000 */ #define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk #define RCC_PLLCFGR_PLLP_0 (0x01UL << RCC_PLLCFGR_PLLP_Pos)/*!< 0x00020000 */ #define RCC_PLLCFGR_PLLP_1 (0x02UL << RCC_PLLCFGR_PLLP_Pos)/*!< 0x00040000 */ #define RCC_PLLCFGR_PLLP_2 (0x04UL << RCC_PLLCFGR_PLLP_Pos)/*!< 0x00080000 */ #define RCC_PLLCFGR_PLLP_3 (0x08UL << RCC_PLLCFGR_PLLP_Pos)/*!< 0x00100000 */ #define RCC_PLLCFGR_PLLP_4 (0x10UL << RCC_PLLCFGR_PLLP_Pos)/*!< 0x00200000 */ #define RCC_PLLCFGR_PLLQEN_Pos (24U) #define RCC_PLLCFGR_PLLQEN_Msk (0x1UL << RCC_PLLCFGR_PLLQEN_Pos)/*!< 0x01000000 */ #define RCC_PLLCFGR_PLLQEN RCC_PLLCFGR_PLLQEN_Msk #define RCC_PLLCFGR_PLLQ_Pos (25U) #define RCC_PLLCFGR_PLLQ_Msk (0x7UL << RCC_PLLCFGR_PLLQ_Pos)/*!< 0x0E000000 */ #define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk #define RCC_PLLCFGR_PLLQ_0 (0x1UL << RCC_PLLCFGR_PLLQ_Pos)/*!< 0x02000000 */ #define RCC_PLLCFGR_PLLQ_1 (0x2UL << RCC_PLLCFGR_PLLQ_Pos)/*!< 0x04000000 */ #define RCC_PLLCFGR_PLLQ_2 (0x4UL << RCC_PLLCFGR_PLLQ_Pos)/*!< 0x08000000 */ #define RCC_PLLCFGR_PLLREN_Pos (28U) #define RCC_PLLCFGR_PLLREN_Msk (0x1UL << RCC_PLLCFGR_PLLREN_Pos)/*!< 0x10000000 */ #define RCC_PLLCFGR_PLLREN RCC_PLLCFGR_PLLREN_Msk #define RCC_PLLCFGR_PLLR_Pos (29U) #define RCC_PLLCFGR_PLLR_Msk (0x7UL << RCC_PLLCFGR_PLLR_Pos)/*!< 0xE0000000 */ #define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk #define RCC_PLLCFGR_PLLR_0 (0x1UL << RCC_PLLCFGR_PLLR_Pos)/*!< 0x20000000 */ #define RCC_PLLCFGR_PLLR_1 (0x2UL << RCC_PLLCFGR_PLLR_Pos)/*!< 0x40000000 */ #define RCC_PLLCFGR_PLLR_2 (0x4UL << RCC_PLLCFGR_PLLR_Pos)/*!< 0x80000000 */ /******************** Bit definition for RCC_CIER register ******************/ #define RCC_CIER_LSIRDYIE_Pos (0U) #define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ #define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk #define RCC_CIER_LSERDYIE_Pos (1U) #define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ #define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk #define RCC_CIER_MSIRDYIE_Pos (2U) #define RCC_CIER_MSIRDYIE_Msk (0x1UL << RCC_CIER_MSIRDYIE_Pos) /*!< 0x00000004 */ #define RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE_Msk #define RCC_CIER_HSIRDYIE_Pos (3U) #define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000008 */ #define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk #define RCC_CIER_HSERDYIE_Pos (4U) #define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000010 */ #define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk #define RCC_CIER_PLLRDYIE_Pos (5U) #define RCC_CIER_PLLRDYIE_Msk (0x1UL << RCC_CIER_PLLRDYIE_Pos)/*!< 0x00000020 */ #define RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk #define RCC_CIER_LSECSSIE_Pos (9U) #define RCC_CIER_LSECSSIE_Msk (0x1UL << RCC_CIER_LSECSSIE_Pos) /*!< 0x00000200 */ #define RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE_Msk /******************** Bit definition for RCC_CIFR register ******************/ #define RCC_CIFR_LSIRDYF_Pos (0U) #define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ #define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk #define RCC_CIFR_LSERDYF_Pos (1U) #define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ #define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk #define RCC_CIFR_MSIRDYF_Pos (2U) #define RCC_CIFR_MSIRDYF_Msk (0x1UL << RCC_CIFR_MSIRDYF_Pos) /*!< 0x00000004 */ #define RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF_Msk #define RCC_CIFR_HSIRDYF_Pos (3U) #define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000008 */ #define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk #define RCC_CIFR_HSERDYF_Pos (4U) #define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000010 */ #define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk #define RCC_CIFR_PLLRDYF_Pos (5U) #define RCC_CIFR_PLLRDYF_Msk (0x1UL << RCC_CIFR_PLLRDYF_Pos)/*!< 0x00000020 */ #define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk #define RCC_CIFR_CSSF_Pos (8U) #define RCC_CIFR_CSSF_Msk (0x1UL << RCC_CIFR_CSSF_Pos) /*!< 0x00000100 */ #define RCC_CIFR_CSSF RCC_CIFR_CSSF_Msk #define RCC_CIFR_LSECSSF_Pos (9U) #define RCC_CIFR_LSECSSF_Msk (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */ #define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk /******************** Bit definition for RCC_CICR register ******************/ #define RCC_CICR_LSIRDYC_Pos (0U) #define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */ #define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk #define RCC_CICR_LSERDYC_Pos (1U) #define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */ #define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk #define RCC_CICR_MSIRDYC_Pos (2U) #define RCC_CICR_MSIRDYC_Msk (0x1UL << RCC_CICR_MSIRDYC_Pos) /*!< 0x00000004 */ #define RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC_Msk #define RCC_CICR_HSIRDYC_Pos (3U) #define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000008 */ #define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk #define RCC_CICR_HSERDYC_Pos (4U) #define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000010 */ #define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk #define RCC_CICR_PLLRDYC_Pos (5U) #define RCC_CICR_PLLRDYC_Msk (0x1UL << RCC_CICR_PLLRDYC_Pos)/*!< 0x00000020 */ #define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk #define RCC_CICR_CSSC_Pos (8U) #define RCC_CICR_CSSC_Msk (0x1UL << RCC_CICR_CSSC_Pos) /*!< 0x00000100 */ #define RCC_CICR_CSSC RCC_CICR_CSSC_Msk #define RCC_CICR_LSECSSC_Pos (9U) #define RCC_CICR_LSECSSC_Msk (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */ #define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk /******************** Bit definition for RCC_AHB1RSTR register **************/ #define RCC_AHB1RSTR_DMA1RST_Pos (0U) #define RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)/*!< 0x00000001 */ #define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk #define RCC_AHB1RSTR_DMA2RST_Pos (1U) #define RCC_AHB1RSTR_DMA2RST_Msk (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)/*!< 0x00000002 */ #define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk #define RCC_AHB1RSTR_DMAMUX1RST_Pos (2U) #define RCC_AHB1RSTR_DMAMUX1RST_Msk (0x1UL << RCC_AHB1RSTR_DMAMUX1RST_Pos)/*!< 0x00000004 */ #define RCC_AHB1RSTR_DMAMUX1RST RCC_AHB1RSTR_DMAMUX1RST_Msk #define RCC_AHB1RSTR_CRCRST_Pos (12U) #define RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)/*!< 0x00001000 */ #define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk /******************** Bit definition for RCC_AHB2RSTR register ***************/ #define RCC_AHB2RSTR_GPIOARST_Pos (0U) #define RCC_AHB2RSTR_GPIOARST_Msk (0x1UL << RCC_AHB2RSTR_GPIOARST_Pos)/*!< 0x00000001 */ #define RCC_AHB2RSTR_GPIOARST RCC_AHB2RSTR_GPIOARST_Msk #define RCC_AHB2RSTR_GPIOBRST_Pos (1U) #define RCC_AHB2RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOBRST_Pos)/*!< 0x00000002 */ #define RCC_AHB2RSTR_GPIOBRST RCC_AHB2RSTR_GPIOBRST_Msk #define RCC_AHB2RSTR_GPIOCRST_Pos (2U) #define RCC_AHB2RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOCRST_Pos)/*!< 0x00000004 */ #define RCC_AHB2RSTR_GPIOCRST RCC_AHB2RSTR_GPIOCRST_Msk #define RCC_AHB2RSTR_GPIOHRST_Pos (7U) #define RCC_AHB2RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOHRST_Pos)/*!< 0x00000080 */ #define RCC_AHB2RSTR_GPIOHRST RCC_AHB2RSTR_GPIOHRST_Msk /******************** Bit definition for RCC_AHB3RSTR register ***************/ #define RCC_AHB3RSTR_PKARST_Pos (16U) #define RCC_AHB3RSTR_PKARST_Msk (0x1UL << RCC_AHB3RSTR_PKARST_Pos) /*!< 0x00010000 */ #define RCC_AHB3RSTR_PKARST RCC_AHB3RSTR_PKARST_Msk #define RCC_AHB3RSTR_AESRST_Pos (17U) #define RCC_AHB3RSTR_AESRST_Msk (0x1UL << RCC_AHB3RSTR_AESRST_Pos)/*!< 0x00020000 */ #define RCC_AHB3RSTR_AESRST RCC_AHB3RSTR_AESRST_Msk #define RCC_AHB3RSTR_RNGRST_Pos (18U) #define RCC_AHB3RSTR_RNGRST_Msk (0x1UL << RCC_AHB3RSTR_RNGRST_Pos)/*!< 0x00040000 */ #define RCC_AHB3RSTR_RNGRST RCC_AHB3RSTR_RNGRST_Msk #define RCC_AHB3RSTR_HSEMRST_Pos (19U) #define RCC_AHB3RSTR_HSEMRST_Msk (0x1UL << RCC_AHB3RSTR_HSEMRST_Pos)/*!< 0x00080000 */ #define RCC_AHB3RSTR_HSEMRST RCC_AHB3RSTR_HSEMRST_Msk #define RCC_AHB3RSTR_FLASHRST_Pos (25U) #define RCC_AHB3RSTR_FLASHRST_Msk (0x1UL << RCC_AHB3RSTR_FLASHRST_Pos) /*!< 0x02000000 */ #define RCC_AHB3RSTR_FLASHRST RCC_AHB3RSTR_FLASHRST_Msk /******************** Bit definition for RCC_APB1RSTR1 register **************/ #define RCC_APB1RSTR1_TIM2RST_Pos (0U) #define RCC_APB1RSTR1_TIM2RST_Msk (0x1UL << RCC_APB1RSTR1_TIM2RST_Pos)/*!< 0x00000001 */ #define RCC_APB1RSTR1_TIM2RST RCC_APB1RSTR1_TIM2RST_Msk #define RCC_APB1RSTR1_SPI2RST_Pos (14U) #define RCC_APB1RSTR1_SPI2RST_Msk (0x1UL << RCC_APB1RSTR1_SPI2RST_Pos)/*!< 0x00004000 */ #define RCC_APB1RSTR1_SPI2RST RCC_APB1RSTR1_SPI2RST_Msk #define RCC_APB1RSTR1_USART2RST_Pos (17U) #define RCC_APB1RSTR1_USART2RST_Msk (0x1UL << RCC_APB1RSTR1_USART2RST_Pos)/*!< 0x00020000 */ #define RCC_APB1RSTR1_USART2RST RCC_APB1RSTR1_USART2RST_Msk #define RCC_APB1RSTR1_I2C1RST_Pos (21U) #define RCC_APB1RSTR1_I2C1RST_Msk (0x1UL << RCC_APB1RSTR1_I2C1RST_Pos)/*!< 0x00200000 */ #define RCC_APB1RSTR1_I2C1RST RCC_APB1RSTR1_I2C1RST_Msk #define RCC_APB1RSTR1_I2C2RST_Pos (22U) #define RCC_APB1RSTR1_I2C2RST_Msk (0x1UL << RCC_APB1RSTR1_I2C2RST_Pos)/*!< 0x00400000 */ #define RCC_APB1RSTR1_I2C2RST RCC_APB1RSTR1_I2C2RST_Msk #define RCC_APB1RSTR1_I2C3RST_Pos (23U) #define RCC_APB1RSTR1_I2C3RST_Msk (0x1UL << RCC_APB1RSTR1_I2C3RST_Pos)/*!< 0x00800000 */ #define RCC_APB1RSTR1_I2C3RST RCC_APB1RSTR1_I2C3RST_Msk #define RCC_APB1RSTR1_DACRST_Pos (29U) #define RCC_APB1RSTR1_DACRST_Msk (0x1UL << RCC_APB1RSTR1_DACRST_Pos)/*!< 0x20000000 */ #define RCC_APB1RSTR1_DACRST RCC_APB1RSTR1_DACRST_Msk #define RCC_APB1RSTR1_LPTIM1RST_Pos (31U) #define RCC_APB1RSTR1_LPTIM1RST_Msk (0x1UL << RCC_APB1RSTR1_LPTIM1RST_Pos)/*!< 0x80000000 */ #define RCC_APB1RSTR1_LPTIM1RST RCC_APB1RSTR1_LPTIM1RST_Msk /******************** Bit definition for RCC_APB1RSTR2 register **************/ #define RCC_APB1RSTR2_LPUART1RST_Pos (0U) #define RCC_APB1RSTR2_LPUART1RST_Msk (0x1UL << RCC_APB1RSTR2_LPUART1RST_Pos)/*!< 0x00000001 */ #define RCC_APB1RSTR2_LPUART1RST RCC_APB1RSTR2_LPUART1RST_Msk #define RCC_APB1RSTR2_LPTIM2RST_Pos (5U) #define RCC_APB1RSTR2_LPTIM2RST_Msk (0x1UL << RCC_APB1RSTR2_LPTIM2RST_Pos)/*!< 0x00000020 */ #define RCC_APB1RSTR2_LPTIM2RST RCC_APB1RSTR2_LPTIM2RST_Msk #define RCC_APB1RSTR2_LPTIM3RST_Pos (6U) #define RCC_APB1RSTR2_LPTIM3RST_Msk (0x1UL << RCC_APB1RSTR2_LPTIM3RST_Pos)/*!< 0x00000040 */ #define RCC_APB1RSTR2_LPTIM3RST RCC_APB1RSTR2_LPTIM3RST_Msk /******************** Bit definition for RCC_APB2RSTR register **************/ #define RCC_APB2RSTR_ADCRST_Pos (9U) #define RCC_APB2RSTR_ADCRST_Msk (0x1UL << RCC_APB2RSTR_ADCRST_Pos)/*!< 0x00000200 */ #define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk #define RCC_APB2RSTR_TIM1RST_Pos (11U) #define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)/*!< 0x00000800 */ #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk #define RCC_APB2RSTR_SPI1RST_Pos (12U) #define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)/*!< 0x00001000 */ #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk #define RCC_APB2RSTR_USART1RST_Pos (14U) #define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos)/*!< 0x00004000 */ #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk #define RCC_APB2RSTR_TIM16RST_Pos (17U) #define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos)/*!< 0x00020000 */ #define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk #define RCC_APB2RSTR_TIM17RST_Pos (18U) #define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos)/*!< 0x00040000 */ #define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /******************** Bit definition for RCC_APB3RSTR register **************/ #define RCC_APB3RSTR_SUBGHZSPIRST_Pos (0U) #define RCC_APB3RSTR_SUBGHZSPIRST_Msk (0x1UL << RCC_APB3RSTR_SUBGHZSPIRST_Pos) /*!< 0x00000001 */ #define RCC_APB3RSTR_SUBGHZSPIRST RCC_APB3RSTR_SUBGHZSPIRST_Msk /******************** Bit definition for RCC_AHB1ENR register ****************/ #define RCC_AHB1ENR_DMA1EN_Pos (0U) #define RCC_AHB1ENR_DMA1EN_Msk (0x1UL << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00000001 */ #define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk #define RCC_AHB1ENR_DMA2EN_Pos (1U) #define RCC_AHB1ENR_DMA2EN_Msk (0x1UL << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00000002 */ #define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk #define RCC_AHB1ENR_DMAMUX1EN_Pos (2U) #define RCC_AHB1ENR_DMAMUX1EN_Msk (0x1UL << RCC_AHB1ENR_DMAMUX1EN_Pos)/*!< 0x00000004 */ #define RCC_AHB1ENR_DMAMUX1EN RCC_AHB1ENR_DMAMUX1EN_Msk #define RCC_AHB1ENR_CRCEN_Pos (12U) #define RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */ #define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk /******************** Bit definition for RCC_AHB2ENR register ***************/ #define RCC_AHB2ENR_GPIOAEN_Pos (0U) #define RCC_AHB2ENR_GPIOAEN_Msk (0x1UL << RCC_AHB2ENR_GPIOAEN_Pos) /*!< 0x00000001 */ #define RCC_AHB2ENR_GPIOAEN RCC_AHB2ENR_GPIOAEN_Msk #define RCC_AHB2ENR_GPIOBEN_Pos (1U) #define RCC_AHB2ENR_GPIOBEN_Msk (0x1UL << RCC_AHB2ENR_GPIOBEN_Pos) /*!< 0x00000002 */ #define RCC_AHB2ENR_GPIOBEN RCC_AHB2ENR_GPIOBEN_Msk #define RCC_AHB2ENR_GPIOCEN_Pos (2U) #define RCC_AHB2ENR_GPIOCEN_Msk (0x1UL << RCC_AHB2ENR_GPIOCEN_Pos) /*!< 0x00000004 */ #define RCC_AHB2ENR_GPIOCEN RCC_AHB2ENR_GPIOCEN_Msk #define RCC_AHB2ENR_GPIOHEN_Pos (7U) #define RCC_AHB2ENR_GPIOHEN_Msk (0x1UL << RCC_AHB2ENR_GPIOHEN_Pos) /*!< 0x00000080 */ #define RCC_AHB2ENR_GPIOHEN RCC_AHB2ENR_GPIOHEN_Msk /******************** Bit definition for RCC_AHB3ENR register ***************/ #define RCC_AHB3ENR_PKAEN_Pos (16U) #define RCC_AHB3ENR_PKAEN_Msk (0x1UL << RCC_AHB3ENR_PKAEN_Pos) /*!< 0x00010000 */ #define RCC_AHB3ENR_PKAEN RCC_AHB3ENR_PKAEN_Msk #define RCC_AHB3ENR_AESEN_Pos (17U) #define RCC_AHB3ENR_AESEN_Msk (0x1UL << RCC_AHB3ENR_AESEN_Pos)/*!< 0x00020000 */ #define RCC_AHB3ENR_AESEN RCC_AHB3ENR_AESEN_Msk #define RCC_AHB3ENR_RNGEN_Pos (18U) #define RCC_AHB3ENR_RNGEN_Msk (0x1UL << RCC_AHB3ENR_RNGEN_Pos) /*!< 0x00040000 */ #define RCC_AHB3ENR_RNGEN RCC_AHB3ENR_RNGEN_Msk #define RCC_AHB3ENR_HSEMEN_Pos (19U) #define RCC_AHB3ENR_HSEMEN_Msk (0x1UL << RCC_AHB3ENR_HSEMEN_Pos) /*!< 0x00080000 */ #define RCC_AHB3ENR_HSEMEN RCC_AHB3ENR_HSEMEN_Msk #define RCC_AHB3ENR_FLASHEN_Pos (25U) #define RCC_AHB3ENR_FLASHEN_Msk (0x1UL << RCC_AHB3ENR_FLASHEN_Pos) /*!< 0x02000000 */ #define RCC_AHB3ENR_FLASHEN RCC_AHB3ENR_FLASHEN_Msk /******************** Bit definition for RCC_APB1ENR1 register **************/ #define RCC_APB1ENR1_TIM2EN_Pos (0U) #define RCC_APB1ENR1_TIM2EN_Msk (0x1UL << RCC_APB1ENR1_TIM2EN_Pos) /*!< 0x00000001 */ #define RCC_APB1ENR1_TIM2EN RCC_APB1ENR1_TIM2EN_Msk #define RCC_APB1ENR1_RTCAPBEN_Pos (10U) #define RCC_APB1ENR1_RTCAPBEN_Msk (0x1UL << RCC_APB1ENR1_RTCAPBEN_Pos)/*!< 0x00000400 */ #define RCC_APB1ENR1_RTCAPBEN RCC_APB1ENR1_RTCAPBEN_Msk #define RCC_APB1ENR1_WWDGEN_Pos (11U) #define RCC_APB1ENR1_WWDGEN_Msk (0x1UL << RCC_APB1ENR1_WWDGEN_Pos) /*!< 0x00000800 */ #define RCC_APB1ENR1_WWDGEN RCC_APB1ENR1_WWDGEN_Msk #define RCC_APB1ENR1_SPI2EN_Pos (14U) #define RCC_APB1ENR1_SPI2EN_Msk (0x1UL << RCC_APB1ENR1_SPI2EN_Pos) /*!< 0x00004000 */ #define RCC_APB1ENR1_SPI2EN RCC_APB1ENR1_SPI2EN_Msk #define RCC_APB1ENR1_USART2EN_Pos (17U) #define RCC_APB1ENR1_USART2EN_Msk (0x1UL << RCC_APB1ENR1_USART2EN_Pos) /*!< 0x00020000 */ #define RCC_APB1ENR1_USART2EN RCC_APB1ENR1_USART2EN_Msk #define RCC_APB1ENR1_I2C1EN_Pos (21U) #define RCC_APB1ENR1_I2C1EN_Msk (0x1UL << RCC_APB1ENR1_I2C1EN_Pos) /*!< 0x00200000 */ #define RCC_APB1ENR1_I2C1EN RCC_APB1ENR1_I2C1EN_Msk #define RCC_APB1ENR1_I2C2EN_Pos (22U) #define RCC_APB1ENR1_I2C2EN_Msk (0x1UL << RCC_APB1ENR1_I2C2EN_Pos) /*!< 0x00400000 */ #define RCC_APB1ENR1_I2C2EN RCC_APB1ENR1_I2C2EN_Msk #define RCC_APB1ENR1_I2C3EN_Pos (23U) #define RCC_APB1ENR1_I2C3EN_Msk (0x1UL << RCC_APB1ENR1_I2C3EN_Pos) /*!< 0x00800000 */ #define RCC_APB1ENR1_I2C3EN RCC_APB1ENR1_I2C3EN_Msk #define RCC_APB1ENR1_DACEN_Pos (29U) #define RCC_APB1ENR1_DACEN_Msk (0x1UL << RCC_APB1ENR1_DACEN_Pos)/*!< 0x20000000 */ #define RCC_APB1ENR1_DACEN RCC_APB1ENR1_DACEN_Msk #define RCC_APB1ENR1_LPTIM1EN_Pos (31U) #define RCC_APB1ENR1_LPTIM1EN_Msk (0x1UL << RCC_APB1ENR1_LPTIM1EN_Pos)/*!< 0x80000000 */ #define RCC_APB1ENR1_LPTIM1EN RCC_APB1ENR1_LPTIM1EN_Msk /******************** Bit definition for RCC_APB1ENR2 register **************/ #define RCC_APB1ENR2_LPUART1EN_Pos (0U) #define RCC_APB1ENR2_LPUART1EN_Msk (0x1UL << RCC_APB1ENR2_LPUART1EN_Pos)/*!< 0x00000001 */ #define RCC_APB1ENR2_LPUART1EN RCC_APB1ENR2_LPUART1EN_Msk #define RCC_APB1ENR2_LPTIM2EN_Pos (5U) #define RCC_APB1ENR2_LPTIM2EN_Msk (0x1UL << RCC_APB1ENR2_LPTIM2EN_Pos)/*!< 0x00000020 */ #define RCC_APB1ENR2_LPTIM2EN RCC_APB1ENR2_LPTIM2EN_Msk #define RCC_APB1ENR2_LPTIM3EN_Pos (6U) #define RCC_APB1ENR2_LPTIM3EN_Msk (0x1UL << RCC_APB1ENR2_LPTIM3EN_Pos)/*!< 0x00000040 */ #define RCC_APB1ENR2_LPTIM3EN RCC_APB1ENR2_LPTIM3EN_Msk /******************** Bit definition for RCC_APB2ENR register **************/ #define RCC_APB2ENR_ADCEN_Pos (9U) #define RCC_APB2ENR_ADCEN_Msk (0x1UL << RCC_APB2ENR_ADCEN_Pos) /*!< 0x00000200 */ #define RCC_APB2ENR_ADCEN RCC_APB2ENR_ADCEN_Msk #define RCC_APB2ENR_TIM1EN_Pos (11U) #define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */ #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk #define RCC_APB2ENR_SPI1EN_Pos (12U) #define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk #define RCC_APB2ENR_USART1EN_Pos (14U) #define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos)/*!< 0x00004000 */ #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk #define RCC_APB2ENR_TIM16EN_Pos (17U) #define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */ #define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk #define RCC_APB2ENR_TIM17EN_Pos (18U) #define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */ #define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk /******************** Bit definition for RCC_APB3ENR register **************/ #define RCC_APB3ENR_SUBGHZSPIEN_Pos (0U) #define RCC_APB3ENR_SUBGHZSPIEN_Msk (0x1UL << RCC_APB3ENR_SUBGHZSPIEN_Pos)/*!< 0x00000001 */ #define RCC_APB3ENR_SUBGHZSPIEN RCC_APB3ENR_SUBGHZSPIEN_Msk /******************** Bit definition for RCC_AHB1SMENR register ****************/ #define RCC_AHB1SMENR_DMA1SMEN_Pos (0U) #define RCC_AHB1SMENR_DMA1SMEN_Msk (0x1UL << RCC_AHB1SMENR_DMA1SMEN_Pos)/*!< 0x00000001 */ #define RCC_AHB1SMENR_DMA1SMEN RCC_AHB1SMENR_DMA1SMEN_Msk #define RCC_AHB1SMENR_DMA2SMEN_Pos (1U) #define RCC_AHB1SMENR_DMA2SMEN_Msk (0x1UL << RCC_AHB1SMENR_DMA2SMEN_Pos)/*!< 0x00000002 */ #define RCC_AHB1SMENR_DMA2SMEN RCC_AHB1SMENR_DMA2SMEN_Msk #define RCC_AHB1SMENR_DMAMUX1SMEN_Pos (2U) #define RCC_AHB1SMENR_DMAMUX1SMEN_Msk (0x1UL << RCC_AHB1SMENR_DMAMUX1SMEN_Pos)/*!< 0x00000004 */ #define RCC_AHB1SMENR_DMAMUX1SMEN RCC_AHB1SMENR_DMAMUX1SMEN_Msk #define RCC_AHB1SMENR_CRCSMEN_Pos (12U) #define RCC_AHB1SMENR_CRCSMEN_Msk (0x1UL << RCC_AHB1SMENR_CRCSMEN_Pos)/*!< 0x00001000 */ #define RCC_AHB1SMENR_CRCSMEN RCC_AHB1SMENR_CRCSMEN_Msk /******************** Bit definition for RCC_AHB2SMENR register ***************/ #define RCC_AHB2SMENR_GPIOASMEN_Pos (0U) #define RCC_AHB2SMENR_GPIOASMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOASMEN_Pos)/*!< 0x00000001 */ #define RCC_AHB2SMENR_GPIOASMEN RCC_AHB2SMENR_GPIOASMEN_Msk #define RCC_AHB2SMENR_GPIOBSMEN_Pos (1U) #define RCC_AHB2SMENR_GPIOBSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOBSMEN_Pos)/*!< 0x00000002 */ #define RCC_AHB2SMENR_GPIOBSMEN RCC_AHB2SMENR_GPIOBSMEN_Msk #define RCC_AHB2SMENR_GPIOCSMEN_Pos (2U) #define RCC_AHB2SMENR_GPIOCSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOCSMEN_Pos)/*!< 0x00000004 */ #define RCC_AHB2SMENR_GPIOCSMEN RCC_AHB2SMENR_GPIOCSMEN_Msk #define RCC_AHB2SMENR_GPIOHSMEN_Pos (7U) #define RCC_AHB2SMENR_GPIOHSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOHSMEN_Pos)/*!< 0x00000080 */ #define RCC_AHB2SMENR_GPIOHSMEN RCC_AHB2SMENR_GPIOHSMEN_Msk /******************** Bit definition for RCC_AHB3SMENR register ***************/ #define RCC_AHB3SMENR_PKASMEN_Pos (16U) #define RCC_AHB3SMENR_PKASMEN_Msk (0x1UL << RCC_AHB3SMENR_PKASMEN_Pos) /*!< 0x00010000 */ #define RCC_AHB3SMENR_PKASMEN RCC_AHB3SMENR_PKASMEN_Msk #define RCC_AHB3SMENR_AESSMEN_Pos (17U) #define RCC_AHB3SMENR_AESSMEN_Msk (0x1UL << RCC_AHB3SMENR_AESSMEN_Pos) /*!< 0x00020000 */ #define RCC_AHB3SMENR_AESSMEN RCC_AHB3SMENR_AESSMEN_Msk #define RCC_AHB3SMENR_RNGSMEN_Pos (18U) #define RCC_AHB3SMENR_RNGSMEN_Msk (0x1UL << RCC_AHB3SMENR_RNGSMEN_Pos)/*!< 0x00040000 */ #define RCC_AHB3SMENR_RNGSMEN RCC_AHB3SMENR_RNGSMEN_Msk #define RCC_AHB3SMENR_SRAM1SMEN_Pos (23U) #define RCC_AHB3SMENR_SRAM1SMEN_Msk (0x1UL << RCC_AHB3SMENR_SRAM1SMEN_Pos)/*!< 0x00800000 */ #define RCC_AHB3SMENR_SRAM1SMEN RCC_AHB3SMENR_SRAM1SMEN_Msk #define RCC_AHB3SMENR_SRAM2SMEN_Pos (24U) #define RCC_AHB3SMENR_SRAM2SMEN_Msk (0x1UL << RCC_AHB3SMENR_SRAM2SMEN_Pos)/*!< 0x01000000 */ #define RCC_AHB3SMENR_SRAM2SMEN RCC_AHB3SMENR_SRAM2SMEN_Msk #define RCC_AHB3SMENR_FLASHSMEN_Pos (25U) #define RCC_AHB3SMENR_FLASHSMEN_Msk (0x1UL << RCC_AHB3SMENR_FLASHSMEN_Pos)/*!< 0x02000000 */ #define RCC_AHB3SMENR_FLASHSMEN RCC_AHB3SMENR_FLASHSMEN_Msk /******************** Bit definition for RCC_APB1SMENR1 register **************/ #define RCC_APB1SMENR1_TIM2SMEN_Pos (0U) #define RCC_APB1SMENR1_TIM2SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM2SMEN_Pos)/*!< 0x00000001 */ #define RCC_APB1SMENR1_TIM2SMEN RCC_APB1SMENR1_TIM2SMEN_Msk #define RCC_APB1SMENR1_RTCAPBSMEN_Pos (10U) #define RCC_APB1SMENR1_RTCAPBSMEN_Msk (0x1UL << RCC_APB1SMENR1_RTCAPBSMEN_Pos)/*!< 0x00000400 */ #define RCC_APB1SMENR1_RTCAPBSMEN RCC_APB1SMENR1_RTCAPBSMEN_Msk #define RCC_APB1SMENR1_WWDGSMEN_Pos (11U) #define RCC_APB1SMENR1_WWDGSMEN_Msk (0x1UL << RCC_APB1SMENR1_WWDGSMEN_Pos)/*!< 0x00000800 */ #define RCC_APB1SMENR1_WWDGSMEN RCC_APB1SMENR1_WWDGSMEN_Msk #define RCC_APB1SMENR1_SPI2SMEN_Pos (14U) #define RCC_APB1SMENR1_SPI2SMEN_Msk (0x1UL << RCC_APB1SMENR1_SPI2SMEN_Pos)/*!< 0x00004000 */ #define RCC_APB1SMENR1_SPI2SMEN RCC_APB1SMENR1_SPI2SMEN_Msk #define RCC_APB1SMENR1_USART2SMEN_Pos (17U) #define RCC_APB1SMENR1_USART2SMEN_Msk (0x1UL << RCC_APB1SMENR1_USART2SMEN_Pos)/*!< 0x00020000 */ #define RCC_APB1SMENR1_USART2SMEN RCC_APB1SMENR1_USART2SMEN_Msk #define RCC_APB1SMENR1_I2C1SMEN_Pos (21U) #define RCC_APB1SMENR1_I2C1SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C1SMEN_Pos)/*!< 0x00200000 */ #define RCC_APB1SMENR1_I2C1SMEN RCC_APB1SMENR1_I2C1SMEN_Msk #define RCC_APB1SMENR1_I2C2SMEN_Pos (22U) #define RCC_APB1SMENR1_I2C2SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C2SMEN_Pos)/*!< 0x00400000 */ #define RCC_APB1SMENR1_I2C2SMEN RCC_APB1SMENR1_I2C2SMEN_Msk #define RCC_APB1SMENR1_I2C3SMEN_Pos (23U) #define RCC_APB1SMENR1_I2C3SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C3SMEN_Pos)/*!< 0x00800000 */ #define RCC_APB1SMENR1_I2C3SMEN RCC_APB1SMENR1_I2C3SMEN_Msk #define RCC_APB1SMENR1_DACSMEN_Pos (29U) #define RCC_APB1SMENR1_DACSMEN_Msk (0x1UL << RCC_APB1SMENR1_DACSMEN_Pos)/*!< 0x20000000 */ #define RCC_APB1SMENR1_DACSMEN RCC_APB1SMENR1_DACSMEN_Msk #define RCC_APB1SMENR1_LPTIM1SMEN_Pos (31U) #define RCC_APB1SMENR1_LPTIM1SMEN_Msk (0x1UL << RCC_APB1SMENR1_LPTIM1SMEN_Pos)/*!< 0x80000000 */ #define RCC_APB1SMENR1_LPTIM1SMEN RCC_APB1SMENR1_LPTIM1SMEN_Msk /******************** Bit definition for RCC_APB1SMENR2 register **************/ #define RCC_APB1SMENR2_LPUART1SMEN_Pos (0U) #define RCC_APB1SMENR2_LPUART1SMEN_Msk (0x1UL << RCC_APB1SMENR2_LPUART1SMEN_Pos)/*!< 0x00000001 */ #define RCC_APB1SMENR2_LPUART1SMEN RCC_APB1SMENR2_LPUART1SMEN_Msk #define RCC_APB1SMENR2_LPTIM2SMEN_Pos (5U) #define RCC_APB1SMENR2_LPTIM2SMEN_Msk (0x1UL << RCC_APB1SMENR2_LPTIM2SMEN_Pos)/*!< 0x00000020 */ #define RCC_APB1SMENR2_LPTIM2SMEN RCC_APB1SMENR2_LPTIM2SMEN_Msk #define RCC_APB1SMENR2_LPTIM3SMEN_Pos (6U) #define RCC_APB1SMENR2_LPTIM3SMEN_Msk (0x1UL << RCC_APB1SMENR2_LPTIM3SMEN_Pos)/*!< 0x00000040 */ #define RCC_APB1SMENR2_LPTIM3SMEN RCC_APB1SMENR2_LPTIM3SMEN_Msk /******************** Bit definition for RCC_APB2SMENR register **************/ #define RCC_APB2SMENR_ADCSMEN_Pos (9U) #define RCC_APB2SMENR_ADCSMEN_Msk (0x1UL << RCC_APB2SMENR_ADCSMEN_Pos)/*!< 0x00000200 */ #define RCC_APB2SMENR_ADCSMEN RCC_APB2SMENR_ADCSMEN_Msk #define RCC_APB2SMENR_TIM1SMEN_Pos (11U) #define RCC_APB2SMENR_TIM1SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM1SMEN_Pos)/*!< 0x00000800 */ #define RCC_APB2SMENR_TIM1SMEN RCC_APB2SMENR_TIM1SMEN_Msk #define RCC_APB2SMENR_SPI1SMEN_Pos (12U) #define RCC_APB2SMENR_SPI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos)/*!< 0x00001000 */ #define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk #define RCC_APB2SMENR_USART1SMEN_Pos (14U) #define RCC_APB2SMENR_USART1SMEN_Msk (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos)/*!< 0x00004000 */ #define RCC_APB2SMENR_USART1SMEN RCC_APB2SMENR_USART1SMEN_Msk #define RCC_APB2SMENR_TIM16SMEN_Pos (17U) #define RCC_APB2SMENR_TIM16SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM16SMEN_Pos)/*!< 0x00020000 */ #define RCC_APB2SMENR_TIM16SMEN RCC_APB2SMENR_TIM16SMEN_Msk #define RCC_APB2SMENR_TIM17SMEN_Pos (18U) #define RCC_APB2SMENR_TIM17SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM17SMEN_Pos)/*!< 0x00040000 */ #define RCC_APB2SMENR_TIM17SMEN RCC_APB2SMENR_TIM17SMEN_Msk /******************** Bit definition for RCC_APB3SMENR register **************/ #define RCC_APB3SMENR_SUBGHZSPISMEN_Pos (0U) #define RCC_APB3SMENR_SUBGHZSPISMEN_Msk (0x1UL << RCC_APB3SMENR_SUBGHZSPISMEN_Pos)/*!< 0x00000001 */ #define RCC_APB3SMENR_SUBGHZSPISMEN RCC_APB3SMENR_SUBGHZSPISMEN_Msk /******************** Bit definition for RCC_CCIPR register ******************/ #define RCC_CCIPR_USART1SEL_Pos (0U) #define RCC_CCIPR_USART1SEL_Msk (0x3UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000003 */ #define RCC_CCIPR_USART1SEL RCC_CCIPR_USART1SEL_Msk #define RCC_CCIPR_USART1SEL_0 (0x1UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000001 */ #define RCC_CCIPR_USART1SEL_1 (0x2UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000002 */ #define RCC_CCIPR_USART2SEL_Pos (2U) #define RCC_CCIPR_USART2SEL_Msk (0x3UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x0000000C */ #define RCC_CCIPR_USART2SEL RCC_CCIPR_USART2SEL_Msk #define RCC_CCIPR_USART2SEL_0 (0x1UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000004 */ #define RCC_CCIPR_USART2SEL_1 (0x2UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000008 */ #define RCC_CCIPR_I2S2SEL_Pos (8U) #define RCC_CCIPR_I2S2SEL_Msk (0x3UL << RCC_CCIPR_I2S2SEL_Pos) /*!< 0x00000300 */ #define RCC_CCIPR_I2S2SEL RCC_CCIPR_I2S2SEL_Msk #define RCC_CCIPR_I2S2SEL_0 (0x1UL << RCC_CCIPR_I2S2SEL_Pos) /*!< 0x00000100 */ #define RCC_CCIPR_I2S2SEL_1 (0x2UL << RCC_CCIPR_I2S2SEL_Pos) /*!< 0x00000200 */ #define RCC_CCIPR_LPUART1SEL_Pos (10U) #define RCC_CCIPR_LPUART1SEL_Msk (0x3UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000C00 */ #define RCC_CCIPR_LPUART1SEL RCC_CCIPR_LPUART1SEL_Msk #define RCC_CCIPR_LPUART1SEL_0 (0x1UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000400 */ #define RCC_CCIPR_LPUART1SEL_1 (0x2UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000800 */ #define RCC_CCIPR_I2C1SEL_Pos (12U) #define RCC_CCIPR_I2C1SEL_Msk (0x3UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00003000 */ #define RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk #define RCC_CCIPR_I2C1SEL_0 (0x1UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00001000 */ #define RCC_CCIPR_I2C1SEL_1 (0x2UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00002000 */ #define RCC_CCIPR_I2C2SEL_Pos (14U) #define RCC_CCIPR_I2C2SEL_Msk (0x3UL << RCC_CCIPR_I2C2SEL_Pos) /*!< 0x0000C000 */ #define RCC_CCIPR_I2C2SEL RCC_CCIPR_I2C2SEL_Msk #define RCC_CCIPR_I2C2SEL_0 (0x1UL << RCC_CCIPR_I2C2SEL_Pos) /*!< 0x00004000 */ #define RCC_CCIPR_I2C2SEL_1 (0x2UL << RCC_CCIPR_I2C2SEL_Pos) /*!< 0x00008000 */ #define RCC_CCIPR_I2C3SEL_Pos (16U) #define RCC_CCIPR_I2C3SEL_Msk (0x3UL << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00030000 */ #define RCC_CCIPR_I2C3SEL RCC_CCIPR_I2C3SEL_Msk #define RCC_CCIPR_I2C3SEL_0 (0x1UL << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00010000 */ #define RCC_CCIPR_I2C3SEL_1 (0x2UL << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00020000 */ #define RCC_CCIPR_LPTIM1SEL_Pos (18U) #define RCC_CCIPR_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x000C0000 */ #define RCC_CCIPR_LPTIM1SEL RCC_CCIPR_LPTIM1SEL_Msk #define RCC_CCIPR_LPTIM1SEL_0 (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00040000 */ #define RCC_CCIPR_LPTIM1SEL_1 (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00080000 */ #define RCC_CCIPR_LPTIM2SEL_Pos (20U) #define RCC_CCIPR_LPTIM2SEL_Msk (0x3UL << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00300000 */ #define RCC_CCIPR_LPTIM2SEL RCC_CCIPR_LPTIM2SEL_Msk #define RCC_CCIPR_LPTIM2SEL_0 (0x1UL << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00100000 */ #define RCC_CCIPR_LPTIM2SEL_1 (0x2UL << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00200000 */ #define RCC_CCIPR_LPTIM3SEL_Pos (22U) #define RCC_CCIPR_LPTIM3SEL_Msk (0x3UL << RCC_CCIPR_LPTIM3SEL_Pos) /*!< 0x00C00000 */ #define RCC_CCIPR_LPTIM3SEL RCC_CCIPR_LPTIM3SEL_Msk #define RCC_CCIPR_LPTIM3SEL_0 (0x1UL << RCC_CCIPR_LPTIM3SEL_Pos) /*!< 0x00400000 */ #define RCC_CCIPR_LPTIM3SEL_1 (0x2UL << RCC_CCIPR_LPTIM3SEL_Pos) /*!< 0x00800000 */ #define RCC_CCIPR_ADCSEL_Pos (28U) #define RCC_CCIPR_ADCSEL_Msk (0x3UL << RCC_CCIPR_ADCSEL_Pos) /*!< 0x30000000 */ #define RCC_CCIPR_ADCSEL RCC_CCIPR_ADCSEL_Msk #define RCC_CCIPR_ADCSEL_0 (0x1UL << RCC_CCIPR_ADCSEL_Pos) /*!< 0x10000000 */ #define RCC_CCIPR_ADCSEL_1 (0x2UL << RCC_CCIPR_ADCSEL_Pos) /*!< 0x20000000 */ #define RCC_CCIPR_RNGSEL_Pos (30U) #define RCC_CCIPR_RNGSEL_Msk (0x3UL << RCC_CCIPR_RNGSEL_Pos) /*!< 0xC0000000 */ #define RCC_CCIPR_RNGSEL RCC_CCIPR_RNGSEL_Msk #define RCC_CCIPR_RNGSEL_0 (0x1UL << RCC_CCIPR_RNGSEL_Pos) /*!< 0x40000000 */ #define RCC_CCIPR_RNGSEL_1 (0x2UL << RCC_CCIPR_RNGSEL_Pos) /*!< 0x80000000 */ /******************** Bit definition for RCC_BDCR register ******************/ #define RCC_BDCR_LSEON_Pos (0U) #define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk #define RCC_BDCR_LSERDY_Pos (1U) #define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */ #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk #define RCC_BDCR_LSEBYP_Pos (2U) #define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */ #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk #define RCC_BDCR_LSEDRV_Pos (3U) #define RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */ #define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk #define RCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */ #define RCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */ #define RCC_BDCR_LSECSSON_Pos (5U) #define RCC_BDCR_LSECSSON_Msk (0x1UL << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */ #define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk #define RCC_BDCR_LSECSSD_Pos (6U) #define RCC_BDCR_LSECSSD_Msk (0x1UL << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */ #define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk #define RCC_BDCR_LSESYSEN_Pos (7U) #define RCC_BDCR_LSESYSEN_Msk (0x1UL << RCC_BDCR_LSESYSEN_Pos) /*!< 0x00000080 */ #define RCC_BDCR_LSESYSEN RCC_BDCR_LSESYSEN_Msk #define RCC_BDCR_RTCSEL_Pos (8U) #define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */ #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk #define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */ #define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */ #define RCC_BDCR_LSESYSRDY_Pos (11U) #define RCC_BDCR_LSESYSRDY_Msk (0x1UL << RCC_BDCR_LSESYSRDY_Pos) /*!< 0x00000800 */ #define RCC_BDCR_LSESYSRDY RCC_BDCR_LSESYSRDY_Msk #define RCC_BDCR_RTCEN_Pos (15U) #define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */ #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk #define RCC_BDCR_BDRST_Pos (16U) #define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */ #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk #define RCC_BDCR_LSCOEN_Pos (24U) #define RCC_BDCR_LSCOEN_Msk (0x1UL << RCC_BDCR_LSCOEN_Pos) /*!< 0x01000000 */ #define RCC_BDCR_LSCOEN RCC_BDCR_LSCOEN_Msk #define RCC_BDCR_LSCOSEL_Pos (25U) #define RCC_BDCR_LSCOSEL_Msk (0x1UL << RCC_BDCR_LSCOSEL_Pos) /*!< 0x02000000 */ #define RCC_BDCR_LSCOSEL RCC_BDCR_LSCOSEL_Msk /******************** Bit definition for RCC_CSR register *******************/ #define RCC_CSR_LSION_Pos (0U) #define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */ #define RCC_CSR_LSION RCC_CSR_LSION_Msk #define RCC_CSR_LSIRDY_Pos (1U) #define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */ #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk #define RCC_CSR_LSIPRE_Pos (4U) #define RCC_CSR_LSIPRE_Msk (0x1UL << RCC_CSR_LSIPRE_Pos) /*!< 0x00000010 */ #define RCC_CSR_LSIPRE RCC_CSR_LSIPRE_Msk #define RCC_CSR_MSISRANGE_Pos (8U) #define RCC_CSR_MSISRANGE_Msk (0xFUL << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000F00 */ #define RCC_CSR_MSISRANGE RCC_CSR_MSISRANGE_Msk #define RCC_CSR_MSISRANGE_1 (0x4UL << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000400 */ #define RCC_CSR_MSISRANGE_2 (0x5UL << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000500 */ #define RCC_CSR_MSISRANGE_4 (0x6UL << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000600 */ #define RCC_CSR_MSISRANGE_8 (0x7UL << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000700 */ #define RCC_CSR_RFRSTF_Pos (14U) #define RCC_CSR_RFRSTF_Msk (0x1UL << RCC_CSR_RFRSTF_Pos) /*!< 0x0004000 */ #define RCC_CSR_RFRSTF RCC_CSR_RFRSTF_Msk #define RCC_CSR_RFRST_Pos (15U) #define RCC_CSR_RFRST_Msk (0x1UL << RCC_CSR_RFRST_Pos) /*!< 0x0008000 */ #define RCC_CSR_RFRST RCC_CSR_RFRST_Msk #define RCC_CSR_RMVF_Pos (23U) #define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x00800000 */ #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk #define RCC_CSR_RFILARSTF_Pos (24U) #define RCC_CSR_RFILARSTF_Msk (0x1UL << RCC_CSR_RFILARSTF_Pos) /*!< 0x01000000 */ #define RCC_CSR_RFILARSTF RCC_CSR_RFILARSTF_Msk #define RCC_CSR_OBLRSTF_Pos (25U) #define RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */ #define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk #define RCC_CSR_PINRSTF_Pos (26U) #define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */ #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk #define RCC_CSR_BORRSTF_Pos (27U) #define RCC_CSR_BORRSTF_Msk (0x1UL << RCC_CSR_BORRSTF_Pos) /*!< 0x08000000 */ #define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk #define RCC_CSR_SFTRSTF_Pos (28U) #define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */ #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk #define RCC_CSR_IWDGRSTF_Pos (29U) #define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */ #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk #define RCC_CSR_WWDGRSTF_Pos (30U) #define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */ #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk #define RCC_CSR_LPWRRSTF_Pos (31U) #define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */ #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /******************** Bit definition for RCC_EXTCFGR register *******************/ #define RCC_EXTCFGR_SHDHPRE_Pos (0U) #define RCC_EXTCFGR_SHDHPRE_Msk (0xFUL << RCC_EXTCFGR_SHDHPRE_Pos) /*!< 0x0000000F */ #define RCC_EXTCFGR_SHDHPRE RCC_EXTCFGR_SHDHPRE_Msk #define RCC_EXTCFGR_SHDHPRE_0 (0x1UL << RCC_EXTCFGR_SHDHPRE_Pos) /*!< 0x00000001 */ #define RCC_EXTCFGR_SHDHPRE_1 (0x2UL << RCC_EXTCFGR_SHDHPRE_Pos) /*!< 0x00000002 */ #define RCC_EXTCFGR_SHDHPRE_2 (0x4UL << RCC_EXTCFGR_SHDHPRE_Pos) /*!< 0x00000004 */ #define RCC_EXTCFGR_SHDHPRE_3 (0x8UL << RCC_EXTCFGR_SHDHPRE_Pos) /*!< 0x00000008 */ #define RCC_EXTCFGR_SHDHPREF_Pos (16U) #define RCC_EXTCFGR_SHDHPREF_Msk (0x1UL << RCC_EXTCFGR_SHDHPREF_Pos)/*!< 0x00010000 */ #define RCC_EXTCFGR_SHDHPREF RCC_EXTCFGR_SHDHPREF_Msk /******************************************************************************/ /* */ /* RNG */ /* */ /******************************************************************************/ /* * @brief Specific device feature definitions */ #define RNG_VER_3_2 /******************** Bits definition for RNG_CR register *******************/ #define RNG_CR_RNGEN_Pos (2U) #define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ #define RNG_CR_RNGEN RNG_CR_RNGEN_Msk #define RNG_CR_IE_Pos (3U) #define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ #define RNG_CR_IE RNG_CR_IE_Msk #define RNG_CR_CED_Pos (5U) #define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ #define RNG_CR_CED RNG_CR_CED_Msk #define RNG_CR_RNG_CONFIG3_Pos (8U) #define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) /*!< 0x00000F00 */ #define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk #define RNG_CR_NISTC_Pos (12U) #define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) /*!< 0x00001000 */ #define RNG_CR_NISTC RNG_CR_NISTC_Msk #define RNG_CR_RNG_CONFIG2_Pos (13U) #define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) /*!< 0x0000E000 */ #define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk #define RNG_CR_CLKDIV_Pos (16U) #define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) /*!< 0x000F0000 */ #define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk #define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ #define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ #define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ #define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ #define RNG_CR_RNG_CONFIG1_Pos (20U) #define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x03F00000 */ #define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk #define RNG_CR_CONDRST_Pos (30U) #define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) /*!< 0x40000000 */ #define RNG_CR_CONDRST RNG_CR_CONDRST_Msk #define RNG_CR_CONFIGLOCK_Pos (31U) #define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) /*!< 0x80000000 */ #define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk /******************** Bits definition for RNG_SR register *******************/ #define RNG_SR_DRDY_Pos (0U) #define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ #define RNG_SR_DRDY RNG_SR_DRDY_Msk #define RNG_SR_CECS_Pos (1U) #define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */ #define RNG_SR_CECS RNG_SR_CECS_Msk #define RNG_SR_SECS_Pos (2U) #define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ #define RNG_SR_SECS RNG_SR_SECS_Msk #define RNG_SR_CEIS_Pos (5U) #define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ #define RNG_SR_CEIS RNG_SR_CEIS_Msk #define RNG_SR_SEIS_Pos (6U) #define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ #define RNG_SR_SEIS RNG_SR_SEIS_Msk /******************** Bits definition for RNG_DR register *******************/ #define RNG_DR_RNDATA_Pos (0U) #define RNG_DR_RNDATA_Msk (0xFFFFFFFFUL << RNG_DR_RNDATA_Pos) /*!< 0xFFFFFFFF */ #define RNG_DR_RNDATA RNG_DR_RNDATA_Msk /******************** Bits definition for RNG_HTCR register *****************/ #define RNG_HTCR_HTCFG_Pos (0U) #define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk /******************************************************************************/ /* */ /* Real-Time Clock (RTC) */ /* */ /******************************************************************************/ /******************** Bits definition for RTC_TR register *******************/ #define RTC_TR_PM_Pos (22U) #define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */ #define RTC_TR_PM RTC_TR_PM_Msk #define RTC_TR_HT_Pos (20U) #define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */ #define RTC_TR_HT RTC_TR_HT_Msk #define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */ #define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */ #define RTC_TR_HU_Pos (16U) #define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */ #define RTC_TR_HU RTC_TR_HU_Msk #define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */ #define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */ #define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */ #define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */ #define RTC_TR_MNT_Pos (12U) #define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */ #define RTC_TR_MNT RTC_TR_MNT_Msk #define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */ #define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */ #define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */ #define RTC_TR_MNU_Pos (8U) #define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_TR_MNU RTC_TR_MNU_Msk #define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */ #define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */ #define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */ #define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */ #define RTC_TR_ST_Pos (4U) #define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */ #define RTC_TR_ST RTC_TR_ST_Msk #define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */ #define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */ #define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */ #define RTC_TR_SU_Pos (0U) #define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */ #define RTC_TR_SU RTC_TR_SU_Msk #define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */ #define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */ #define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */ #define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */ /******************** Bits definition for RTC_DR register *******************/ #define RTC_DR_YT_Pos (20U) #define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */ #define RTC_DR_YT RTC_DR_YT_Msk #define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */ #define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */ #define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */ #define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */ #define RTC_DR_YU_Pos (16U) #define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */ #define RTC_DR_YU RTC_DR_YU_Msk #define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */ #define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */ #define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */ #define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */ #define RTC_DR_WDU_Pos (13U) #define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */ #define RTC_DR_WDU RTC_DR_WDU_Msk #define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */ #define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */ #define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */ #define RTC_DR_MT_Pos (12U) #define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */ #define RTC_DR_MT RTC_DR_MT_Msk #define RTC_DR_MU_Pos (8U) #define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */ #define RTC_DR_MU RTC_DR_MU_Msk #define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */ #define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */ #define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */ #define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */ #define RTC_DR_DT_Pos (4U) #define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */ #define RTC_DR_DT RTC_DR_DT_Msk #define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */ #define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */ #define RTC_DR_DU_Pos (0U) #define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */ #define RTC_DR_DU RTC_DR_DU_Msk #define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */ #define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */ #define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */ #define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */ /******************** Bits definition for RTC_SSR register ******************/ #define RTC_SSR_SS_Pos (0U) #define RTC_SSR_SS_Msk (0xFFFFFFFFUL << RTC_SSR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_SSR_SS RTC_SSR_SS_Msk /******************** Bits definition for RTC_ICSR register ******************/ #define RTC_ICSR_RECALPF_Pos (16U) #define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */ #define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk #define RTC_ICSR_BCDU_Pos (10U) #define RTC_ICSR_BCDU_Msk (0x7UL << RTC_ICSR_BCDU_Pos) /*!< 0x00001C00 */ #define RTC_ICSR_BCDU RTC_ICSR_BCDU_Msk #define RTC_ICSR_BCDU_0 (0x1UL << RTC_ICSR_BCDU_Pos) /*!< 0x00000400 */ #define RTC_ICSR_BCDU_1 (0x2UL << RTC_ICSR_BCDU_Pos) /*!< 0x00000800 */ #define RTC_ICSR_BCDU_2 (0x4UL << RTC_ICSR_BCDU_Pos) /*!< 0x00001000 */ #define RTC_ICSR_BIN_Pos (8U) #define RTC_ICSR_BIN_Msk (0x3UL << RTC_ICSR_BIN_Pos) /*!< 0x00000300 */ #define RTC_ICSR_BIN RTC_ICSR_BIN_Msk #define RTC_ICSR_BIN_0 (0x1UL << RTC_ICSR_BIN_Pos) /*!< 0x00000100 */ #define RTC_ICSR_BIN_1 (0x2UL << RTC_ICSR_BIN_Pos) /*!< 0x00000200 */ #define RTC_ICSR_INIT_Pos (7U) #define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */ #define RTC_ICSR_INIT RTC_ICSR_INIT_Msk #define RTC_ICSR_INITF_Pos (6U) #define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */ #define RTC_ICSR_INITF RTC_ICSR_INITF_Msk #define RTC_ICSR_RSF_Pos (5U) #define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */ #define RTC_ICSR_RSF RTC_ICSR_RSF_Msk #define RTC_ICSR_INITS_Pos (4U) #define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */ #define RTC_ICSR_INITS RTC_ICSR_INITS_Msk #define RTC_ICSR_SHPF_Pos (3U) #define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */ #define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk #define RTC_ICSR_WUTWF_Pos (2U) #define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */ #define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk /******************** Bits definition for RTC_PRER register *****************/ #define RTC_PRER_PREDIV_A_Pos (16U) #define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk #define RTC_PRER_PREDIV_S_Pos (0U) #define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */ #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk /******************** Bits definition for RTC_WUTR register *****************/ #define RTC_WUTR_WUTOCLR_Pos (16U) #define RTC_WUTR_WUTOCLR_Msk (0xFFFFUL << RTC_WUTR_WUTOCLR_Pos) /*!< 0x0000FFFF */ #define RTC_WUTR_WUTOCLR RTC_WUTR_WUTOCLR_Msk #define RTC_WUTR_WUT_Pos (0U) #define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */ #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk /******************** Bits definition for RTC_CR register *******************/ #define RTC_CR_OUT2EN_Pos (31U) #define RTC_CR_OUT2EN_Msk (0x1UL << RTC_CR_OUT2EN_Pos) /*!< 0x80000000 */ #define RTC_CR_OUT2EN RTC_CR_OUT2EN_Msk /*! 0x01 )))) /****************************** IWDG Instances ********************************/ #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG) /****************************** WWDG Instances ********************************/ #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG) /****************** LPTIM Instances : All supported instances *****************/ #define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1) || \ ((INSTANCE) == LPTIM2) || \ ((INSTANCE) == LPTIM3)) /****************** LPTIM Instances : Encoder mode ****************************/ #define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1) /****************** TIM Instances : All supported instances *******************/ #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM16) || \ ((INSTANCE) == TIM17)) /****************** TIM Instances : supporting 32 bits counter ****************/ #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM2) /****************** TIM Instances : supporting the break function *************/ #define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM16) || \ ((INSTANCE) == TIM17)) /************** TIM Instances : supporting Break source selection *************/ #define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM16) || \ ((INSTANCE) == TIM17)) /****************** TIM Instances : supporting 2 break inputs *****************/ #define IS_TIM_BKIN2_INSTANCE(INSTANCE) ((INSTANCE) == TIM1) /************* TIM Instances : at least 1 capture/compare channel *************/ #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM16) || \ ((INSTANCE) == TIM17)) /************ TIM Instances : at least 2 capture/compare channels *************/ #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2)) /************ TIM Instances : at least 3 capture/compare channels *************/ #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2)) /************ TIM Instances : at least 4 capture/compare channels *************/ #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2)) /****************** TIM Instances : at least 5 capture/compare channels *******/ #define IS_TIM_CC5_INSTANCE(INSTANCE) ((INSTANCE) == TIM1) /****************** TIM Instances : at least 6 capture/compare channels *******/ #define IS_TIM_CC6_INSTANCE(INSTANCE) ((INSTANCE) == TIM1) /****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/ #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM16) || \ ((INSTANCE) == TIM17)) /************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/ #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM16) || \ ((INSTANCE) == TIM17)) /******************** TIM Instances : DMA burst feature ***********************/ #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM16) || \ ((INSTANCE) == TIM17)) /******************* TIM Instances : Timer input selection ********************/ #define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM16) || \ ((INSTANCE) == TIM17)) /******************* TIM Instances : output(s) available **********************/ #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ ((((INSTANCE) == TIM1) && \ (((CHANNEL) == TIM_CHANNEL_1) || \ ((CHANNEL) == TIM_CHANNEL_2) || \ ((CHANNEL) == TIM_CHANNEL_3) || \ ((CHANNEL) == TIM_CHANNEL_4) || \ ((CHANNEL) == TIM_CHANNEL_5) || \ ((CHANNEL) == TIM_CHANNEL_6))) \ || \ (((INSTANCE) == TIM2) && \ (((CHANNEL) == TIM_CHANNEL_1) || \ ((CHANNEL) == TIM_CHANNEL_2) || \ ((CHANNEL) == TIM_CHANNEL_3) || \ ((CHANNEL) == TIM_CHANNEL_4))) \ || \ (((INSTANCE) == TIM16) && \ (((CHANNEL) == TIM_CHANNEL_1))) \ || \ (((INSTANCE) == TIM17) && \ (((CHANNEL) == TIM_CHANNEL_1)))) /****************** TIM Instances : supporting complementary output(s) ********/ #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ ((((INSTANCE) == TIM1) && \ (((CHANNEL) == TIM_CHANNEL_1) || \ ((CHANNEL) == TIM_CHANNEL_2) || \ ((CHANNEL) == TIM_CHANNEL_3))) \ || \ (((INSTANCE) == TIM17) && \ ((CHANNEL) == TIM_CHANNEL_1)) \ || \ (((INSTANCE) == TIM16) && \ ((CHANNEL) == TIM_CHANNEL_1))) /****************** TIM Instances : supporting clock division *****************/ #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM16) || \ ((INSTANCE) == TIM17)) /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/ #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2)) /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/ #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2)) /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/ #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2)) /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/ #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2)) /****************** TIM Instances : supporting combined 3-phase PWM mode ******/ #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) ((INSTANCE) == TIM1) /****************** TIM Instances : supporting commutation event generation ***/ #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM16) || \ ((INSTANCE) == TIM17)) /****************** TIM Instances : supporting counting mode selection ********/ #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2)) /****************** TIM Instances : supporting encoder interface **************/ #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2)) /****************** TIM Instances : supporting Hall sensor interface **********/ #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == TIM1) /**************** TIM Instances : external trigger input available ************/ #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2)) /************* TIM Instances : supporting ETR source selection ***************/ #define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2)) /****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/ #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2)) /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/ #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2)) /****************** TIM Instances : supporting OCxREF clear *******************/ #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2)) /****************** TIM Instances : remapping capability **********************/ #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM16) || \ ((INSTANCE) == TIM17)) /****************** TIM Instances : supporting repetition counter *************/ #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM16) || \ ((INSTANCE) == TIM17)) /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/ #define IS_TIM_TRGO2_INSTANCE(INSTANCE) ((INSTANCE) == TIM1) /******************* TIM Instances : Timer input XOR function *****************/ #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2)) /************ TIM Instances : Advanced timers ********************************/ #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)) /******************** UART Instances : Asynchronous mode **********************/ #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ ((INSTANCE) == USART2)) /******************** USART Instances : Synchronous mode **********************/ #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ ((INSTANCE) == USART2)) /****************** UART Instances : Hardware Flow control ********************/ #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ ((INSTANCE) == USART2) || \ ((INSTANCE) == LPUART1)) /********************* USART Instances : Smard card mode ***********************/ #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ ((INSTANCE) == USART2)) /****************** UART Instances : Auto Baud Rate detection ****************/ #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ ((INSTANCE) == USART2)) /******************** UART Instances : Half-Duplex mode **********************/ #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ ((INSTANCE) == USART2) || \ ((INSTANCE) == LPUART1)) /******************** UART Instances : LIN mode **********************/ #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ ((INSTANCE) == USART2)) /******************** UART Instances : Wake-up from Stop mode **********************/ #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ ((INSTANCE) == USART2) || \ ((INSTANCE) == LPUART1)) /****************** UART Instances : Driver Enable *****************/ #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ ((INSTANCE) == USART2) || \ ((INSTANCE) == LPUART1)) /****************** UART Instances : SPI Slave selection mode ***************/ #define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ ((INSTANCE) == USART2)) /****************** UART Instances : Driver Enable *****************/ #define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ ((INSTANCE) == USART2) || \ ((INSTANCE) == LPUART1)) /*********************** UART Instances : IRDA mode ***************************/ #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ ((INSTANCE) == USART2)) /******************** LPUART Instance *****************************************/ #define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1) /******************************************************************************/ /* For a painless codes migration between the STM32WLxx device product */ /* lines, the aliases defined below are put in place to overcome the */ /* differences in the interrupt handlers and IRQn definitions. */ /* No need to update developed interrupt code when moving across */ /* product lines within the same STM32WL Family */ /******************************************************************************/ /** * @} */ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif /* __cplusplus */ #endif /* __STM32WLE4xx_H */ /** * @} */ /** * @} */