Lines Matching +full:fail +full:- +full:fast
10 * - Data structures and the address mapping for all peripherals
11 * - Peripheral's registers declarations and bits definition
12 * - Macros to access peripheral's registers hardware
17 * Copyright (c) 2019-2022 STMicroelectronics.
22 * If no LICENSE file comes with this software, it is provided AS-IS.
46 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
69 …/****** Cortex-M4 Processor Exceptions Numbers **************************************************…
70 …NonMaskableInt_IRQn = -14, /*!< Non Maskable Interrupt …
71 …HardFault_IRQn = -13, /*!< Cortex-M4 Hard Fault Interrupt …
72 …MemoryManagement_IRQn = -12, /*!< Cortex-M4 Memory Management Interrupt …
73 …BusFault_IRQn = -11, /*!< Cortex-M4 Bus Fault Interrupt …
74 …UsageFault_IRQn = -10, /*!< Cortex-M4 Usage Fault Interrupt …
75 …SVCall_IRQn = -5, /*!< Cortex-M4 SV Call Interrupt …
76 …DebugMonitor_IRQn = -4, /*!< Cortex-M4 Debug Monitor Interrupt …
77 …PendSV_IRQn = -2, /*!< Cortex-M4 Pend SV Interrupt …
78 …SysTick_IRQn = -1, /*!< Cortex-M4 System Tick Interrupt …
134 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
159 … uint32_t RESERVED5[4]; /*!< Reserved, 0x30 - 0x3C */
161 … uint32_t RESERVED6[23];/*!< Reserved, 0x44 - 0x9C */
164 … uint32_t RESERVED9[3]; /*!< Reserved, 0xA8 - 0xB0 */
208 …uint32_t RESERVED1[13]; /*!< Reserved, 0x08-0x38 …
281 …ED2[7]; /*!< Reserved, Address offset: 0x40-0x58 */
285 …ED3[6]; /*!< Reserved, Address offset: 0x68-0x7C */
298 …__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
303 …__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
308 * @brief Inter-integrated Circuit Interface
366 …__IO uint32_t PUCRA; /*!< PWR Pull-Up Control Register of port A, Address offset:…
367 …__IO uint32_t PDCRA; /*!< PWR Pull-Down Control Register of port A, Address offset:…
368 …__IO uint32_t PUCRB; /*!< PWR Pull-Up Control Register of port B, Address offset:…
369 …__IO uint32_t PDCRB; /*!< PWR Pull-Down Control Register of port B, Address offset:…
370 …__IO uint32_t PUCRC; /*!< PWR Pull-Up Control Register of port C, Address offset:…
371 …__IO uint32_t PDCRC; /*!< PWR Pull-Down Control Register of port C, Address offset:…
372 …t RESERVED2[2]; /*!< Reserved, Address offset: 0x38-0x3C */
373 …__IO uint32_t PUCRE; /*!< PWR Pull-Up Control Register of port E, Address offset:…
374 …__IO uint32_t PDCRE; /*!< PWR Pull-Down Control Register of port E, Address offset:…
375 …t RESERVED0[4]; /*!< Reserved, Address offset: 0x48-0x54 */
376 …__IO uint32_t PUCRH; /*!< PWR Pull-Up Control Register of port H, Address offset:…
377 …__IO uint32_t PDCRH; /*!< PWR Pull-Down Control Register of port H, Address offset:…
378 …t RESERVED1[8]; /*!< Reserved, Address offset: 0x60-0x7C */
393 … Address offset: 0x10-0x14 */
397 …__IO uint32_t SMPSCR; /*!< RCC SMPS step-down converter control register, …
428 … Address offset: 0xA0-0x104 */
430 … Address offset: 0x10C-0x144 */
452 * @brief Real-Time Clock
470 …__IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address …
522 …SCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
528 …served, Address offset: 0x2C-0xFC */
529 …__IO uint32_t IMR1; /*!< SYSCFG CPU1 (CORTEX M4) interrupt masks control-status regis…
530 …__IO uint32_t IMR2; /*!< SYSCFG CPU1 (CORTEX M4) interrupt masks control-status regis…
531 …__IO uint32_t C2IMR1; /*!< SYSCFG CPU2 (CORTEX M0) interrupt masks control-status regis…
532 …__IO uint32_t C2IMR2; /*!< SYSCFG CPU2 (CORTEX M0) interrupt masks control-status regis…
553 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
559 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
660 …__IO uint32_t IOGXCR[7]; /*!< TSC I/O group x counter register, Address offset: 0x34-4…
664 * @brief Inter-Processor Communication
668 …__IO uint32_t C1CR; /*!< Inter-Processor Communication: C1 control register, …
669 …__IO uint32_t C1MR ; /*!< Inter-Processor Communication: C1 mask register, …
670 …__IO uint32_t C1SCR; /*!< Inter-Processor Communication: C1 status set clear register, …
671 …__IO uint32_t C1TOC2SR; /*!< Inter-Processor Communication: C1 to processor M4 status reg…
672 …__IO uint32_t C2CR; /*!< Inter-Processor Communication: C2 control register, …
673 …__IO uint32_t C2MR ; /*!< Inter-Processor Communication: C2 mask register, …
674 …__IO uint32_t C2SCR; /*!< Inter-Processor Communication: C2 status set clear register, …
675 …__IO uint32_t C2TOC1SR; /*!< Inter-Processor Communication: C2 to processor M4 status regi…
695 …4]; /*!< Reserved, Address offset: 0x10 - 0x1C */
700 …4]; /*!< Reserved, Address offset: 0x30 - 0x3C */
701 …8]; /*!< Reserved, Address offset: 0x40 - 0x5C */
702 …8]; /*!< Reserved, Address offset: 0x60 - 0x7C */
705 …2]; /*!< Reserved, Address offset: 0x88 - 0x8C */
708 …10]; /*!< Reserved, Address offset: 0x98 - 0xBC */
711 …2]; /*!< Reserved, Address offset: 0xC8 - 0xCC */
724 …uint32_t Reserved1[253]; /*!< Reserved Address offset: 0x000C-0x03F…
725 …__IO uint32_t RAM[894]; /*!< PKA RAM, Address offset: 0x0400-0x11F…
733 …__IO uint32_t R[32]; /*!< HSEM 2-step write lock and read back registers, Address offset: 0…
734 …__IO uint32_t RLR[32]; /*!< HSEM 1-step read lock registers, Address offset: 8…
743 …32_t Reserved[8]; /*!< Reserved Address offset: 120h-13Ch*/
772 #define SYSTEM_MEMORY_BASE (0x1FFF0000UL) /*!< System Memory : 28Kb (0x1FFF0000 - 0x1FFF6FFF) …
773 #define OTP_AREA_BASE (0x1FFF7000UL) /*!< OTP area : 1kB (0x1FFF7000 - 0x1FFF73FF) …
774 #define OPTION_BYTE_BASE (0x1FFF7800UL) /*!< Option Bytes : 128B (0x1FFF7800 - 0x1FFF787F) …
775 #define ENGI_BYTE_BASE (0x1FFF7400UL) /*!< Engi Bytes : 3kB (0x1FFF7400 - 0x1FFF7FFF) …
788 #define SRAM1_END_ADDR (0x20002FFFUL) /*!< SRAM1 : 12KB (0x20000000 - 0x200…
789 #define SRAM2A_END_ADDR (0x20037FFFUL) /*!< SRAM2a (backup) : 32KB (0x20030000 - 0x200…
790 #define SRAM2B_END_ADDR (0x20038FFFUL) /*!< SRAM2b (backup) : 4KB (0x20038000 - 0x200…
792 #define SYSTEM_MEMORY_END_ADDR (0x1FFF6FFFUL) /*!< System Memory : 28KB (0x1FFF0000 - 0x1FFF6FFF) …
793 #define OTP_AREA_END_ADDR (0x1FFF73FFUL) /*!< OTP area : 1KB (0x1FFF7000 - 0x1FFF73FF) …
794 #define OPTION_BYTE_END_ADDR (0x1FFF8FFFUL) /*!< Option Bytes : 4KB (0x1FFF8000 - 0x1FFF8FFF) …
795 #define ENGI_BYTE_END_ADDR (0x1FFF7FFFUL) /*!< Engi Bytes : 3kB (0x1FFF7400 - 0x1FFF7FFF) …
882 #define UID64_BASE ((uint32_t)0x1FFF7580UL) /*!< 64-bit Unique device Identificati…
1536 … ADC_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */
1635 … CRC_IDR_IDR_Msk /*!< General-purpose 8-bits data regist…
3051 #define PKA_MONTGOMERY_PARAM_IN_MOD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input modul…
3052 #define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input modul…
3055 #define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x594U - PKA_RAM_OFFSET)>>2) /*!< Output Mont…
3058 #define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Input expon…
3059 #define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3060 #define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x594U - PKA_RAM_OFFSET)>>2) /*!< Input stora…
3061 #define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input base …
3062 #define PKA_MODULAR_EXP_IN_EXPONENT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Input expon…
3063 #define PKA_MODULAR_EXP_IN_MODULUS ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input modul…
3066 #define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x594U - PKA_RAM_OFFSET)>>2) /*!< Output stor…
3067 #define PKA_MODULAR_EXP_OUT_SM_ALGO_ACC1 ((0x724U - PKA_RAM_OFFSET)>>2) /*!< Output SM a…
3068 #define PKA_MODULAR_EXP_OUT_SM_ALGO_ACC2 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Output SM a…
3069 #define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Output base…
3070 #define PKA_MODULAR_EXP_OUT_SM_ALGO_ACC3 ((0xE3CU - PKA_RAM_OFFSET)>>2) /*!< Output SM a…
3073 #define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Input expon…
3074 #define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3075 #define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x408U - PKA_RAM_OFFSET)>>2) /*!< Input sign …
3076 #define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x40CU - PKA_RAM_OFFSET)>>2) /*!< Input ECC c…
3077 #define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x460U - PKA_RAM_OFFSET)>>2) /*!< Input modul…
3078 #define PKA_ECC_SCALAR_MUL_IN_MONTGOMERY_PARAM ((0x4B4U - PKA_RAM_OFFSET)>>2) /*!< Input stora…
3079 #define PKA_ECC_SCALAR_MUL_IN_K ((0x508U - PKA_RAM_OFFSET)>>2) /*!< Input 'k' o…
3080 #define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x55CU - PKA_RAM_OFFSET)>>2) /*!< Input initi…
3081 #define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Input initi…
3084 #define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x55CU - PKA_RAM_OFFSET)>>2) /*!< Output resu…
3085 #define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Output resu…
3086 #define PKA_ECC_SCALAR_MUL_OUT_LAST_DOUBLE_X1 ((0xDE8U - PKA_RAM_OFFSET)>>2) /*!< Output last…
3087 #define PKA_ECC_SCALAR_MUL_OUT_LAST_DOUBLE_Y1 ((0xE3CU - PKA_RAM_OFFSET)>>2) /*!< Output last…
3088 #define PKA_ECC_SCALAR_MUL_OUT_LAST_DOUBLE_Z1 ((0xE90U - PKA_RAM_OFFSET)>>2) /*!< Output last…
3089 #define PKA_ECC_SCALAR_MUL_OUT_CHECK_POINT_X2 ((0xEE4U - PKA_RAM_OFFSET)>>2) /*!< Output chec…
3090 #define PKA_ECC_SCALAR_MUL_OUT_CHECK_POINT_Y2 ((0xF38U - PKA_RAM_OFFSET)>>2) /*!< Output chec…
3091 #define PKA_ECC_SCALAR_MUL_OUT_CHECK_POINT_Z2 ((0xF8CU - PKA_RAM_OFFSET)>>2) /*!< Output chec…
3094 #define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input modul…
3095 #define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x408U - PKA_RAM_OFFSET)>>2) /*!< Input sign …
3096 #define PKA_POINT_CHECK_IN_A_COEFF ((0x40CU - PKA_RAM_OFFSET)>>2) /*!< Input ECC c…
3097 #define PKA_POINT_CHECK_IN_B_COEFF ((0x7FCU - PKA_RAM_OFFSET)>>2) /*!< Input ECC c…
3098 #define PKA_POINT_CHECK_IN_MOD_GF ((0x460U - PKA_RAM_OFFSET)>>2) /*!< Input modul…
3099 #define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x55CU - PKA_RAM_OFFSET)>>2) /*!< Input initi…
3100 #define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Input initi…
3103 #define PKA_POINT_CHECK_OUT_ERROR ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Output erro…
3106 #define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Input order…
3107 #define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input modul…
3108 #define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x408U - PKA_RAM_OFFSET)>>2) /*!< Input sign …
3109 #define PKA_ECDSA_SIGN_IN_A_COEFF ((0x40CU - PKA_RAM_OFFSET)>>2) /*!< Input ECC c…
3110 #define PKA_ECDSA_SIGN_IN_MOD_GF ((0x460U - PKA_RAM_OFFSET)>>2) /*!< Input modul…
3111 #define PKA_ECDSA_SIGN_IN_K ((0x508U - PKA_RAM_OFFSET)>>2) /*!< Input k val…
3112 #define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x55CU - PKA_RAM_OFFSET)>>2) /*!< Input initi…
3113 #define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Input initi…
3114 #define PKA_ECDSA_SIGN_IN_HASH_E ((0xDE8U - PKA_RAM_OFFSET)>>2) /*!< Input e, ha…
3115 #define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0xE3CU - PKA_RAM_OFFSET)>>2) /*!< Input d, pr…
3116 #define PKA_ECDSA_SIGN_IN_ORDER_N ((0xE94U - PKA_RAM_OFFSET)>>2) /*!< Input n, or…
3119 #define PKA_ECDSA_SIGN_OUT_ERROR ((0xEE8U - PKA_RAM_OFFSET)>>2) /*!< Output erro…
3120 #define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x700U - PKA_RAM_OFFSET)>>2) /*!< Output sign…
3121 #define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x754U - PKA_RAM_OFFSET)>>2) /*!< Output sign…
3122 #define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x103CU - PKA_RAM_OFFSET)>>2) /*!< Output fina…
3123 #define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1090U - PKA_RAM_OFFSET)>>2) /*!< Output fina…
3126 #define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input order…
3127 #define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x4B4U - PKA_RAM_OFFSET)>>2) /*!< Input modul…
3128 #define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x45CU - PKA_RAM_OFFSET)>>2) /*!< Input sign …
3129 #define PKA_ECDSA_VERIF_IN_A_COEFF ((0x460U - PKA_RAM_OFFSET)>>2) /*!< Input ECC c…
3130 #define PKA_ECDSA_VERIF_IN_MOD_GF ((0x4B8U - PKA_RAM_OFFSET)>>2) /*!< Input modul…
3131 #define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x5E8U - PKA_RAM_OFFSET)>>2) /*!< Input initi…
3132 #define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x63CU - PKA_RAM_OFFSET)>>2) /*!< Input initi…
3133 #define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0xF40U - PKA_RAM_OFFSET)>>2) /*!< Input publi…
3134 #define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0xF94U - PKA_RAM_OFFSET)>>2) /*!< Input publi…
3135 #define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x1098U - PKA_RAM_OFFSET)>>2) /*!< Input r, pa…
3136 #define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input s, pa…
3137 #define PKA_ECDSA_VERIF_IN_HASH_E ((0xFE8U - PKA_RAM_OFFSET)>>2) /*!< Input e, ha…
3138 #define PKA_ECDSA_VERIF_IN_ORDER_N ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input n, or…
3141 #define PKA_ECDSA_VERIF_OUT_RESULT ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Output resu…
3144 #define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3145 #define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x65CU - PKA_RAM_OFFSET)>>2) /*!< Input Dp CR…
3146 #define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Input Dq CR…
3147 #define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x7ECU - PKA_RAM_OFFSET)>>2) /*!< Input qInv …
3148 #define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x97CU - PKA_RAM_OFFSET)>>2) /*!< Input Prime…
3149 #define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input Prime…
3150 #define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0xEECU - PKA_RAM_OFFSET)>>2) /*!< Input base …
3153 #define PKA_RSA_CRT_EXP_OUT_RESULT ((0x724U - PKA_RAM_OFFSET)>>2) /*!< Output resu…
3156 #define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3157 #define PKA_MODULAR_REDUC_IN_OPERAND ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3158 #define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input modul…
3159 #define PKA_MODULAR_REDUC_IN_MODULUS ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input modul…
3162 #define PKA_MODULAR_REDUC_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output resu…
3165 #define PKA_ARITHMETIC_ADD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3166 #define PKA_ARITHMETIC_ADD_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3167 #define PKA_ARITHMETIC_ADD_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3170 #define PKA_ARITHMETIC_ADD_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output resu…
3173 #define PKA_ARITHMETIC_SUB_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3174 #define PKA_ARITHMETIC_SUB_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3175 #define PKA_ARITHMETIC_SUB_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3178 #define PKA_ARITHMETIC_SUB_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output resu…
3181 #define PKA_ARITHMETIC_MUL_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3182 #define PKA_ARITHMETIC_MUL_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3183 #define PKA_ARITHMETIC_MUL_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3186 #define PKA_ARITHMETIC_MUL_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output resu…
3189 #define PKA_COMPARISON_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3190 #define PKA_COMPARISON_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3191 #define PKA_COMPARISON_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3194 #define PKA_COMPARISON_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output resu…
3197 #define PKA_MODULAR_ADD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3198 #define PKA_MODULAR_ADD_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3199 #define PKA_MODULAR_ADD_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3200 #define PKA_MODULAR_ADD_IN_OP3_MOD ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3203 #define PKA_MODULAR_ADD_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output resu…
3206 #define PKA_MODULAR_INV_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3207 #define PKA_MODULAR_INV_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3208 #define PKA_MODULAR_INV_IN_OP2_MOD ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3211 #define PKA_MODULAR_INV_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output resu…
3214 #define PKA_MODULAR_SUB_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3215 #define PKA_MODULAR_SUB_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3216 #define PKA_MODULAR_SUB_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3217 #define PKA_MODULAR_SUB_IN_OP3_MOD ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3220 #define PKA_MODULAR_SUB_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output resu…
3223 #define PKA_MONTGOMERY_MUL_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3224 #define PKA_MONTGOMERY_MUL_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3225 #define PKA_MONTGOMERY_MUL_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3226 #define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input modul…
3229 #define PKA_MONTGOMERY_MUL_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output resu…
3232 #define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3233 #define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3234 #define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3235 #define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3238 #define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output resu…
3303 #define FLASH_SR_MISERR FLASH_SR_MISERR_Msk /*!< Fast programmin…
3306 #define FLASH_SR_FASTERR FLASH_SR_FASTERR_Msk /*!< Fast programmin…
3347 #define FLASH_CR_FSTPG FLASH_CR_FSTPG_Msk /*!< Fast programmin…
3370 …CC FLASH_ECCR_ADDR_ECC_Msk /*!< double-word address ECC fail …
3373 … FLASH_ECCR_SYSF_ECC_Msk /*!< System flash ECC fail …
3573 #define FLASH_C2SR_MISERR FLASH_C2SR_MISERR_Msk /*!< CPU2 Fast progra…
3576 #define FLASH_C2SR_FASTERR FLASH_C2SR_FASTERR_Msk /*!< CPU2 Fast progra…
3608 #define FLASH_C2CR_FSTPG FLASH_C2CR_FSTPG_Msk /*!< CPU2 Fast progra…
5166 /* Inter-integrated Circuit Interface (I2C) */
5243 #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressi…
5246 #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address …
5275 …AR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
5437 #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive d…
5442 #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit …
5511 #define PWR_CR1_LPR PWR_CR1_LPR_Msk /*!< Regulator Low-P…
5535 … PWR_CR3_EWUP_Msk /*!< Enable all external Wake-Up lines */
5553 … PWR_CR3_APC_Msk /*!< Apply pull-up and pull-down configurat…
5567 #define PWR_CR3_EIWUL PWR_CR3_EIWUL_Msk /*!< Internal Wake-U…
5572 #define PWR_CR4_WP PWR_CR4_WP_Msk /*!< Wake-Up polarit…
5575 #define PWR_CR4_WP1 PWR_CR4_WP1_Msk /*!< Wake-Up Pin 1 […
5578 #define PWR_CR4_WP4 PWR_CR4_WP4_Msk /*!< Wake-Up Pin 4 […
5639 #define PWR_SR2_REGLPS PWR_SR2_REGLPS_Msk /*!< Low-power regul…
5642 #define PWR_SR2_REGLPF PWR_SR2_REGLPF_Msk /*!< Low-power regul…
5655 #define PWR_SCR_CWUF PWR_SCR_CWUF_Msk /*!< Clear Wake-up F…
5658 #define PWR_SCR_CWUF1 PWR_SCR_CWUF1_Msk /*!< Clear Wake-up P…
5661 #define PWR_SCR_CWUF4 PWR_SCR_CWUF4_Msk /*!< Clear Wake-up P…
5713 #define PWR_PUCRA_PA0 PWR_PUCRA_PA0_Msk /*!< Pin PA0 Pull-Up…
5716 #define PWR_PUCRA_PA1 PWR_PUCRA_PA1_Msk /*!< Pin PA1 Pull-Up…
5719 #define PWR_PUCRA_PA2 PWR_PUCRA_PA2_Msk /*!< Pin PA2 Pull-Up…
5722 #define PWR_PUCRA_PA3 PWR_PUCRA_PA3_Msk /*!< Pin PA3 Pull-Up…
5725 #define PWR_PUCRA_PA4 PWR_PUCRA_PA4_Msk /*!< Pin PA4 Pull-Up…
5728 #define PWR_PUCRA_PA5 PWR_PUCRA_PA5_Msk /*!< Pin PA5 Pull-Up…
5731 #define PWR_PUCRA_PA6 PWR_PUCRA_PA6_Msk /*!< Pin PA6 Pull-Up…
5734 #define PWR_PUCRA_PA7 PWR_PUCRA_PA7_Msk /*!< Pin PA7 Pull-Up…
5737 #define PWR_PUCRA_PA8 PWR_PUCRA_PA8_Msk /*!< Pin PA8 Pull-Up…
5740 #define PWR_PUCRA_PA9 PWR_PUCRA_PA9_Msk /*!< Pin PA9 Pull-Up…
5743 #define PWR_PUCRA_PA10 PWR_PUCRA_PA10_Msk /*!< Pin PA10 Pull-U…
5746 #define PWR_PUCRA_PA11 PWR_PUCRA_PA11_Msk /*!< Pin PA11 Pull-U…
5749 #define PWR_PUCRA_PA12 PWR_PUCRA_PA12_Msk /*!< Pin PA12 Pull-U…
5752 #define PWR_PUCRA_PA13 PWR_PUCRA_PA13_Msk /*!< Pin PA13 Pull-U…
5755 #define PWR_PUCRA_PA15 PWR_PUCRA_PA15_Msk /*!< Pin PA15 Pull-U…
5760 #define PWR_PDCRA_PA0 PWR_PDCRA_PA0_Msk /*!< Pin PA0 Pull-Do…
5763 #define PWR_PDCRA_PA1 PWR_PDCRA_PA1_Msk /*!< Pin PA1 Pull-Do…
5766 #define PWR_PDCRA_PA2 PWR_PDCRA_PA2_Msk /*!< Pin PA2 Pull-Do…
5769 #define PWR_PDCRA_PA3 PWR_PDCRA_PA3_Msk /*!< Pin PA3 Pull-Do…
5772 #define PWR_PDCRA_PA4 PWR_PDCRA_PA4_Msk /*!< Pin PA4 Pull-Do…
5775 #define PWR_PDCRA_PA5 PWR_PDCRA_PA5_Msk /*!< Pin PA5 Pull-Do…
5778 #define PWR_PDCRA_PA6 PWR_PDCRA_PA6_Msk /*!< Pin PA6 Pull-Do…
5781 #define PWR_PDCRA_PA7 PWR_PDCRA_PA7_Msk /*!< Pin PA7 Pull-Do…
5784 #define PWR_PDCRA_PA8 PWR_PDCRA_PA8_Msk /*!< Pin PA8 Pull-Do…
5787 #define PWR_PDCRA_PA9 PWR_PDCRA_PA9_Msk /*!< Pin PA9 Pull-Do…
5790 #define PWR_PDCRA_PA10 PWR_PDCRA_PA10_Msk /*!< Pin PA10 Pull-D…
5793 #define PWR_PDCRA_PA11 PWR_PDCRA_PA11_Msk /*!< Pin PA11 Pull-D…
5796 #define PWR_PDCRA_PA12 PWR_PDCRA_PA12_Msk /*!< Pin PA12 Pull-D…
5799 #define PWR_PDCRA_PA14 PWR_PDCRA_PA14_Msk /*!< Pin PA14 Pull-D…
5804 #define PWR_PUCRB_PB0 PWR_PUCRB_PB0_Msk /*!< Pin PB0 Pull-Up…
5807 #define PWR_PUCRB_PB1 PWR_PUCRB_PB1_Msk /*!< Pin PB1 Pull-Up…
5810 #define PWR_PUCRB_PB2 PWR_PUCRB_PB2_Msk /*!< Pin PB2 Pull-Up…
5813 #define PWR_PUCRB_PB3 PWR_PUCRB_PB3_Msk /*!< Pin PB3 Pull-Up…
5816 #define PWR_PUCRB_PB4 PWR_PUCRB_PB4_Msk /*!< Pin PB4 Pull-Up…
5819 #define PWR_PUCRB_PB5 PWR_PUCRB_PB5_Msk /*!< Pin PB5 Pull-Up…
5822 #define PWR_PUCRB_PB6 PWR_PUCRB_PB6_Msk /*!< Pin PB6 Pull-Up…
5825 #define PWR_PUCRB_PB7 PWR_PUCRB_PB7_Msk /*!< Pin PB7 Pull-Up…
5828 #define PWR_PUCRB_PB8 PWR_PUCRB_PB8_Msk /*!< Pin PB8 Pull-Up…
5831 #define PWR_PUCRB_PB9 PWR_PUCRB_PB9_Msk /*!< Pin PB9 Pull-Up…
5836 #define PWR_PDCRB_PB0 PWR_PDCRB_PB0_Msk /*!< Pin PB0 Pull-Do…
5839 #define PWR_PDCRB_PB1 PWR_PDCRB_PB1_Msk /*!< Pin PB1 Pull-Do…
5842 #define PWR_PDCRB_PB2 PWR_PDCRB_PB2_Msk /*!< Pin PB2 Pull-Do…
5845 #define PWR_PDCRB_PB3 PWR_PDCRB_PB3_Msk /*!< Pin PB3 Pull-Do…
5848 #define PWR_PDCRB_PB5 PWR_PDCRB_PB5_Msk /*!< Pin PB5 Pull-Do…
5851 #define PWR_PDCRB_PB6 PWR_PDCRB_PB6_Msk /*!< Pin PB6 Pull-Do…
5854 #define PWR_PDCRB_PB7 PWR_PDCRB_PB7_Msk /*!< Pin PB7 Pull-Do…
5857 #define PWR_PDCRB_PB8 PWR_PDCRB_PB8_Msk /*!< Pin PB8 Pull-Do…
5860 #define PWR_PDCRB_PB9 PWR_PDCRB_PB9_Msk /*!< Pin PB9 Pull-Do…
5865 #define PWR_PUCRC_PC14 PWR_PUCRC_PC14_Msk /*!< Pin PC14 Pull-U…
5868 #define PWR_PUCRC_PC15 PWR_PUCRC_PC15_Msk /*!< Pin PC15 Pull-U…
5873 #define PWR_PDCRC_PC14 PWR_PDCRC_PC14_Msk /*!< Pin PC14 Pull-D…
5876 #define PWR_PDCRC_PC15 PWR_PDCRC_PC15_Msk /*!< Pin PC15 Pull-D…
5881 #define PWR_PUCRE_PE4 PWR_PUCRE_PE4_Msk /*!< Pin PE4 Pull-Up…
5886 #define PWR_PDCRE_PE4 PWR_PDCRE_PE4_Msk /*!< Pin PE4 Pull-Do…
5891 #define PWR_PUCRH_PH3 PWR_PUCRH_PH3_Msk /*!< Pin PH3 Pull-Up…
5896 #define PWR_PDCRH_PH3 PWR_PDCRH_PH3_Msk /*!< Pin PH3 Pull-Do…
5921 … PWR_C2CR3_EWUP_Msk /*!< Enable all external Wake-Up lines for CPU2 */
5935 … PWR_C2CR3_APC_Msk /*!< Apply pull-up and pull-down configurat…
5939 #define PWR_C2CR3_EIWUL PWR_C2CR3_EIWUL_Msk /*!< Internal Wake-U…
7049 /* Real-Time Clock (RTC) */
7177 #define RTC_CR_TSIE RTC_CR_TSIE_Msk /*!< Time-stamp inte…
7279 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk /*!< Wakeup auto-rel…
7523 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk /*!< Use a 8-second …
7526 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk /*!< Use a 16-second…
7552 #define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk /*!< RTC_TAMPx pull-…
7585 … RTC_ALRMASSR_MASKSS_Msk /*!< Alarm A mask the most-significant bits star…
7597 … RTC_ALRMBSSR_MASKSS_Msk /*!< Alarm B mask the most-significant bits star…
8369 …6_FMP SYSCFG_CFGR1_I2C_PB6_FMP_Msk /*!< Fast-mode Plus (Fm+) dri…
8372 …7_FMP SYSCFG_CFGR1_I2C_PB7_FMP_Msk /*!< Fast-mode Plus (Fm+) dri…
8375 …8_FMP SYSCFG_CFGR1_I2C_PB8_FMP_Msk /*!< Fast-mode Plus (Fm+) dri…
8378 …9_FMP SYSCFG_CFGR1_I2C_PB9_FMP_Msk /*!< Fast-mode Plus (Fm+) dri…
8381 … SYSCFG_CFGR1_I2C1_FMP_Msk /*!< I2C1 Fast-mode Plus (Fm+) dri…
8580 …GE0_Msk /*!< SRAM2A Write protection page 0 (0x20030000 - 0x200303FF) */
8583 …GE1_Msk /*!< SRAM2A Write protection page 1 (0x20030400 - 0x200307FF) */
8586 …GE2_Msk /*!< SRAM2A Write protection page 2 (0x20030800 - 0x20030BFF) */
8589 …GE3_Msk /*!< SRAM2A Write protection page 3 (0x20030C00 - 0x20030FFF) */
8592 …GE4_Msk /*!< SRAM2A Write protection page 4 (0x20031000 - 0x200313FF) */
8595 …GE5_Msk /*!< SRAM2A Write protection page 5 (0x20031400 - 0x200317FF) */
8598 …GE6_Msk /*!< SRAM2A Write protection page 6 (0x20031800 - 0x20031BFF) */
8601 …GE7_Msk /*!< SRAM2A Write protection page 7 (0x20031C00 - 0x20031FFF) */
8604 …GE8_Msk /*!< SRAM2A Write protection page 8 (0x20032000 - 0x200323FF) */
8607 …GE9_Msk /*!< SRAM2A Write protection page 9 (0x20032400 - 0x200327FF) */
8610 …GE10_Msk /*!< SRAM2A Write protection page 10 (0x20032800 - 0x20032BFF) */
8613 …GE11_Msk /*!< SRAM2A Write protection page 11 (0x20032C00 - 0x20032FFF) */
8616 …GE12_Msk /*!< SRAM2A Write protection page 12 (0x20033000 - 0x200333FF) */
8619 …GE13_Msk /*!< SRAM2A Write protection page 13 (0x20033400 - 0x200337FF) */
8622 …GE14_Msk /*!< SRAM2A Write protection page 14 (0x20033800 - 0x20033BFF) */
8625 …GE15_Msk /*!< SRAM2A Write protection page 15 (0x20033C00 - 0x20033FFF) */
8628 …GE16_Msk /*!< SRAM2A Write protection page 16 (0x20034000 - 0x200343FF) */
8631 …GE17_Msk /*!< SRAM2A Write protection page 17 (0x20034400 - 0x200347FF) */
8634 …GE18_Msk /*!< SRAM2A Write protection page 18 (0x20034800 - 0x20034BFF) */
8637 …GE19_Msk /*!< SRAM2A Write protection page 19 (0x20034C00 - 0x20034FFF) */
8640 …GE20_Msk /*!< SRAM2A Write protection page 20 (0x20035000 - 0x200353FF) */
8643 …GE21_Msk /*!< SRAM2A Write protection page 21 (0x20035400 - 0x200357FF) */
8646 …GE22_Msk /*!< SRAM2A Write protection page 22 (0x20035800 - 0x20035BFF) */
8649 …GE23_Msk /*!< SRAM2A Write protection page 23 (0x20035C00 - 0x20035FFF) */
8652 …GE24_Msk /*!< SRAM2A Write protection page 24 (0x20036000 - 0x200363FF) */
8655 …GE25_Msk /*!< SRAM2A Write protection page 25 (0x20036400 - 0x200367FF) */
8658 …GE26_Msk /*!< SRAM2A Write protection page 26 (0x20036800 - 0x20036BFF) */
8661 …GE27_Msk /*!< SRAM2A Write protection page 27 (0x20036C00 - 0x20036FFF) */
8664 …GE28_Msk /*!< SRAM2A Write protection page 28 (0x20037000 - 0x200373FF) */
8667 …GE29_Msk /*!< SRAM2A Write protection page 29 (0x20037400 - 0x200377FF) */
8670 …GE30_Msk /*!< SRAM2A Write protection page 30 (0x20037800 - 0x20037BFF) */
8673 …GE31_Msk /*!< SRAM2A Write protection page 31 (0x20037C00 - 0x20037FFF) */
8683 …GE32_Msk /*!< SRAM2B Write protection page 0 (0x20038000 - 0x200383FF) */
8686 …GE33_Msk /*!< SRAM2B Write protection page 1 (0x20038400 - 0x200387FF) */
8689 …GE34_Msk /*!< SRAM2B Write protection page 2 (0x20038800 - 0x20038bFF) */
8692 …GE35_Msk /*!< SRAM2B Write protection page 3 (0x20038C00 - 0x20038FFF) */
8694 …r SYSCFG_IMR1 register (Interrupt masks control and status register on CPU1 - part 1) ************…
8732 …r SYSCFG_IMR2 register (Interrupt masks control and status register on CPU1 - part 2) ************…
8740 …SYSCFG_C2IMR1 register (Interrupt masks control and status register on CPU2 - part 1) ************…
8818 …SYSCFG_C2IMR2 register (Interrupt masks control and status register on CPU2 - part 2) ************…
8888 … TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selectio…
8894 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload prel…
9147 …R1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
9172 …R1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
9189 /*----------------------------------------------------------------------------*/
9227 …R2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
9252 …R2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
9269 /*----------------------------------------------------------------------------*/
9301 …R3_OC5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */
9320 …R3_OC6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 6 Fast enable */
9412 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<Actual auto-relo…
9461 … TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
9479 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Select…
9482 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Select…
9512 …BDTR_BKDSRM TIM_BDTR_BKDSRM_Msk /*!<Break disarming/re-arming */
9515 …DTR_BK2DSRM TIM_BDTR_BK2DSRM_Msk /*!<Break2 disarming/re-arming */
9794 /* Inter-Processor Communication Controller (IPCC) */
10169 #define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - …
10178 … USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
10203 #define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - …
10224 #define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit…
10268 #define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate…
10271 … USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
10276 #define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-…
10290 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power…
10293 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Se…
10332 … USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
10388 #define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate…
10453 #define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate…
10456 #define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate…
10568 #define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-B…
10584 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-b…
10718 /*********************** UART Instances : Half-Duplex mode ********************/
10725 /*********************** UART Instances : Wake-up from Stop mode **************/
10947 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/