Lines Matching +full:fail +full:- +full:fast
8 * - Data structures and the address mapping for all peripherals
9 * - Peripheral's registers declarations and bits definition
10 * - Macros to access peripheral's registers hardware
20 * If no LICENSE file comes with this software, it is provided AS-IS.
53 /* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ============…
54 …Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset …
55 …NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempte…
56 …HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault …
57 …MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Vio…
59 …BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other add…
61 …UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Tr…
62 …SecureFault_IRQn = -9, /*!< -9 Secure Fault …
63 …SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction …
64 …DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor …
65 …PendSV_IRQn = -2, /*!< -2 Pendable request for system service …
66 …SysTick_IRQn = -1, /*!< -1 System Tick Timer …
71 …RTC_IRQn = 2, /*!< RTC non-secure interrupt …
75 …FLASH_IRQn = 6, /*!< FLASH non-secure global interrupt …
201 /* ------- Start of section using anonymous unions and disabling warnings ------- */
209 #pragma clang diagnostic ignored "-Wc11-extensions"
210 #pragma clang diagnostic ignored "-Wreserved-id-macro"
223 /* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ------ */
235 #include <core_cm33.h> /*!< ARM Cortex-M33 processor and core peripherals */
267 * @brief Inter-integrated Circuit Interface
292 …__IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offs…
293 …__IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offs…
294 …__IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offs…
295 …__IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offs…
296 …__IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offs…
297 …__IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offs…
298 …__IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offs…
299 …__IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offs…
300 …__IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offs…
354 …_t RESERVED1[168];/*!< Reserved, Address offset: 0x60 -- 0x2FC */
368 …__IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */
371 … uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */
372 …__IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */
380 __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */
406 uint32_t RESERVED1[2];/*!< Reserved, 0x18 - 0x1C */
444 …__IO uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset: …
445 …VED1[2]; /*!< Reserved 1, Address offset: 0x54 -- 0x58 */
449 …VED2[10];/*!< Reserved 2, Address offset: 0x68 -- 0x8C */
457 …VED3[8]; /*!< Reserved 3, Address offset: 0xAC -- 0xC8 */
458 …__IO uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: …
486 uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FC */
487 …t32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FC */
488 …t32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFC */
503 …2_t RESERVED1[17]; /*!< Reserved 1, 0x1C -- 0x5C */
504 …2_t EXTICR[4]; /*!< EXIT External Interrupt Configuration Register, 0x60 -- 0x6C */
506 …2_t RESERVED2[3]; /*!< Reserved 2, 0x74 -- 0x7C */
518 …__IO uint32_t NSKEYR; /*!< FLASH non-secure key register, Address offse…
522 …__IO uint32_t PDKEY1R; /*!< FLASH Bank 1 power-down key register, Address offse…
523 …__IO uint32_t PDKEY2R; /*!< FLASH Bank 2 power-down key register, Address offse…
524 …__IO uint32_t NSSR; /*!< FLASH non-secure status register, Address offse…
526 …__IO uint32_t NSCR; /*!< FLASH non-secure control register, Address offse…
530 …RESERVED3[2]; /*!< Reserved3, Address offset: 0x38-0x3C */
532 …__IO uint32_t NSBOOTADD0R; /*!< FLASH non-secure boot address 0 register, Address offse…
533 …__IO uint32_t NSBOOTADD1R; /*!< FLASH non-secure boot address 1 register, Address offse…
547 …__IO uint32_t SECBB1R1; /*!< FLASH secure block-based bank 1 register 1, Address offse…
548 …__IO uint32_t SECBB1R2; /*!< FLASH secure block-based bank 1 register 2, Address offse…
549 …__IO uint32_t SECBB1R3; /*!< FLASH secure block-based bank 1 register 3, Address offse…
550 …__IO uint32_t SECBB1R4; /*!< FLASH secure block-based bank 1 register 4, Address offse…
551 …RESERVED4[4]; /*!< Reserved4, Address offset: 0x90-0x9C */
552 …__IO uint32_t SECBB2R1; /*!< FLASH secure block-based bank 2 register 1, Address offse…
553 …__IO uint32_t SECBB2R2; /*!< FLASH secure block-based bank 2 register 2, Address offse…
554 …__IO uint32_t SECBB2R3; /*!< FLASH secure block-based bank 2 register 3, Address offse…
555 …__IO uint32_t SECBB2R4; /*!< FLASH secure block-based bank 2 register 4, Address offse…
556 …RESERVED5[4]; /*!< Reserved5, Address offset: 0xB0-0xBC */
559 …RESERVED6[2]; /*!< Reserved6, Address offset: 0xC8-0xCC */
560 …__IO uint32_t PRIVBB1R1; /*!< FLASH privilege block-based bank 1 register 1, Address offse…
561 …__IO uint32_t PRIVBB1R2; /*!< FLASH privilege block-based bank 1 register 2, Address offse…
562 …__IO uint32_t PRIVBB1R3; /*!< FLASH privilege block-based bank 1 register 3, Address offse…
563 …__IO uint32_t PRIVBB1R4; /*!< FLASH privilege block-based bank 1 register 4, Address offse…
564 …RESERVED7[4]; /*!< Reserved7, Address offset: 0xE0-0xEC */
565 …__IO uint32_t PRIVBB2R1; /*!< FLASH privilege block-based bank 2 register 1, Address offse…
566 …__IO uint32_t PRIVBB2R2; /*!< FLASH privilege block-based bank 2 register 2, Address offse…
567 …__IO uint32_t PRIVBB2R3; /*!< FLASH privilege block-based bank 2 register 3, Address offse…
568 …__IO uint32_t PRIVBB2R4; /*!< FLASH privilege block-based bank 2 register 4, Address offse…
594 …__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
599 …__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
601 …__IO uint32_t HSLVR; /*!< GPIO high-speed low voltage register, Address offset: 0x2C */
611 … Reserved1, Address offset: 0x04-0x0C */
619 … Reserved3, Address offset: 0x2C-0x3C */
620 …__IO uint32_t MPCWM1ACFGR; /*!< TZSC memory 1 sub-region A watermark configuration register, …
621 …__IO uint32_t MPCWM1AR; /*!< TZSC memory 1 sub-region A watermark register, …
622 …__IO uint32_t MPCWM1BCFGR; /*!< TZSC memory 1 sub-region B watermark configuration register, …
623 …__IO uint32_t MPCWM1BR; /*!< TZSC memory 1 sub-region B watermark register, …
624 …__IO uint32_t MPCWM2ACFGR; /*!< TZSC memory 2 sub-region A watermark configuration register, …
625 …__IO uint32_t MPCWM2AR; /*!< TZSC memory 2 sub-region A watermark register, …
626 …__IO uint32_t MPCWM2BCFGR; /*!< TZSC memory 2 sub-region B watermark configuration register, …
627 …__IO uint32_t MPCWM2BR; /*!< TZSC memory 2 sub-region B watermark register, …
628 …__IO uint32_t MPCWM3ACFGR; /*!< TZSC memory 3 sub-region A watermark configuration register, …
629 …__IO uint32_t MPCWM3AR; /*!< TZSC memory 3 sub-region A watermark register, …
630 … Reserved4, Address offset: 0x68-0x6C */
631 …__IO uint32_t MPCWM4ACFGR; /*!< TZSC memory 4 sub-region A watermark configuration register, …
632 …__IO uint32_t MPCWM4AR; /*!< TZSC memory 4 sub-region A watermark register, …
633 … Reserved5, Address offset: 0x78-0x7C */
634 …__IO uint32_t MPCWM5ACFGR; /*!< TZSC memory 5 sub-region A watermark configuration register, …
635 …__IO uint32_t MPCWM5AR; /*!< TZSC memory 5 sub-region A watermark register, …
636 …__IO uint32_t MPCWM5BCFGR; /*!< TZSC memory 5 sub-region B watermark configuration register, …
637 …__IO uint32_t MPCWM5BR; /*!< TZSC memory 5 sub-region B watermark register, …
643 … RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */
645 … RESERVED2[59]; /*!< Reserved2, Address offset: 0x14-0xFC */
646 …t32_t SECCFGR[32]; /*!< MPCBBx security configuration registers, Address offset: 0x100-0x180 */
647 … RESERVED3[32]; /*!< Reserved3, Address offset: 0x180-0x200 */
648 …t32_t PRIVCFGR[32]; /*!< MPCBBx privilege configuration registers, Address offset: 0x200-0x280 */
678 …uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C …
683 …uint32_t RESERVED2[240]; /*!< Reserved, Address offset: 0x30-0x3EC */
701 … uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x18-0x1C */
719 __IO uint32_t RESERVED1[4]; /*!< Reserved, 0x018 - 0x024 */
739 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
745 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
819 …uint32_t RESERVED1[6]; /*!< Reserved, 0x08-0x1C …
834 …__IO uint32_t OLDCR; /*!< MDF Out-Of Limit Detector Control Register, Address offset:…
846 …uint32_t RESERVED1[9]; /*!< Reserved, 0xC8-0xE8 …
863 …RVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */
866 …RVED2[6]; /*!< Reserved, Address offset: 0x028-0x03C */
872 …RVED5[11]; /*!< Reserved, Address offset: 0x054-0x07C */
878 …RVED8[27]; /*!< Reserved, Address offset: 0x094-0x0FC */
884 …RVED11[3]; /*!< Reserved, Address offset: 0x114-0x11C */
886 …RVED12[3]; /*!< Reserved, Address offset: 0x124-0x12C */
888 …RVED13[3]; /*!< Reserved, Address offset: 0x134-0x13C */
894 …RVED16[3]; /*!< Reserved, Address offset: 0x154-0x15C */
896 …RVED17[7]; /*!< Reserved, Address offset: 0x164-0x17C */
902 …RVED20[3]; /*!< Reserved, Address offset: 0x194-0x19C */
904 …RVED21[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */
916 …OTFDEC Region Configuration register, Address offset: 0x20 + 0x30 * (x -1) (x = 1 to 4) */
917 …OTFDEC Region Start Address register, Address offset: 0x24 + 0x30 * (x -1) (x = 1 to 4) */
918 …OTFDEC Region End Address register, Address offset: 0x28 + 0x30 * (x -1) (x = 1 to 4) */
919 …OTFDEC Region Nonce register 0, Address offset: 0x2C + 0x30 * (x -1) (x = 1 to 4) */
920 …OTFDEC Region Nonce register 1, Address offset: 0x30 + 0x30 * (x -1) (x = 1 to 4) */
921 …OTFDEC Region Key register 0, Address offset: 0x34 + 0x30 * (x -1) (x = 1 to 4) */
922 …OTFDEC Region Key register 1, Address offset: 0x38 + 0x30 * (x -1) (x = 1 to 4) */
923 …OTFDEC Region Key register 2, Address offset: 0x3C + 0x30 * (x -1) (x = 1 to 4) */
924 …OTFDEC Region Key register 3, Address offset: 0x40 + 0x30 * (x -1) (x = 1 to 4) */
930 … /*!< Reserved, Address offset: 0x004-0x00C */
932 … /*!< Reserved, Address offset: 0x014-0x2FC */
945 …CR[8]; /*!< OCTOSPIM IO Manager Port[1:8] Configuration register, Address offset: 0x04-0x20 */
966 …__IO uint32_t UCPDR; /*!< Power USB Type-C and Power Delivery register, Address offset: 0x…
975 …__IO uint32_t PUCRA; /*!< Power Port A pull-up control register, Address offset: 0x…
976 …__IO uint32_t PDCRA; /*!< Power Port A pull-down control register, Address offset: 0x…
977 …__IO uint32_t PUCRB; /*!< Power Port B pull-up control register, Address offset: 0x…
978 …__IO uint32_t PDCRB; /*!< Power Port B pull-down control register, Address offset: 0x…
979 …__IO uint32_t PUCRC; /*!< Power Port C pull-up control register, Address offset: 0x…
980 …__IO uint32_t PDCRC; /*!< Power Port C pull-down control register, Address offset: 0x…
981 …__IO uint32_t PUCRD; /*!< Power Port D pull-up control register, Address offset: 0x…
982 …__IO uint32_t PDCRD; /*!< Power Port D pull-down control register, Address offset: 0x…
983 …__IO uint32_t PUCRE; /*!< Power Port E pull-up control register, Address offset: 0x…
984 …__IO uint32_t PDCRE; /*!< Power Port E pull-down control register, Address offset: 0x…
985 …__IO uint32_t PUCRF; /*!< Power Port F pull-up control register, Address offset: 0x…
986 …__IO uint32_t PDCRF; /*!< Power Port F pull-down control register, Address offset: 0x…
987 …__IO uint32_t PUCRG; /*!< Power Port G pull-up control register, Address offset: 0x…
988 …__IO uint32_t PDCRG; /*!< Power Port G pull-down control register, Address offset: 0x…
989 …__IO uint32_t PUCRH; /*!< Power Port H pull-up control register, Address offset: 0x…
990 …__IO uint32_t PDCRH; /*!< Power Port H pull-down control register, Address offset: 0x…
991 …__IO uint32_t PUCRI; /*!< Power Port I pull-up control register, Address offset: 0x…
992 …__IO uint32_t PDCRI; /*!< Power Port I pull-down control register, Address offset: 0x…
1093 …uint32_t Reserved[253]; /*!< Reserved memory area Address offset: 0x0C -> 0x03F…
1094 …__IO uint32_t RAM[1334]; /*!< PKA RAM Address offset: 0x400 -> 0x18D…
1104 * @brief Real-Time Clock
1122 …__IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x…
1159 …_t RESERVED1[4]; /*!< Reserved, Address offset: 0x43 -- 0x50 */
1161 …_t RESERVED2[42]; /*!< Reserved, Address offset: 0x58 -- 0xFC */
1247 …__IO uint32_t CNSLCKR; /*!< SYSCFG CPU non-secure lock register, Address offset: …
1256 … RESERVED2[16];/*!< RESERVED2, Address offset: 0x30 - 0x6C */
1282 …uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C …
1289 …uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C …
1383 uint32_t Reserved44[15]; /*!< Reserved, Address offset: 844-87Ch */
1389 * @brief USB_OTG_IN_Endpoint-Specific_Register
1404 * @brief USB_OTG_OUT_Endpoint-Specific_Registers
1462 …[4]; /*!< Reserved, 0x030 - 0x03C */
1471 …[8]; /*!< Reserved, 0x060 - 0x07C */
1480 …[8]; /*!< Reserved, 0x0A0 - 0x0BC */
1500 …[128];/*!< Reserved, 0x100 + 0x004 - 0x100 + 0x200 */
1502 …[58];/*!< Reserved, 0x100 + 0x208 - 0x100 + 0x2EC */
1514 …BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR)…
1515 …__IO uint32_t PCSCNTR; /*!< PSRAM chip-select counter register, …
1523 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
1560 …__IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address of…
1573 …uint32_t RESERVED2[4]; /*!< Reserved, 0x050 - 0x05C …
1579 …uint32_t RESERVED3[3]; /*!< Reserved, 0x074 - 0x07C …
1584 …uint32_t RESERVED4[4]; /*!< Reserved, 0x090 - 0x09C …
1646 …uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C …
1648 …uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C …
1674 …XCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
1690 /* -------- End of section using anonymous unions and disabling warnings -------- */
1725 /* External memories base addresses - Not aliased */
1737 /* Flash, Peripheral and internal SRAMs base addresses - Non secure */
1738 #define FLASH_BASE_NS (0x08000000UL) /*!< FLASH (up to 2 MB) non-secure base address …
1739 #define SRAM1_BASE_NS (0x20000000UL) /*!< SRAM1 (192 KB) non-secure base address …
1740 #define SRAM2_BASE_NS (0x20030000UL) /*!< SRAM2 (64 KB) non-secure base address …
1741 #define SRAM3_BASE_NS (0x20040000UL) /*!< SRAM3 (512 KB) non-secure base address …
1742 #define SRAM4_BASE_NS (0x28000000UL) /*!< SRAM4 (16 KB) non-secure base address …
1743 #define PERIPH_BASE_NS (0x40000000UL) /*!< Peripheral non-secure base address …
1745 /* Peripheral memory map - Non secure */
1922 /* Flash, Peripheral and internal SRAMs base addresses - Secure */
1930 /* Peripheral memory map - Secure */
2114 #define FLASH_OTP_BASE (0x0BFA0000UL) /*!< FLASH OTP (one-time programmable) base address …
2115 #define FLASH_OTP_SIZE (0x200U) /*!< 512 bytes OTP (one-time programmable) …
2167 * @brief RSSLib non-secure callable function pointer structure
2537 /*!< Memory & Instance aliases and base addresses for Non-Secure/Secure peripherals */
4259 #define ADC4_PWRR_AUTOFF ADC4_PWRR_AUTOFF_Msk /*!< ADC Auto-Off m…
5025 … ADC_CALFACT_I_APB_ADDR_Msk /*!< ADC calibration factors in single-ended mode */
5059 … ADC4_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */
5211 … CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data regist…
5496 …R DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned dat…
5499 … DAC_DHR12R1_DACC1DHRB_Msk /*!<DAC channel1 12-bit Right-aligned data B */
5504 …R DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data…
5507 …RB DAC_DHR12L1_DACC1DHRB_Msk /*!<DAC channel1 12-bit Left aligned data…
5512 …R DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned dat…
5515 …RB DAC_DHR8R1_DACC1DHRB_Msk /*!<DAC channel1 8-bit Right aligned dat…
5520 …R DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned dat…
5523 … DAC_DHR12R2_DACC2DHRB_Msk /*!<DAC channel2 12-bit Right-aligned data B */
5528 …R DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data…
5531 …RB DAC_DHR12L2_DACC2DHRB_Msk /*!<DAC channel2 12-bit Left aligned data…
5536 …R DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned dat…
5539 …RB DAC_DHR8R2_DACC2DHRB_Msk /*!<DAC channel2 8-bit Right aligned dat…
5544 …R DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned dat…
5547 …R DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned dat…
5552 …R DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data…
5555 …R DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data…
5560 …R DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned dat…
5563 …R DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned dat…
6540 … DMA_MISR_MIS0_Msk /*!< Masked Interrupt State of Non-Secure Channel 0 */
6543 … DMA_MISR_MIS1_Msk /*!< Masked Interrupt State of Non-Secure Channel 1 */
6546 … DMA_MISR_MIS2_Msk /*!< Masked Interrupt State of Non-Secure Channel 2 */
6549 … DMA_MISR_MIS3_Msk /*!< Masked Interrupt State of Non-Secure Channel 3 */
6552 … DMA_MISR_MIS4_Msk /*!< Masked Interrupt State of Non-Secure Channel 4 */
6555 … DMA_MISR_MIS5_Msk /*!< Masked Interrupt State of Non-Secure Channel 5 */
6558 … DMA_MISR_MIS6_Msk /*!< Masked Interrupt State of Non-Secure Channel 6 */
6561 … DMA_MISR_MIS7_Msk /*!< Masked Interrupt State of Non-Secure Channel 7 */
6564 … DMA_MISR_MIS8_Msk /*!< Masked Interrupt State of Non-Secure Channel 8 */
6567 … DMA_MISR_MIS9_Msk /*!< Masked Interrupt State of Non-Secure Channel 9 */
6570 … DMA_MISR_MIS10_Msk /*!< Masked Interrupt State of Non-Secure Channel 10 */
6573 … DMA_MISR_MIS11_Msk /*!< Masked Interrupt State of Non-Secure Channel 11 */
6576 … DMA_MISR_MIS12_Msk /*!< Masked Interrupt State of Non-Secure Channel 12 */
6579 … DMA_MISR_MIS13_Msk /*!< Masked Interrupt State of Non-Secure Channel 13 */
6582 … DMA_MISR_MIS14_Msk /*!< Masked Interrupt State of Non-Secure Channel 14 */
6585 … DMA_MISR_MIS14_Msk /*!< Masked Interrupt State of Non-Secure Channel 15 */
6640 #define DMA_CLBAR_LBA DMA_CLBAR_LBA_Msk /*!< Linked-lis…
6654 … DMA_CFCR_ULEF_Msk /*!< Update linked-list item error flag …
6680 … DMA_CSR_ULEF_Msk /*!< Update linked-list item error flag …
6715 … DMA_CCR_ULEIE_Msk /*!< Update linked-list item error inter…
6730 #define DMA_CCR_LAP DMA_CCR_LAP_Msk /*!< Linked-lis…
6756 …k /*!< Source byte exchange within the unaligned half-word of each source w…
6779 … DMA_CTR1_DHX_Msk /*!< Destination half-word exchange …
6868 … DMA_CLLR_LA_Msk /*!< Pointer to the next linked-list data structure */
8007 #define FDCAN_CREL_SUBSTEP FDCAN_CREL_SUBSTEP_Msk /*!<Sub-step of…
8405 #define FDCAN_RXGFC_ANFE FDCAN_RXGFC_ANFE_Msk /*!<Accept Non-…
8408 #define FDCAN_RXGFC_ANFS FDCAN_RXGFC_ANFS_Msk /*!<Accept Non-…
8575 #define FLASH_BLOCKBASED_NB_REG (4U) /*!< 4 Block-based registers fo…
8612 #define FLASH_ACR_LPM FLASH_ACR_LPM_Msk /*!< Low-Power …
8615 …1 FLASH_ACR_PDREQ1_Msk /*!< Bank 1 power-down mode request */
8618 …2 FLASH_ACR_PDREQ2_Msk /*!< Bank 2 power-down mode request */
8621 …PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash power-down mode during slee…
8626 #define FLASH_NSSR_EOP FLASH_NSSR_EOP_Msk /*!< Non-secure…
8629 #define FLASH_NSSR_OPERR FLASH_NSSR_OPERR_Msk /*!< Non-secure…
8632 #define FLASH_NSSR_PROGERR FLASH_NSSR_PROGERR_Msk /*!< Non-secure…
8635 #define FLASH_NSSR_WRPERR FLASH_NSSR_WRPERR_Msk /*!< Non-secure…
8638 #define FLASH_NSSR_PGAERR FLASH_NSSR_PGAERR_Msk /*!< Non-secure…
8641 #define FLASH_NSSR_SIZERR FLASH_NSSR_SIZERR_Msk /*!< Non-secure…
8644 #define FLASH_NSSR_PGSERR FLASH_NSSR_PGSERR_Msk /*!< Non-secure…
8650 #define FLASH_NSSR_BSY FLASH_NSSR_BSY_Msk /*!< Non-secure…
8653 #define FLASH_NSSR_WDW FLASH_NSSR_WDW_Msk /*!< Non-secure…
8662 …_PD1 FLASH_NSSR_PD1_Msk /*!< Bank 1 in power-down mode */
8665 …_PD2 FLASH_NSSR_PD2_Msk /*!< Bank 2 in power-down mode */
8699 #define FLASH_NSCR_PG FLASH_NSCR_PG_Msk /*!< Non-secure…
8702 #define FLASH_NSCR_PER FLASH_NSCR_PER_Msk /*!< Non-secure…
8705 #define FLASH_NSCR_MER1 FLASH_NSCR_MER1_Msk /*!< Non-secure…
8708 #define FLASH_NSCR_PNB FLASH_NSCR_PNB_Msk /*!< Non-secure…
8711 #define FLASH_NSCR_BKER FLASH_NSCR_BKER_Msk /*!< Non-secure…
8714 #define FLASH_NSCR_BWR FLASH_NSCR_BWR_Msk /*!< Non-secure…
8717 #define FLASH_NSCR_MER2 FLASH_NSCR_MER2_Msk /*!< Non-secure…
8720 #define FLASH_NSCR_STRT FLASH_NSCR_STRT_Msk /*!< Non-secure…
8726 #define FLASH_NSCR_EOPIE FLASH_NSCR_EOPIE_Msk /*!< Non-secure…
8729 #define FLASH_NSCR_ERRIE FLASH_NSCR_ERRIE_Msk /*!< Non-secure…
8738 #define FLASH_NSCR_LOCK FLASH_NSCR_LOCK_Msk /*!< Non-secure…
8781 #define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk /*!< ECC fail a…
8784 #define FLASH_ECCR_BK_ECC FLASH_ECCR_BK_ECC_Msk /*!< ECC fail b…
8787 …ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk /*!< System Flash ECC fail */
8854 #define FLASH_OPTR_DUALBANK FLASH_OPTR_DUALBANK_Msk /*!< Dual-bank …
8875 #define FLASH_OPTR_PA15_PUPEN FLASH_OPTR_PA15_PUPEN_Msk /*!< PA15 pull-…
8889 #define FLASH_NSBOOTADD0R_NSBOOTADD0 FLASH_NSBOOTADD0R_NSBOOTADD0_Msk /*!< Non-secure…
8894 #define FLASH_NSBOOTADD1R_NSBOOTADD1 FLASH_NSBOOTADD1R_NSBOOTADD1_Msk /*!< Non-secure…
8994 … FLASH_PRIVCFGR_NSPRIV_Msk /*!< Privilege protection for non-secure registers */
9007 … FMAC_X1BUFCFG_X1_BUF_SIZE_Msk /*!< Allocated size of X1 buffer in 16-bit words */
9018 …UF_SIZE FMAC_X2BUFCFG_X2_BUF_SIZE_Msk /*!< Size of X2 buffer in 16-bit words */
9026 …F_SIZE FMAC_YBUFCFG_Y_BUF_SIZE_Msk /*!< Size of Y buffer in 16-bit words */
9193 … FMC_BTRx_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) …
9200 … FMC_BTRx_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
9251 … FMC_BWTRx_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) …
9258 … FMC_BWTRx_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
11069 #define MDF_DFLTRSFR_HPFBYP MDF_DFLTRSFR_HPFBYP_Msk /*!<High-pass f…
11072 …C MDF_DFLTRSFR_HPFC_Msk /*!<High-pass filter cut-off frequency…
11341 … TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selectio…
11346 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload…
11622 …1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
11643 …2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
11658 /*----------------------------------------------------------------------------*/
11692 …3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
11713 …4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
11728 /*----------------------------------------------------------------------------*/
11757 …5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */
11773 …6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 6 Fast enable */
11866 …ARR TIM_ARR_ARR_Msk /*!<Actual auto-reload Value */
11915 … TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
11931 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State S…
11934 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State S…
11961 …BKDSRM TIM_BDTR_BKDSRM_Msk /*!<Break disarming/re-arming */
11964 …K2DSRM TIM_BDTR_BK2DSRM_Msk /*!<Break2 disarming/re-arming */
12191 … LPTIM_ISR_CC1OF_Msk /*!< Capture/Compare 1 over-capture flag */
12194 … LPTIM_ISR_CC2OF_Msk /*!< Capture/Compare 2 over-capture flag */
12235 … LPTIM_ICR_CC1OCF_Msk /*!< Capture/Compare 1 over-capture clear flag */
12238 … LPTIM_ICR_CC2OCF_Msk /*!< Capture/Compare 2 over-capture clear flag */
12278 … LPTIM_DIER_CC1OIE_Msk /*!< Capture/Compare 1 over-capture interrupt ena…
12281 … LPTIM_DIER_CC2OIE_Msk /*!< Capture/Compare 2 over-capture interrupt ena…
12765 …AIL_Msk /*!<Boot Acknowledgment received (BootAck check fail) …
12847 …LIE SDMMC_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable …
12850 …FAILIE SDMMC_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable …
12901 … SDMMC_MASK_ACKFAILIE_Msk /*!<Acknowledgment Fail Interrupt Enable */
13960 …GR_REG_EN OTFDEC_REG_CONFIGR_REG_EN_Msk /*!< Region on-the-fly decryption enab…
13974 …C_REG_CONFIGR_KEYCRC OTFDEC_REG_CONFIGR_KEYCRC_Msk /*!< Region key 8-bit CRC */
14025 #define OTFDEC_ISR_XONEIF OTFDEC_ISR_XONEIF_Msk /*!< Execute-on…
14036 #define OTFDEC_ICR_XONEIF OTFDEC_ICR_XONEIF_Msk /*!< Execute-on…
14047 #define OTFDEC_IER_XONEIE OTFDEC_IER_XONEIE_Msk /*!< Execute-on…
14060 … PWR_CR1_LPMS_Msk /*!< LPMS[2:0] Low-power mode selection …
14072 #define PWR_CR1_ULPMEN PWR_CR1_ULPMEN_Msk /*!< BOR ultra-…
14075 … PWR_CR1_SRAM1PD_Msk /*!< SRAM1 power-down in Run mode …
14078 … PWR_CR1_SRAM2PD_Msk /*!< SRAM2 power-down in Run mode …
14081 … PWR_CR1_SRAM3PD_Msk /*!< SRAM3 power-down in Run mode …
14084 … PWR_CR1_SRAM4PD_Msk /*!< SRAM4 power-down in Run mode …
14089 … PWR_CR2_SRAM1PDS1_Msk /*!< SRAM1 page 1 (64 KB) power-down in Stop modes (S…
14092 … PWR_CR2_SRAM1PDS2_Msk /*!< SRAM1 page 2 (64 KB) power-down in Stop modes (S…
14095 … PWR_CR2_SRAM1PDS3_Msk /*!< SRAM1 page 3 (64 KB) power-down in Stop modes (S…
14098 … PWR_CR2_SRAM2PDS1_Msk /*!< SRAM2 page 1 (8 KB) power-down in Stop modes (S…
14101 … PWR_CR2_SRAM2PDS2_Msk /*!< SRAM2 page 2 (56 KB) power-down in Stop modes (S…
14104 … PWR_CR2_SRAM4PDS_Msk /*!< SRAM4 power-down in Stop modes (S…
14107 … PWR_CR2_ICRAMPDS_Msk /*!< ICACHE SRAM power-down in Stop modes (S…
14110 … PWR_CR2_DC1RAMPDS_Msk /*!< DCACHE1 SRAM power-down in Stop modes (S…
14113 … PWR_CR2_DMA2DRAMPDS_Msk /*!< DMA2D SRAM power-down in Stop modes (S…
14116 …R2_PRAMPDS_Msk /*!< FDCAN and USB peripherals SRAM power-down in Stop modes (S…
14119 … PWR_CR2_PKARAMPDS_Msk /*!< PKA32 SRAM power-down in Stop modes (S…
14122 #define PWR_CR2_SRAM4FWU PWR_CR2_SRAM4FWU_Msk /*!< SRAM4 fast…
14125 … PWR_CR2_FLASHFWU_Msk /*!< Flash memory fast wakeup from Stop mo…
14128 … PWR_CR2_SRAM3PDS1_Msk /*!< SRAM3 page 1 (64 KB) power-down in Stop modes (S…
14131 … PWR_CR2_SRAM3PDS2_Msk /*!< SRAM3 page 2 (64 KB) power-down in Stop modes (S…
14134 … PWR_CR2_SRAM3PDS3_Msk /*!< SRAM3 page 3 (64 KB) power-down in Stop modes (S…
14137 … PWR_CR2_SRAM3PDS4_Msk /*!< SRAM3 page 4 (64 KB) power-down in Stop modes (S…
14140 … PWR_CR2_SRAM3PDS5_Msk /*!< SRAM3 page 5 (64 KB) power-down in Stop modes (S…
14143 … PWR_CR2_SRAM3PDS6_Msk /*!< SRAM3 page 6 (64 KB) power-down in Stop modes (S…
14146 … PWR_CR2_SRAM3PDS7_Msk /*!< SRAM3 page 7 (64 KB) power-down in Stop modes (S…
14149 … PWR_CR2_SRAM3PDS8_Msk /*!< SRAM3 page 8 (64 KB) power-down in Stop modes (S…
14160 #define PWR_CR3_FSTEN PWR_CR3_FSTEN_Msk /*!< Fast soft …
14328 #define PWR_UCPDR_UCPD_DBDIS PWR_UCPDR_UCPD_DBDIS_Msk /*!< USB Type-C…
14331 #define PWR_UCPDR_UCPD_STDBY PWR_UCPDR_UCPD_STDBY_Msk /*!< USB Type-C…
14360 #define PWR_SECCFGR_LPMSEC PWR_SECCFGR_LPMSEC_Msk /*!< Low-power …
14369 …PCSEC PWR_SECCFGR_APCSEC_Msk /*!< Pull-up/pull-down secure prote…
14377 #define PWR_PRIVCFGR_NSPRIV PWR_PRIVCFGR_NSPRIV_Msk /*!< RCC non-se…
14490 … PWR_APCR_APC_Msk /*!< Apply pull-up and pull-down configurat…
14495 …RA_PU0 PWR_PUCRA_PU0_Msk /*!< Apply pull-up for PA0 */
14498 …RA_PU1 PWR_PUCRA_PU1_Msk /*!< Apply pull-up for PA1 */
14501 …RA_PU2 PWR_PUCRA_PU2_Msk /*!< Apply pull-up for PA2 */
14504 …RA_PU3 PWR_PUCRA_PU3_Msk /*!< Apply pull-up for PA3 */
14507 …RA_PU4 PWR_PUCRA_PU4_Msk /*!< Apply pull-up for PA4 */
14510 …RA_PU5 PWR_PUCRA_PU5_Msk /*!< Apply pull-up for PA5 */
14513 …RA_PU6 PWR_PUCRA_PU6_Msk /*!< Apply pull-up for PA6 */
14516 …RA_PU7 PWR_PUCRA_PU7_Msk /*!< Apply pull-up for PA7 */
14519 …RA_PU8 PWR_PUCRA_PU8_Msk /*!< Apply pull-up for PA8 */
14522 …RA_PU9 PWR_PUCRA_PU9_Msk /*!< Apply pull-up for PA9 */
14525 …RA_PU10 PWR_PUCRA_PU10_Msk /*!< Apply pull-up for PA10 */
14528 …RA_PU11 PWR_PUCRA_PU11_Msk /*!< Apply pull-up for PA11 */
14531 …RA_PU12 PWR_PUCRA_PU12_Msk /*!< Apply pull-up for PA12 */
14534 …RA_PU13 PWR_PUCRA_PU13_Msk /*!< Apply pull-up for PA13 */
14537 …RA_PU15 PWR_PUCRA_PU15_Msk /*!< Apply pull-up for PA15 */
14542 …_PD0 PWR_PDCRA_PD0_Msk /*!< Apply pull-down for PA0 */
14545 …_PD1 PWR_PDCRA_PD1_Msk /*!< Apply pull-down for PA1 */
14548 …_PD2 PWR_PDCRA_PD2_Msk /*!< Apply pull-down for PA2 */
14551 …_PD3 PWR_PDCRA_PD3_Msk /*!< Apply pull-down for PA3 */
14554 …_PD4 PWR_PDCRA_PD4_Msk /*!< Apply pull-down for PA4 */
14557 …_PD5 PWR_PDCRA_PD5_Msk /*!< Apply pull-down for PA5 */
14560 …_PD6 PWR_PDCRA_PD6_Msk /*!< Apply pull-down for PA6 */
14563 …_PD7 PWR_PDCRA_PD7_Msk /*!< Apply pull-down for PA7 */
14566 …_PD8 PWR_PDCRA_PD8_Msk /*!< Apply pull-down for PA8 */
14569 …_PD9 PWR_PDCRA_PD9_Msk /*!< Apply pull-down for PA9 */
14572 …_PD10 PWR_PDCRA_PD10_Msk /*!< Apply pull-down for PA10 */
14575 …_PD11 PWR_PDCRA_PD11_Msk /*!< Apply pull-down for PA11 */
14578 …_PD12 PWR_PDCRA_PD12_Msk /*!< Apply pull-down for PA12 */
14581 …_PD14 PWR_PDCRA_PD14_Msk /*!< Apply pull-down for PA14 */
14586 …RB_PU0 PWR_PUCRB_PU0_Msk /*!< Apply pull-up for PB0 */
14589 …RB_PU1 PWR_PUCRB_PU1_Msk /*!< Apply pull-up for PB1 */
14592 …RB_PU2 PWR_PUCRB_PU2_Msk /*!< Apply pull-up for PB2 */
14595 …RB_PU3 PWR_PUCRB_PU3_Msk /*!< Apply pull-up for PB3 */
14598 …RB_PU4 PWR_PUCRB_PU4_Msk /*!< Apply pull-up for PB4 */
14601 …RB_PU5 PWR_PUCRB_PU5_Msk /*!< Apply pull-up for PB5 */
14604 …RB_PU6 PWR_PUCRB_PU6_Msk /*!< Apply pull-up for PB6 */
14607 …RB_PU7 PWR_PUCRB_PU7_Msk /*!< Apply pull-up for PB7 */
14610 …RB_PU8 PWR_PUCRB_PU8_Msk /*!< Apply pull-up for PB8 */
14613 …RB_PU9 PWR_PUCRB_PU9_Msk /*!< Apply pull-up for PB9 */
14616 …RB_PU10 PWR_PUCRB_PU10_Msk /*!< Apply pull-up for PB10 */
14619 …RB_PU11 PWR_PUCRB_PU11_Msk /*!< Apply pull-up for PB11 */
14622 …RB_PU12 PWR_PUCRB_PU12_Msk /*!< Apply pull-up for PB12 */
14625 …RB_PU13 PWR_PUCRB_PU13_Msk /*!< Apply pull-up for PB13 */
14628 …RB_PU14 PWR_PUCRB_PU14_Msk /*!< Apply pull-up for PB14 */
14631 …RB_PU15 PWR_PUCRB_PU15_Msk /*!< Apply pull-up for PB15 */
14636 …_PD0 PWR_PDCRB_PD0_Msk /*!< Apply pull-down for PB0 */
14639 …_PD1 PWR_PDCRB_PD1_Msk /*!< Apply pull-down for PB1 */
14642 …_PD2 PWR_PDCRB_PD2_Msk /*!< Apply pull-down for PB2 */
14645 …_PD3 PWR_PDCRB_PD3_Msk /*!< Apply pull-down for PB3 */
14648 …_PD5 PWR_PDCRB_PD5_Msk /*!< Apply pull-down for PB5 */
14651 …_PD6 PWR_PDCRB_PD6_Msk /*!< Apply pull-down for PB6 */
14654 …_PD7 PWR_PDCRB_PD7_Msk /*!< Apply pull-down for PB7 */
14657 …_PD8 PWR_PDCRB_PD8_Msk /*!< Apply pull-down for PB8 */
14660 …_PD9 PWR_PDCRB_PD9_Msk /*!< Apply pull-down for PB9 */
14663 …_PD10 PWR_PDCRB_PD10_Msk /*!< Apply pull-down for PB10 */
14666 …_PD11 PWR_PDCRB_PD11_Msk /*!< Apply pull-down for PB11 */
14669 …_PD12 PWR_PDCRB_PD12_Msk /*!< Apply pull-down for PB12 */
14672 …_PD13 PWR_PDCRB_PD13_Msk /*!< Apply pull-down for PB13 */
14675 …_PD14 PWR_PDCRB_PD14_Msk /*!< Apply pull-down for PB14 */
14678 …_PD15 PWR_PDCRB_PD15_Msk /*!< Apply pull-down for PB15 */
14683 …RC_PU0 PWR_PUCRC_PU0_Msk /*!< Apply pull-up for PC0 */
14686 …RC_PU1 PWR_PUCRC_PU1_Msk /*!< Apply pull-up for PC1 */
14689 …RC_PU2 PWR_PUCRC_PU2_Msk /*!< Apply pull-up for PC2 */
14692 …RC_PU3 PWR_PUCRC_PU3_Msk /*!< Apply pull-up for PC3 */
14695 …RC_PU4 PWR_PUCRC_PU4_Msk /*!< Apply pull-up for PC4 */
14698 …RC_PU5 PWR_PUCRC_PU5_Msk /*!< Apply pull-up for PC5 */
14701 …RC_PU6 PWR_PUCRC_PU6_Msk /*!< Apply pull-up for PC6 */
14704 …RC_PU7 PWR_PUCRC_PU7_Msk /*!< Apply pull-up for PC7 */
14707 …RC_PU8 PWR_PUCRC_PU8_Msk /*!< Apply pull-up for PC8 */
14710 …RC_PU9 PWR_PUCRC_PU9_Msk /*!< Apply pull-up for PC9 */
14713 …RC_PU10 PWR_PUCRC_PU10_Msk /*!< Apply pull-up for PC10 */
14716 …RC_PU11 PWR_PUCRC_PU11_Msk /*!< Apply pull-up for PC11 */
14719 …RC_PU12 PWR_PUCRC_PU12_Msk /*!< Apply pull-up for PC12 */
14722 …RC_PU13 PWR_PUCRC_PU13_Msk /*!< Apply pull-up for PC13 */
14725 …RC_PU14 PWR_PUCRC_PU14_Msk /*!< Apply pull-up for PC14 */
14728 …RC_PU15 PWR_PUCRC_PU15_Msk /*!< Apply pull-up for PC15 */
14733 …_PD0 PWR_PDCRC_PD0_Msk /*!< Apply pull-down for PC0 */
14736 …_PD1 PWR_PDCRC_PD1_Msk /*!< Apply pull-down for PC1 */
14739 …_PD2 PWR_PDCRC_PD2_Msk /*!< Apply pull-down for PC2 */
14742 …_PD3 PWR_PDCRC_PD3_Msk /*!< Apply pull-down for PC3 */
14745 …_PD4 PWR_PDCRC_PD4_Msk /*!< Apply pull-down for PC4 */
14748 …_PD5 PWR_PDCRC_PD5_Msk /*!< Apply pull-down for PC5 */
14751 …_PD6 PWR_PDCRC_PD6_Msk /*!< Apply pull-down for PC6 */
14754 …_PD7 PWR_PDCRC_PD7_Msk /*!< Apply pull-down for PC7 */
14757 …_PD8 PWR_PDCRC_PD8_Msk /*!< Apply pull-down for PC8 */
14760 …_PD9 PWR_PDCRC_PD9_Msk /*!< Apply pull-down for PC9 */
14763 …_PD10 PWR_PDCRC_PD10_Msk /*!< Apply pull-down for PC10 */
14766 …_PD11 PWR_PDCRC_PD11_Msk /*!< Apply pull-down for PC11 */
14769 …_PD12 PWR_PDCRC_PD12_Msk /*!< Apply pull-down for PC12 */
14772 …_PD13 PWR_PDCRC_PD13_Msk /*!< Apply pull-down for PC13 */
14775 …_PD14 PWR_PDCRC_PD14_Msk /*!< Apply pull-down for PC14 */
14778 …_PD15 PWR_PDCRC_PD15_Msk /*!< Apply pull-down for PC15 */
14783 …RD_PU0 PWR_PUCRD_PU0_Msk /*!< Apply pull-up for PD0 */
14786 …RD_PU1 PWR_PUCRD_PU1_Msk /*!< Apply pull-up for PD1 */
14789 …RD_PU2 PWR_PUCRD_PU2_Msk /*!< Apply pull-up for PD2 */
14792 …RD_PU3 PWR_PUCRD_PU3_Msk /*!< Apply pull-up for PD3 */
14795 …RD_PU4 PWR_PUCRD_PU4_Msk /*!< Apply pull-up for PD4 */
14798 …RD_PU5 PWR_PUCRD_PU5_Msk /*!< Apply pull-up for PD5 */
14801 …RD_PU6 PWR_PUCRD_PU6_Msk /*!< Apply pull-up for PD6 */
14804 …RD_PU7 PWR_PUCRD_PU7_Msk /*!< Apply pull-up for PD7 */
14807 …RD_PU8 PWR_PUCRD_PU8_Msk /*!< Apply pull-up for PD8 */
14810 …RD_PU9 PWR_PUCRD_PU9_Msk /*!< Apply pull-up for PD9 */
14813 …RD_PU10 PWR_PUCRD_PU10_Msk /*!< Apply pull-up for PD10 */
14816 …RD_PU11 PWR_PUCRD_PU11_Msk /*!< Apply pull-up for PD11 */
14819 …RD_PU12 PWR_PUCRD_PU12_Msk /*!< Apply pull-up for PD12 */
14822 …RD_PU13 PWR_PUCRD_PU13_Msk /*!< Apply pull-up for PD13 */
14825 …RD_PU14 PWR_PUCRD_PU14_Msk /*!< Apply pull-up for PD14 */
14828 …RD_PU15 PWR_PUCRD_PU15_Msk /*!< Apply pull-up for PD15 */
14833 …_PD0 PWR_PDCRD_PD0_Msk /*!< Apply pull-down for PD0 */
14836 …_PD1 PWR_PDCRD_PD1_Msk /*!< Apply pull-down for PD1 */
14839 …_PD2 PWR_PDCRD_PD2_Msk /*!< Apply pull-down for PD2 */
14842 …_PD3 PWR_PDCRD_PD3_Msk /*!< Apply pull-down for PD3 */
14845 …_PD4 PWR_PDCRD_PD4_Msk /*!< Apply pull-down for PD4 */
14848 …_PD5 PWR_PDCRD_PD5_Msk /*!< Apply pull-down for PD5 */
14851 …_PD6 PWR_PDCRD_PD6_Msk /*!< Apply pull-down for PD6 */
14854 …_PD7 PWR_PDCRD_PD7_Msk /*!< Apply pull-down for PD7 */
14857 …_PD8 PWR_PDCRD_PD8_Msk /*!< Apply pull-down for PD8 */
14860 …_PD9 PWR_PDCRD_PD9_Msk /*!< Apply pull-down for PD9 */
14863 …_PD10 PWR_PDCRD_PD10_Msk /*!< Apply pull-down for PD10 */
14866 …_PD11 PWR_PDCRD_PD11_Msk /*!< Apply pull-down for PD11 */
14869 …_PD12 PWR_PDCRD_PD12_Msk /*!< Apply pull-down for PD12 */
14872 …_PD13 PWR_PDCRD_PD13_Msk /*!< Apply pull-down for PD13 */
14875 …_PD14 PWR_PDCRD_PD14_Msk /*!< Apply pull-down for PD14 */
14878 …_PD15 PWR_PDCRD_PD15_Msk /*!< Apply pull-down for PD15 */
14883 …RE_PU0 PWR_PUCRE_PU0_Msk /*!< Apply pull-up for PE0 */
14886 …RE_PU1 PWR_PUCRE_PU1_Msk /*!< Apply pull-up for PE1 */
14889 …RE_PU2 PWR_PUCRE_PU2_Msk /*!< Apply pull-up for PE2 */
14892 …RE_PU3 PWR_PUCRE_PU3_Msk /*!< Apply pull-up for PE3 */
14895 …RE_PU4 PWR_PUCRE_PU4_Msk /*!< Apply pull-up for PE4 */
14898 …RE_PU5 PWR_PUCRE_PU5_Msk /*!< Apply pull-up for PE5 */
14901 …RE_PU6 PWR_PUCRE_PU6_Msk /*!< Apply pull-up for PE6 */
14904 …RE_PU7 PWR_PUCRE_PU7_Msk /*!< Apply pull-up for PE7 */
14907 …RE_PU8 PWR_PUCRE_PU8_Msk /*!< Apply pull-up for PE8 */
14910 …RE_PU9 PWR_PUCRE_PU9_Msk /*!< Apply pull-up for PE9 */
14913 …RE_PU10 PWR_PUCRE_PU10_Msk /*!< Apply pull-up for PE10 */
14916 …RE_PU11 PWR_PUCRE_PU11_Msk /*!< Apply pull-up for PE11 */
14919 …RE_PU12 PWR_PUCRE_PU12_Msk /*!< Apply pull-up for PE12 */
14922 …RE_PU13 PWR_PUCRE_PU13_Msk /*!< Apply pull-up for PE13 */
14925 …RE_PU14 PWR_PUCRE_PU14_Msk /*!< Apply pull-up for PE14 */
14928 …RE_PU15 PWR_PUCRE_PU15_Msk /*!< Apply pull-up for PE15 */
14933 …_PD0 PWR_PDCRE_PD0_Msk /*!< Apply pull-down for PE0 */
14936 …_PD1 PWR_PDCRE_PD1_Msk /*!< Apply pull-down for PE1 */
14939 …_PD2 PWR_PDCRE_PD2_Msk /*!< Apply pull-down for PE2 */
14942 …_PD3 PWR_PDCRE_PD3_Msk /*!< Apply pull-down for PE3 */
14945 …_PD4 PWR_PDCRE_PD4_Msk /*!< Apply pull-down for PE4 */
14948 …_PD5 PWR_PDCRE_PD5_Msk /*!< Apply pull-down for PE5 */
14951 …_PD6 PWR_PDCRE_PD6_Msk /*!< Apply pull-down for PE6 */
14954 …_PD7 PWR_PDCRE_PD7_Msk /*!< Apply pull-down for PE7 */
14957 …_PD8 PWR_PDCRE_PD8_Msk /*!< Apply pull-down for PE8 */
14960 …_PD9 PWR_PDCRE_PD9_Msk /*!< Apply pull-down for PE9 */
14963 …_PD10 PWR_PDCRE_PD10_Msk /*!< Apply pull-down for PE10 */
14966 …_PD11 PWR_PDCRE_PD11_Msk /*!< Apply pull-down for PE11 */
14969 …_PD12 PWR_PDCRE_PD12_Msk /*!< Apply pull-down for PE12 */
14972 …_PD13 PWR_PDCRE_PD13_Msk /*!< Apply pull-down for PE13 */
14975 …_PD14 PWR_PDCRE_PD14_Msk /*!< Apply pull-down for PE14 */
14978 …_PD15 PWR_PDCRE_PD15_Msk /*!< Apply pull-down for PE15 */
14983 …RF_PU0 PWR_PUCRF_PU0_Msk /*!< Apply pull-up for PF0 */
14986 …RF_PU1 PWR_PUCRF_PU1_Msk /*!< Apply pull-up for PF1 */
14989 …RF_PU2 PWR_PUCRF_PU2_Msk /*!< Apply pull-up for PF2 */
14992 …RF_PU3 PWR_PUCRF_PU3_Msk /*!< Apply pull-up for PF3 */
14995 …RF_PU4 PWR_PUCRF_PU4_Msk /*!< Apply pull-up for PF4 */
14998 …RF_PU5 PWR_PUCRF_PU5_Msk /*!< Apply pull-up for PF5 */
15001 …RF_PU6 PWR_PUCRF_PU6_Msk /*!< Apply pull-up for PF6 */
15004 …RF_PU7 PWR_PUCRF_PU7_Msk /*!< Apply pull-up for PF7 */
15007 …RF_PU8 PWR_PUCRF_PU8_Msk /*!< Apply pull-up for PF8 */
15010 …RF_PU9 PWR_PUCRF_PU9_Msk /*!< Apply pull-up for PF9 */
15013 …RF_PU10 PWR_PUCRF_PU10_Msk /*!< Apply pull-up for PF10 */
15016 …RF_PU11 PWR_PUCRF_PU11_Msk /*!< Apply pull-up for PF11 */
15019 …RF_PU12 PWR_PUCRF_PU12_Msk /*!< Apply pull-up for PF12 */
15022 …RF_PU13 PWR_PUCRF_PU13_Msk /*!< Apply pull-up for PF13 */
15025 …RF_PU14 PWR_PUCRF_PU14_Msk /*!< Apply pull-up for PF14 */
15028 …RF_PU15 PWR_PUCRF_PU15_Msk /*!< Apply pull-up for PF15 */
15033 …_PD0 PWR_PDCRF_PD0_Msk /*!< Apply pull-down for PF0 */
15036 …_PD1 PWR_PDCRF_PD1_Msk /*!< Apply pull-down for PF1 */
15039 …_PD2 PWR_PDCRF_PD2_Msk /*!< Apply pull-down for PF2 */
15042 …_PD3 PWR_PDCRF_PD3_Msk /*!< Apply pull-down for PF3 */
15045 …_PD4 PWR_PDCRF_PD4_Msk /*!< Apply pull-down for PF4 */
15048 …_PD5 PWR_PDCRF_PD5_Msk /*!< Apply pull-down for PF5 */
15051 …_PD6 PWR_PDCRF_PD6_Msk /*!< Apply pull-down for PF6 */
15054 …_PD7 PWR_PDCRF_PD7_Msk /*!< Apply pull-down for PF7 */
15057 …_PD8 PWR_PDCRF_PD8_Msk /*!< Apply pull-down for PF8 */
15060 …_PD9 PWR_PDCRF_PD9_Msk /*!< Apply pull-down for PF9 */
15063 …_PD10 PWR_PDCRF_PD10_Msk /*!< Apply pull-down for PF10 */
15066 …_PD11 PWR_PDCRF_PD11_Msk /*!< Apply pull-down for PF11 */
15069 …_PD12 PWR_PDCRF_PD12_Msk /*!< Apply pull-down for PF12 */
15072 …_PD13 PWR_PDCRF_PD13_Msk /*!< Apply pull-down for PF13 */
15075 …_PD14 PWR_PDCRF_PD14_Msk /*!< Apply pull-down for PF14 */
15078 …_PD15 PWR_PDCRF_PD15_Msk /*!< Apply pull-down for PF15 */
15083 …RG_PU0 PWR_PUCRG_PU0_Msk /*!< Apply pull-up for PG0 */
15086 …RG_PU1 PWR_PUCRG_PU1_Msk /*!< Apply pull-up for PG1 */
15089 …RG_PU2 PWR_PUCRG_PU2_Msk /*!< Apply pull-up for PG2 */
15092 …RG_PU3 PWR_PUCRG_PU3_Msk /*!< Apply pull-up for PG3 */
15095 …RG_PU4 PWR_PUCRG_PU4_Msk /*!< Apply pull-up for PG4 */
15098 …RG_PU5 PWR_PUCRG_PU5_Msk /*!< Apply pull-up for PG5 */
15101 …RG_PU6 PWR_PUCRG_PU6_Msk /*!< Apply pull-up for PG6 */
15104 …RG_PU7 PWR_PUCRG_PU7_Msk /*!< Apply pull-up for PG7 */
15107 …RG_PU8 PWR_PUCRG_PU8_Msk /*!< Apply pull-up for PG8 */
15110 …RG_PU9 PWR_PUCRG_PU9_Msk /*!< Apply pull-up for PG9 */
15113 …RG_PU10 PWR_PUCRG_PU10_Msk /*!< Apply pull-up for PG10 */
15116 …RG_PU11 PWR_PUCRG_PU11_Msk /*!< Apply pull-up for PG11 */
15119 …RG_PU12 PWR_PUCRG_PU12_Msk /*!< Apply pull-up for PG12 */
15122 …RG_PU13 PWR_PUCRG_PU13_Msk /*!< Apply pull-up for PG13 */
15125 …RG_PU14 PWR_PUCRG_PU14_Msk /*!< Apply pull-up for PG14 */
15128 …RG_PU15 PWR_PUCRG_PU15_Msk /*!< Apply pull-up for PG15 */
15133 …_PD0 PWR_PDCRG_PD0_Msk /*!< Apply pull-down for PG0 */
15136 …_PD1 PWR_PDCRG_PD1_Msk /*!< Apply pull-down for PG1 */
15139 …_PD2 PWR_PDCRG_PD2_Msk /*!< Apply pull-down for PG2 */
15142 …_PD3 PWR_PDCRG_PD3_Msk /*!< Apply pull-down for PG3 */
15145 …_PD4 PWR_PDCRG_PD4_Msk /*!< Apply pull-down for PG4 */
15148 …_PD5 PWR_PDCRG_PD5_Msk /*!< Apply pull-down for PG5 */
15151 …_PD6 PWR_PDCRG_PD6_Msk /*!< Apply pull-down for PG6 */
15154 …_PD7 PWR_PDCRG_PD7_Msk /*!< Apply pull-down for PG7 */
15157 …_PD8 PWR_PDCRG_PD8_Msk /*!< Apply pull-down for PG8 */
15160 …_PD9 PWR_PDCRG_PD9_Msk /*!< Apply pull-down for PG9 */
15163 …_PD10 PWR_PDCRG_PD10_Msk /*!< Apply pull-down for PG10 */
15166 …_PD11 PWR_PDCRG_PD11_Msk /*!< Apply pull-down for PG11 */
15169 …_PD12 PWR_PDCRG_PD12_Msk /*!< Apply pull-down for PG12 */
15172 …_PD13 PWR_PDCRG_PD13_Msk /*!< Apply pull-down for PG13 */
15175 …_PD14 PWR_PDCRG_PD14_Msk /*!< Apply pull-down for PG14 */
15178 …_PD15 PWR_PDCRG_PD15_Msk /*!< Apply pull-down for PG15 */
15183 …RH_PU0 PWR_PUCRH_PU0_Msk /*!< Apply pull-up for PH0 */
15186 …RH_PU1 PWR_PUCRH_PU1_Msk /*!< Apply pull-up for PH1 */
15189 …RH_PU2 PWR_PUCRH_PU2_Msk /*!< Apply pull-up for PH2 */
15192 …RH_PU3 PWR_PUCRH_PU3_Msk /*!< Apply pull-up for PH3 */
15195 …RH_PU4 PWR_PUCRH_PU4_Msk /*!< Apply pull-up for PH4 */
15198 …RH_PU5 PWR_PUCRH_PU5_Msk /*!< Apply pull-up for PH5 */
15201 …RH_PU6 PWR_PUCRH_PU6_Msk /*!< Apply pull-up for PH6 */
15204 …RH_PU7 PWR_PUCRH_PU7_Msk /*!< Apply pull-up for PH7 */
15207 …RH_PU8 PWR_PUCRH_PU8_Msk /*!< Apply pull-up for PH8 */
15210 …RH_PU9 PWR_PUCRH_PU9_Msk /*!< Apply pull-up for PH9 */
15213 …RH_PU10 PWR_PUCRH_PU10_Msk /*!< Apply pull-up for PH10 */
15216 …RH_PU11 PWR_PUCRH_PU11_Msk /*!< Apply pull-up for PH11 */
15219 …RH_PU12 PWR_PUCRH_PU12_Msk /*!< Apply pull-up for PH12 */
15222 …RH_PU13 PWR_PUCRH_PU13_Msk /*!< Apply pull-up for PH13 */
15225 …RH_PU14 PWR_PUCRH_PU14_Msk /*!< Apply pull-up for PH14 */
15228 …RH_PU15 PWR_PUCRH_PU15_Msk /*!< Apply pull-up for PH15 */
15233 …_PD0 PWR_PDCRH_PD0_Msk /*!< Apply pull-down for PH0 */
15236 …_PD1 PWR_PDCRH_PD1_Msk /*!< Apply pull-down for PH1 */
15239 …_PD2 PWR_PDCRH_PD2_Msk /*!< Apply pull-down for PH2 */
15242 …_PD3 PWR_PDCRH_PD3_Msk /*!< Apply pull-down for PH3 */
15245 …_PD4 PWR_PDCRH_PD4_Msk /*!< Apply pull-down for PH4 */
15248 …_PD5 PWR_PDCRH_PD5_Msk /*!< Apply pull-down for PH5 */
15251 …_PD6 PWR_PDCRH_PD6_Msk /*!< Apply pull-down for PH6 */
15254 …_PD7 PWR_PDCRH_PD7_Msk /*!< Apply pull-down for PH7 */
15257 …_PD8 PWR_PDCRH_PD8_Msk /*!< Apply pull-down for PH8 */
15260 …_PD9 PWR_PDCRH_PD9_Msk /*!< Apply pull-down for PH9 */
15263 …_PD10 PWR_PDCRH_PD10_Msk /*!< Apply pull-down for PH10 */
15266 …_PD11 PWR_PDCRH_PD11_Msk /*!< Apply pull-down for PH11 */
15269 …_PD12 PWR_PDCRH_PD12_Msk /*!< Apply pull-down for PH12 */
15272 …_PD13 PWR_PDCRH_PD13_Msk /*!< Apply pull-down for PH13 */
15275 …_PD14 PWR_PDCRH_PD14_Msk /*!< Apply pull-down for PH14 */
15278 …_PD15 PWR_PDCRH_PD15_Msk /*!< Apply pull-down for PH15 */
15283 …RI_PU0 PWR_PUCRI_PU0_Msk /*!< Apply pull-up for PI0 */
15286 …RI_PU1 PWR_PUCRI_PU1_Msk /*!< Apply pull-up for PI1 */
15289 …RI_PU2 PWR_PUCRI_PU2_Msk /*!< Apply pull-up for PI2 */
15292 …RI_PU3 PWR_PUCRI_PU3_Msk /*!< Apply pull-up for PI3 */
15295 …RI_PU4 PWR_PUCRI_PU4_Msk /*!< Apply pull-up for PI4 */
15298 …RI_PU5 PWR_PUCRI_PU5_Msk /*!< Apply pull-up for PI5 */
15301 …RI_PU6 PWR_PUCRI_PU6_Msk /*!< Apply pull-up for PI6 */
15304 …RI_PU7 PWR_PUCRI_PU7_Msk /*!< Apply pull-up for PI7 */
15309 …_PD0 PWR_PDCRI_PD0_Msk /*!< Apply pull-down for PI0 */
15312 …_PD1 PWR_PDCRI_PD1_Msk /*!< Apply pull-down for PI1 */
15315 …_PD2 PWR_PDCRI_PD2_Msk /*!< Apply pull-down for PI2 */
15318 …_PD3 PWR_PDCRI_PD3_Msk /*!< Apply pull-down for PI3 */
15321 …_PD4 PWR_PDCRI_PD4_Msk /*!< Apply pull-down for PI4 */
15324 …_PD5 PWR_PDCRI_PD5_Msk /*!< Apply pull-down for PI5 */
15327 …_PD6 PWR_PDCRI_PD6_Msk /*!< Apply pull-down for PI6 */
15330 …_PD7 PWR_PDCRI_PD7_Msk /*!< Apply pull-down for PI7 */
15629 …PLLFAST_Msk /*!< Internal Multi Speed Oscillator (MSI) PLL Fast Mode Selection */
17205 … RCC_CCIPR1_LPTIM2SEL_Msk /*!< LPTIM2SEL[1:0]: bits (Low-power Timer 2 Kernel …
17357 #define RCC_BDCR_LSCOEN RCC_BDCR_LSCOEN_Msk /*!< Low-speed …
17360 #define RCC_BDCR_LSCOSEL RCC_BDCR_LSCOSEL_Msk /*!< Low-speed …
17369 #define RCC_BDCR_LSIPREDIV RCC_BDCR_LSIPREDIV_Msk /*!< Low-speed …
17409 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-power …
17458 #define RCC_PRIVCFGR_NSPRIV RCC_PRIVCFGR_NSPRIV_Msk /*!< RCC Non-Se…
17462 /* Real-Time Clock (RTC) */
17693 …_PU RTC_CR_TAMPALRM_PU_Msk /*!<TAMPALARM output pull-up config */
19860 #define SYSCFG_CFGR1_PB6_FMP SYSCFG_CFGR1_PB6_FMP_Msk /*!< PB6 Fast m…
19863 #define SYSCFG_CFGR1_PB7_FMP SYSCFG_CFGR1_PB7_FMP_Msk /*!< PB7 Fast m…
19866 #define SYSCFG_CFGR1_PB8_FMP SYSCFG_CFGR1_PB8_FMP_Msk /*!< PB8 Fast m…
19869 #define SYSCFG_CFGR1_PB9_FMP SYSCFG_CFGR1_PB9_FMP_Msk /*!< PB9 Fast m…
19873 …ne SYSCFG_FPUIMR_FPU_IE_Msk (0x3FUL << SYSCFG_FPUIMR_FPU_IE_Pos) /*!< 0x0000003F - */
19875 …U_IE_0 (0x1UL << SYSCFG_FPUIMR_FPU_IE_Pos) /*!< 0x00000001 - Invalid operation In…
19876 … (0x2UL << SYSCFG_FPUIMR_FPU_IE_Pos) /*!< 0x00000002 - Divide-by-zero Interrupt e…
19877 …U_IE_2 (0x4UL << SYSCFG_FPUIMR_FPU_IE_Pos) /*!< 0x00000004 - Underflow Interrupt …
19878 …U_IE_3 (0x8UL << SYSCFG_FPUIMR_FPU_IE_Pos) /*!< 0x00000008 - Overflow Interrupt e…
19879 …U_IE_4 (0x10UL << SYSCFG_FPUIMR_FPU_IE_Pos) /*!< 0x00000010 - Input denormal Inter…
19880 …U_IE_5 (0x20UL << SYSCFG_FPUIMR_FPU_IE_Pos) /*!< 0x00000020 - Inexact Interrupt en…
19888 …OCKNSMPU SYSCFG_CNSLCKR_LOCKNSMPU_Msk /*!< Disable Non-Secure MPU registers …
19979 … SYSCFG_UCPD_CC1ENRXFILTER_Msk /*!< USB PD BMC receiver 1 low-power analog filter */
19982 … SYSCFG_UCPD_CC2ENRXFILTER_Msk /*!< USB PD BMC receiver 2 low-power analog filter */
21211 … UCPD_CFG2_RXFILTDIS_Msk /*!< Enables an Rx pre-filter for the BMC de…
21214 …XFILT2N3_Msk /*!< Controls the sampling method for an Rx pre-filter for the BMC de…
21262 …R_ANASUBMODE UCPD_CR_ANASUBMODE_Msk /*!< Analog PHY sub-mode */
21278 … UCPD_CR_FRSTX_Msk /*!< Signal Fast Role Swap request */
21284 … UCPD_CR_CC1TCDIS_Msk /*!< The bit allows the Type-C detector for CC0 to…
21287 … UCPD_CR_CC2TCDIS_Msk /*!< The bit allows the Type-C detector for CC2 to…
21334 #define UCPD_IMR_FRSEVTIE UCPD_IMR_FRSEVTIE_Msk /*!< Fast Role …
21363 … UCPD_SR_RXORDDET_Msk /*!< Rx ordered set (4 K-codes) detected inter…
21394 #define UCPD_SR_FRSEVT UCPD_SR_FRSEVT_Msk /*!< Fast Role …
21435 #define UCPD_ICR_FRSEVTCF UCPD_ICR_FRSEVTCF_Msk /*!< Fast Role …
21464 …LID UCPD_RX_ORDSET_RXSOPKINVALID_Msk /*!< Rx Ordered Set corrupted K-Codes (Debug) */
21474 #define UCPD_RXDR_RXDATA UCPD_RXDR_RXDATA_Msk /*!< 8-bit rece…
21506 #define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk /*!< A-p…
21509 #define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk /*!< A-p…
21512 #define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk /*!< B-p…
21515 #define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-p…
21518 #define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-…
21528 …LSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */
21538 …SK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT han…
21586 #define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-d…
21624 …GDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
21686 … USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed …
21689 …_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
21692 …_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
21702 …YLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */
21708 …GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */
21845 …BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets r…
22213 … USB_OTG_GCCFG_PS2DET_Msk /*!< DM pull-up detection status */
22493 …HAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */
22772 …UP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets r…
22856 …T_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */
22865 … USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
22890 …T_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */
22910 …DDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detec…
22954 #define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-…
22957 … USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
22962 …_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
22976 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-P…
22979 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duple…
23018 … USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
23067 #define USART_RQR_ABRRQ ((uint16_t)0x0001) /*!< Auto-Baud …
23124 #define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud …
23127 #define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud …
23296 /* Inter-integrated Circuit Interface (I2C) */
23382 #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit add…
23385 #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit add…
23414 …A1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
23576 #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit rece…
23581 #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit tran…
23677 … SPI_CR1_HDDIR_Msk /*!<Rx/Tx direction at Half-duplex mode */
23683 #define SPI_CR1_CRC33_17 SPI_CR1_CRC33_17_Msk /*!<32-bit CRC …
23755 …IDI SPI_CFG2_MIDI_Msk /*!<Master Inter-Data Idleness */
23843 #define SPI_SR_RXP SPI_SR_RXP_Msk /*!<Rx-Packet a…
23846 #define SPI_SR_TXP SPI_SR_TXP_Msk /*!<Tx-Packet s…
23861 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!<Rx-Packet a…
23995 … WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to L…
24010 … WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
24105 #define PKA_MONTGOMERY_PARAM_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24106 #define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24109 #define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Out…
24112 #define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24113 #define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24114 #define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24115 #define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24116 #define PKA_MODULAR_EXP_IN_EXPONENT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24117 #define PKA_MODULAR_EXP_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24118 #define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE ((0x16C8UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24119 #define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT ((0x14B8UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24120 #define PKA_MODULAR_EXP_PROTECT_IN_MODULUS ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24121 #define PKA_MODULAR_EXP_PROTECT_IN_PHI ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24124 #define PKA_MODULAR_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Out…
24125 #define PKA_MODULAR_EXP_OUT_ERROR ((0x1298UL - PKA_RAM_OFFSET)>>2) /*!< Out…
24126 #define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Out…
24127 #define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Out…
24130 #define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24131 #define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24132 #define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24133 #define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24134 #define PKA_ECC_SCALAR_MUL_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24135 #define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24136 #define PKA_ECC_SCALAR_MUL_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24137 #define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24138 #define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24139 #define PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24142 #define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Out…
24143 #define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Out…
24144 #define PKA_ECC_SCALAR_MUL_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Out…
24147 #define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24148 #define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24149 #define PKA_POINT_CHECK_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24150 #define PKA_POINT_CHECK_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24151 #define PKA_POINT_CHECK_IN_MOD_GF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24152 #define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24153 #define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24154 #define PKA_POINT_CHECK_IN_MONTGOMERY_PARAM ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24157 #define PKA_POINT_CHECK_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Out…
24160 #define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24161 #define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24162 #define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24163 #define PKA_ECDSA_SIGN_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24164 #define PKA_ECDSA_SIGN_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24165 #define PKA_ECDSA_SIGN_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24166 #define PKA_ECDSA_SIGN_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24167 #define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24168 #define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24169 #define PKA_ECDSA_SIGN_IN_HASH_E ((0x0FE8UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24170 #define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0x0F28UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24171 #define PKA_ECDSA_SIGN_IN_ORDER_N ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24174 #define PKA_ECDSA_SIGN_OUT_ERROR ((0x0FE0UL - PKA_RAM_OFFSET)>>2) /*!< Out…
24175 #define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Out…
24176 #define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Out…
24177 #define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x1400UL - PKA_RAM_OFFSET)>>2) /*!< Ext…
24178 #define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1458UL - PKA_RAM_OFFSET)>>2) /*!< Ext…
24181 #define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24182 #define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24183 #define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x0468UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24184 #define PKA_ECDSA_VERIF_IN_A_COEFF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24185 #define PKA_ECDSA_VERIF_IN_MOD_GF ((0x04D0UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24186 #define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x0678UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24187 #define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x06D0UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24188 #define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0x12F8UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24189 #define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0x1350UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24190 #define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x10E0UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24191 #define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24192 #define PKA_ECDSA_VERIF_IN_HASH_E ((0x13A8UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24193 #define PKA_ECDSA_VERIF_IN_ORDER_N ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24196 #define PKA_ECDSA_VERIF_OUT_RESULT ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Out…
24199 #define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24200 #define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24201 #define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24202 #define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x0948UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24203 #define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x0B60UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24204 #define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24205 #define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24208 #define PKA_RSA_CRT_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Out…
24211 #define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24212 #define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24213 #define PKA_MODULAR_REDUC_IN_OPERAND ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24214 #define PKA_MODULAR_REDUC_IN_MODULUS ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24217 #define PKA_MODULAR_REDUC_OUT_RESULT ((0xE78UL - PKA_RAM_OFFSET)>>2) /*!< Out…
24220 #define PKA_ARITHMETIC_ADD_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24221 #define PKA_ARITHMETIC_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24222 #define PKA_ARITHMETIC_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24225 #define PKA_ARITHMETIC_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Out…
24228 #define PKA_ARITHMETIC_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24229 #define PKA_ARITHMETIC_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24230 #define PKA_ARITHMETIC_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24233 #define PKA_ARITHMETIC_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Out…
24236 #define PKA_ARITHMETIC_MUL_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24237 #define PKA_ARITHMETIC_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24238 #define PKA_ARITHMETIC_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24241 #define PKA_ARITHMETIC_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Out…
24244 #define PKA_COMPARISON_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24245 #define PKA_COMPARISON_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24246 #define PKA_COMPARISON_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24249 #define PKA_COMPARISON_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Out…
24252 #define PKA_MODULAR_ADD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24253 #define PKA_MODULAR_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24254 #define PKA_MODULAR_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24255 #define PKA_MODULAR_ADD_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24258 #define PKA_MODULAR_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Out…
24261 #define PKA_MODULAR_INV_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24262 #define PKA_MODULAR_INV_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24263 #define PKA_MODULAR_INV_IN_OP2_MOD ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24266 #define PKA_MODULAR_INV_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Out…
24269 #define PKA_MODULAR_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24270 #define PKA_MODULAR_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24271 #define PKA_MODULAR_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24272 #define PKA_MODULAR_SUB_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24275 #define PKA_MODULAR_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Out…
24278 #define PKA_MONTGOMERY_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24279 #define PKA_MONTGOMERY_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24280 #define PKA_MONTGOMERY_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24281 #define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24284 #define PKA_MONTGOMERY_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Out…
24287 #define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24288 #define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24289 #define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24290 #define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24293 #define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Out…
24296 #define PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24297 #define PKA_ECC_COMPLETE_ADD_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24298 #define PKA_ECC_COMPLETE_ADD_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24299 #define PKA_ECC_COMPLETE_ADD_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24300 #define PKA_ECC_COMPLETE_ADD_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24301 #define PKA_ECC_COMPLETE_ADD_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24302 #define PKA_ECC_COMPLETE_ADD_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24303 #define PKA_ECC_COMPLETE_ADD_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24304 #define PKA_ECC_COMPLETE_ADD_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24305 #define PKA_ECC_COMPLETE_ADD_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24308 #define PKA_ECC_COMPLETE_ADD_OUT_RESULT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Out…
24309 #define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Out…
24310 #define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Out…
24313 #define PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24314 #define PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24315 #define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24316 #define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24317 #define PKA_ECC_DOUBLE_LADDER_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24318 #define PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24319 #define PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24320 #define PKA_ECC_DOUBLE_LADDER_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24321 #define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24322 #define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24323 #define PKA_ECC_DOUBLE_LADDER_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24324 #define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24325 #define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24328 #define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Out…
24329 #define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Out…
24330 #define PKA_ECC_DOUBLE_LADDER_OUT_ERROR ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Out…
24333 #define PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24334 #define PKA_ECC_PROJECTIVE_AFF_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24335 #define PKA_ECC_PROJECTIVE_AFF_IN_POINT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24336 #define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24337 #define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24338 #define PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2 ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
24341 #define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Out…
24342 #define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Out…
24343 #define PKA_ECC_PROJECTIVE_AFF_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Out…
24856 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
25037 /******************** UART Instances : Half-Duplex mode **********************/
25060 /******************** UART Instances : Wake-up from Stop mode **********************/