Lines Matching +full:fail +full:- +full:fast
10 * - Data structures and the address mapping for all peripherals
11 * - Peripheral's registers declarations and bits definition
12 * - Macros to access peripheral's registers hardware
17 * Copyright (c) 2020-2021 STMicroelectronics.
22 * If no LICENSE file comes with this software, it is provided AS-IS.
57 …/****** Cortex-M0 Processor Exceptions Numbers **************************************************…
58 …NonMaskableInt_IRQn = -14, /*!< Non Maskable Interrupt …
59 …HardFault_IRQn = -13, /*!< Cortex-M0+ Hard Fault Interrupt …
60 …SVCall_IRQn = -5, /*!< Cortex-M0+ SV Call Interrupt …
61 …PendSV_IRQn = -2, /*!< Cortex-M0+ Pend SV Interrupt …
62 …SysTick_IRQn = -1, /*!< Cortex-M0+ System Tick Interrupt …
103 /****** Cortex-M4 Processor Exceptions Numbers ***************************************************…
104 …NonMaskableInt_IRQn = -14, /*!< Non Maskable Interrupt …
105 …HardFault_IRQn = -13, /*!< Cortex-M4 Hard Fault Interrupt …
106 …MemoryManagement_IRQn = -12, /*!< Cortex-M4 Memory Management Interrupt …
107 …BusFault_IRQn = -11, /*!< Cortex-M4 Bus Fault Interrupt …
108 …UsageFault_IRQn = -10, /*!< Cortex-M4 Usage Fault Interrupt …
109 …SVCall_IRQn = -5, /*!< Cortex-M4 SV Call Interrupt …
110 …DebugMonitor_IRQn = -4, /*!< Cortex-M4 Debug Monitor Interrupt …
111 …PendSV_IRQn = -2, /*!< Cortex-M4 Pend SV Interrupt …
112 …SysTick_IRQn = -1, /*!< Cortex-M4 System Tick Interrupt …
188 * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals
197 #include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */
201 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
210 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
246 … uint32_t RESERVED3[4]; /*!< Reserved, 0x30 - 0x3C */
248 … uint32_t RESERVED4[23];/*!< Reserved, 0x44 - 0x9C */
251 … uint32_t RESERVED5[3]; /*!< Reserved, 0xA8 - 0xB0 */
329 …__IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address o…
330 …__IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address o…
331 …__IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address o…
335 …__IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address o…
336 …__IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address o…
337 …__IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address o…
358 …uint32_t RESERVED1[13]; /*!< Reserved, 0x08-0x38 …
419 …4]; /*!< Reserved, Address offset: 0x10 - 0x1C */
424 …4]; /*!< Reserved, Address offset: 0x30 - 0x3C */
425 …8]; /*!< Reserved, Address offset: 0x40 - 0x5C */
426 …8]; /*!< Reserved, Address offset: 0x60 - 0x7C */
429 …2]; /*!< Reserved, Address offset: 0x88 - 0x8C */
432 …10]; /*!< Reserved, Address offset: 0x98 - 0xBC */
435 …2]; /*!< Reserved, Address offset: 0xC8 - 0xCC */
461 …ED2[7]; /*!< Reserved, Address offset: 0x40-0x58 */
465 …ED3[6]; /*!< Reserved, Address offset: 0x68-0x7C */
478 …__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
483 …__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
492 …SERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */
494 …SERVED2[3]; /*!< Reserved2, Address offset: 0x14-0x1C */
496 …SERVED3[67]; /*!< Reserved3, Address offset: 0x24-0x12C */
517 …__IO uint32_t R[16]; /*!< HSEM 2-step write lock and read back registers, Address offset: 00h…
518 …_t Reserved1[16]; /*!< Reserved Address offset: 40h-7Ch */
519 …__IO uint32_t RLR[16]; /*!< HSEM 1-step read lock registers, Address offset: 80h…
520 …_t Reserved2[16]; /*!< Reserved Address offset: C0h-FCh */
529 …_t Reserved[8]; /*!< Reserved Address offset: 120h-13Ch*/
543 * @brief Inter-integrated Circuit Interface
561 * @brief Inter-Processor Communication
565 …__IO uint32_t C1CR; /*!< Inter-Processor Communication: C1 control register, …
566 …__IO uint32_t C1MR ; /*!< Inter-Processor Communication: C1 mask register, …
567 …__IO uint32_t C1SCR; /*!< Inter-Processor Communication: C1 status set clear register, …
568 …__IO uint32_t C1TOC2SR; /*!< Inter-Processor Communication: C1 to processor M4 status reg…
569 …__IO uint32_t C2CR; /*!< Inter-Processor Communication: C2 control register, …
570 …__IO uint32_t C2MR ; /*!< Inter-Processor Communication: C2 mask register, …
571 …__IO uint32_t C2SCR; /*!< Inter-Processor Communication: C2 status set clear register, …
572 …__IO uint32_t C2TOC1SR; /*!< Inter-Processor Communication: C2 to processor M4 status regi…
621 …uint32_t Reserved1[253]; /*!< Reserved Address offset: 0x000C-0x03F…
622 …__IO uint32_t RAM[894]; /*!< PKA RAM, Address offset: 0x0400-0x11F…
638 …__IO uint32_t PUCRA; /*!< PWR Pull-Up Control Register of port A, Address offset:…
639 …__IO uint32_t PDCRA; /*!< PWR Pull-Down Control Register of port A, Address offset:…
640 …__IO uint32_t PUCRB; /*!< PWR Pull-Up Control Register of port B, Address offset:…
641 …__IO uint32_t PDCRB; /*!< PWR Pull-Down Control Register of port B, Address offset:…
642 …__IO uint32_t PUCRC; /*!< PWR Pull-Up Control Register of port C, Address offset:…
643 …__IO uint32_t PDCRC; /*!< PWR Pull-Down Control Register of port C, Address offset:…
644 …t RESERVED0[8]; /*!< Reserved, Address offset: 0x38-0x54 */
645 …__IO uint32_t PUCRH; /*!< PWR Pull-Up Control Register of port H, Address offset:…
646 …__IO uint32_t PDCRH; /*!< PWR Pull-Down Control Register of port H, Address offset:…
647 …t RESERVED1[8]; /*!< Reserved, Address offset: 0x60-0x7C */
700 … Address offset: 0x98-0x104 */
702 … Address offset: 0x10C-0x144 */
740 * @brief Real-Time Clock
758 …__IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x…
796 …SCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
801 …served, Address offset: 0x28-0xFC */
802 …__IO uint32_t IMR1; /*!< SYSCFG CPU1 (CORTEX M4) interrupt masks control-status regis…
803 …__IO uint32_t IMR2; /*!< SYSCFG CPU1 (CORTEX M4) interrupt masks control-status regis…
804 …__IO uint32_t C2IMR1; /*!< SYSCFG CPU2 (CORTEX M0) interrupt masks control-status regis…
805 …__IO uint32_t C2IMR2; /*!< SYSCFG CPU2 (CORTEX M0) interrupt masks control-status regis…
806 …served, Address offset: 0x110-0x204*/
826 …uint32_t RESERVED2[47];/*!< Reserved, Address offset: 0x54 - 0xFC */
865 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
871 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
940 … (SYSTEM_FLASH_BASE + 0x00007000UL) /*!< OTP area : 1kB (0x1FFF7000 - 0x1FFF73FF) */
941 …SE (SYSTEM_FLASH_BASE + 0x00007400UL) /*!< Engi Bytes : 1kB (0x1FFF7400 - 0x1FFF77FF) */
942 …BASE (SYSTEM_FLASH_BASE + 0x00007800UL) /*!< Option Bytes : 2kB (0x1FFF7800 - 0x1FFF7FFF) */
946 #define UID64_BASE (ENGI_BYTES_BASE + 0x00000180UL) /*!< 64-bit Unique device Identifi…
950 #define SYSTEM_MEMORY_END_ADDR (0x1FFF6FFFUL) /*!< System Memory : 28KB (0x1FFF0000 - 0x1FFF6FFF…
951 #define OTP_AREA_END_ADDR (0x1FFF73FFUL) /*!< OTP area : 1KB (0x1FFF7000 - 0x1FFF73FF) …
952 #define ENGI_BYTE_END_ADDR (0x1FFF77FFUL) /*!< Engi Bytes : 1kB (0x1FFF7400 - 0x1FFF77FF) …
953 #define OPTION_BYTE_END_ADDR (0x1FFF7FFFUL) /*!< Option Bytes : 2KB (0x1FFF7800 - 0x1FFF7FFF) …
1860 … ADC_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */
2017 #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-…
2022 #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-…
2027 #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-b…
2032 #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-…
2037 #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-…
2042 #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-b…
2333 #define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - B…
2342 … USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
2367 #define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - B…
2387 #define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit …
2431 #define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate …
2434 … USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
2439 #define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-O…
2453 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power …
2456 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Sel…
2495 … USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
2549 #define USART_RQR_ABRRQ ((uint16_t)0x0001) /*!< Auto-Baud Rate …
2600 #define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate …
2603 #define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate …
2720 … CRC_IDR_IDR_Msk /*!< General-purpose 8-bits data regist…
4338 #define FLASH_SR_MISERR FLASH_SR_MISERR_Msk /*!< Fast programmin…
4341 #define FLASH_SR_FASTERR FLASH_SR_FASTERR_Msk /*!< Fast programmin…
4382 #define FLASH_CR_FSTPG FLASH_CR_FSTPG_Msk /*!< Fast programmin…
4405 …CC FLASH_ECCR_ADDR_ECC_Msk /*!< double-word address ECC fail …
4408 … FLASH_ECCR_SYSF_ECC_Msk /*!< System flash ECC fail …
4560 #define FLASH_C2SR_MISERR FLASH_C2SR_MISERR_Msk /*!< CPU2 Fast progra…
4563 #define FLASH_C2SR_FASTERR FLASH_C2SR_FASTERR_Msk /*!< CPU2 Fast progra…
4595 #define FLASH_C2CR_FSTPG FLASH_C2CR_FSTPG_Msk /*!< CPU2 Fast progra…
4624 #define FLASH_SFR_SUBGHZSPISD FLASH_SFR_SUBGHZSPISD_Msk /* Sub-GHz radio …
4640 #define FLASH_SRRVR_SNBRSA FLASH_SRRVR_SNBRSA_Msk /* Secure non-backu…
4643 #define FLASH_SRRVR_NBRSD FLASH_SRRVR_NBRSD_Msk /* Non-backup SRAM1…
5874 #define PKA_MONTGOMERY_PARAM_IN_MOD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input modul…
5875 #define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input modul…
5878 #define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x594U - PKA_RAM_OFFSET)>>2) /*!< Output Mont…
5881 #define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Input expon…
5882 #define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
5883 #define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x594U - PKA_RAM_OFFSET)>>2) /*!< Input stora…
5884 #define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input base …
5885 #define PKA_MODULAR_EXP_IN_EXPONENT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Input expon…
5886 #define PKA_MODULAR_EXP_IN_MODULUS ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input modul…
5889 #define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x594U - PKA_RAM_OFFSET)>>2) /*!< Output stor…
5890 #define PKA_MODULAR_EXP_OUT_SM_ALGO_ACC1 ((0x724U - PKA_RAM_OFFSET)>>2) /*!< Output SM a…
5891 #define PKA_MODULAR_EXP_OUT_SM_ALGO_ACC2 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Output SM a…
5892 #define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Output base…
5893 #define PKA_MODULAR_EXP_OUT_SM_ALGO_ACC3 ((0xE3CU - PKA_RAM_OFFSET)>>2) /*!< Output SM a…
5896 #define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Input expon…
5897 #define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
5898 #define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x408U - PKA_RAM_OFFSET)>>2) /*!< Input sign …
5899 #define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x40CU - PKA_RAM_OFFSET)>>2) /*!< Input ECC c…
5900 #define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x460U - PKA_RAM_OFFSET)>>2) /*!< Input modul…
5901 #define PKA_ECC_SCALAR_MUL_IN_MONTGOMERY_PARAM ((0x4B4U - PKA_RAM_OFFSET)>>2) /*!< Input stora…
5902 #define PKA_ECC_SCALAR_MUL_IN_K ((0x508U - PKA_RAM_OFFSET)>>2) /*!< Input 'k' o…
5903 #define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x55CU - PKA_RAM_OFFSET)>>2) /*!< Input initi…
5904 #define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Input initi…
5907 #define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x55CU - PKA_RAM_OFFSET)>>2) /*!< Output resu…
5908 #define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Output resu…
5909 #define PKA_ECC_SCALAR_MUL_OUT_LAST_DOUBLE_X1 ((0xDE8U - PKA_RAM_OFFSET)>>2) /*!< Output last…
5910 #define PKA_ECC_SCALAR_MUL_OUT_LAST_DOUBLE_Y1 ((0xE3CU - PKA_RAM_OFFSET)>>2) /*!< Output last…
5911 #define PKA_ECC_SCALAR_MUL_OUT_LAST_DOUBLE_Z1 ((0xE90U - PKA_RAM_OFFSET)>>2) /*!< Output last…
5912 #define PKA_ECC_SCALAR_MUL_OUT_CHECK_POINT_X2 ((0xEE4U - PKA_RAM_OFFSET)>>2) /*!< Output chec…
5913 #define PKA_ECC_SCALAR_MUL_OUT_CHECK_POINT_Y2 ((0xF38U - PKA_RAM_OFFSET)>>2) /*!< Output chec…
5914 #define PKA_ECC_SCALAR_MUL_OUT_CHECK_POINT_Z2 ((0xF8CU - PKA_RAM_OFFSET)>>2) /*!< Output chec…
5917 #define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input modul…
5918 #define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x408U - PKA_RAM_OFFSET)>>2) /*!< Input sign …
5919 #define PKA_POINT_CHECK_IN_A_COEFF ((0x40CU - PKA_RAM_OFFSET)>>2) /*!< Input ECC c…
5920 #define PKA_POINT_CHECK_IN_B_COEFF ((0x7FCU - PKA_RAM_OFFSET)>>2) /*!< Input ECC c…
5921 #define PKA_POINT_CHECK_IN_MOD_GF ((0x460U - PKA_RAM_OFFSET)>>2) /*!< Input modul…
5922 #define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x55CU - PKA_RAM_OFFSET)>>2) /*!< Input initi…
5923 #define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Input initi…
5926 #define PKA_POINT_CHECK_OUT_ERROR ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Output erro…
5929 #define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Input order…
5930 #define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input modul…
5931 #define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x408U - PKA_RAM_OFFSET)>>2) /*!< Input sign …
5932 #define PKA_ECDSA_SIGN_IN_A_COEFF ((0x40CU - PKA_RAM_OFFSET)>>2) /*!< Input ECC c…
5933 #define PKA_ECDSA_SIGN_IN_MOD_GF ((0x460U - PKA_RAM_OFFSET)>>2) /*!< Input modul…
5934 #define PKA_ECDSA_SIGN_IN_K ((0x508U - PKA_RAM_OFFSET)>>2) /*!< Input k val…
5935 #define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x55CU - PKA_RAM_OFFSET)>>2) /*!< Input initi…
5936 #define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Input initi…
5937 #define PKA_ECDSA_SIGN_IN_HASH_E ((0xDE8U - PKA_RAM_OFFSET)>>2) /*!< Input e, ha…
5938 #define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0xE3CU - PKA_RAM_OFFSET)>>2) /*!< Input d, pr…
5939 #define PKA_ECDSA_SIGN_IN_ORDER_N ((0xE94U - PKA_RAM_OFFSET)>>2) /*!< Input n, or…
5942 #define PKA_ECDSA_SIGN_OUT_ERROR ((0xEE8U - PKA_RAM_OFFSET)>>2) /*!< Output erro…
5943 #define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x700U - PKA_RAM_OFFSET)>>2) /*!< Output sign…
5944 #define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x754U - PKA_RAM_OFFSET)>>2) /*!< Output sign…
5945 #define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x103CU - PKA_RAM_OFFSET)>>2) /*!< Output fin…
5946 #define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1090U - PKA_RAM_OFFSET)>>2) /*!< Output fin…
5949 #define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input order…
5950 #define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x4B4U - PKA_RAM_OFFSET)>>2) /*!< Input modul…
5951 #define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x45CU - PKA_RAM_OFFSET)>>2) /*!< Input sign …
5952 #define PKA_ECDSA_VERIF_IN_A_COEFF ((0x460U - PKA_RAM_OFFSET)>>2) /*!< Input ECC c…
5953 #define PKA_ECDSA_VERIF_IN_MOD_GF ((0x4B8U - PKA_RAM_OFFSET)>>2) /*!< Input modul…
5954 #define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x5E8U - PKA_RAM_OFFSET)>>2) /*!< Input initi…
5955 #define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x63CU - PKA_RAM_OFFSET)>>2) /*!< Input initi…
5956 #define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0xF40U - PKA_RAM_OFFSET)>>2) /*!< Input publi…
5957 #define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0xF94U - PKA_RAM_OFFSET)>>2) /*!< Input publi…
5958 #define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x1098U - PKA_RAM_OFFSET)>>2) /*!< Input r, p…
5959 #define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input s, pa…
5960 #define PKA_ECDSA_VERIF_IN_HASH_E ((0xFE8U - PKA_RAM_OFFSET)>>2) /*!< Input e, ha…
5961 #define PKA_ECDSA_VERIF_IN_ORDER_N ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input n, or…
5964 #define PKA_ECDSA_VERIF_OUT_RESULT ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Output resu…
5967 #define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
5968 #define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x65CU - PKA_RAM_OFFSET)>>2) /*!< Input Dp CR…
5969 #define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Input Dq CR…
5970 #define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x7ECU - PKA_RAM_OFFSET)>>2) /*!< Input qInv …
5971 #define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x97CU - PKA_RAM_OFFSET)>>2) /*!< Input Prime…
5972 #define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input Prime…
5973 #define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0xEECU - PKA_RAM_OFFSET)>>2) /*!< Input base …
5976 #define PKA_RSA_CRT_EXP_OUT_RESULT ((0x724U - PKA_RAM_OFFSET)>>2) /*!< Output resu…
5979 #define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
5980 #define PKA_MODULAR_REDUC_IN_OPERAND ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
5981 #define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input modul…
5982 #define PKA_MODULAR_REDUC_IN_MODULUS ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input modul…
5985 #define PKA_MODULAR_REDUC_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output resu…
5988 #define PKA_ARITHMETIC_ADD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
5989 #define PKA_ARITHMETIC_ADD_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
5990 #define PKA_ARITHMETIC_ADD_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
5993 #define PKA_ARITHMETIC_ADD_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output resu…
5996 #define PKA_ARITHMETIC_SUB_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
5997 #define PKA_ARITHMETIC_SUB_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
5998 #define PKA_ARITHMETIC_SUB_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
6001 #define PKA_ARITHMETIC_SUB_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output resu…
6004 #define PKA_ARITHMETIC_MUL_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
6005 #define PKA_ARITHMETIC_MUL_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
6006 #define PKA_ARITHMETIC_MUL_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
6009 #define PKA_ARITHMETIC_MUL_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output resu…
6012 #define PKA_COMPARISON_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
6013 #define PKA_COMPARISON_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
6014 #define PKA_COMPARISON_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
6017 #define PKA_COMPARISON_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output resu…
6020 #define PKA_MODULAR_ADD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
6021 #define PKA_MODULAR_ADD_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
6022 #define PKA_MODULAR_ADD_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
6023 #define PKA_MODULAR_ADD_IN_OP3_MOD ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input opera…
6026 #define PKA_MODULAR_ADD_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output resu…
6029 #define PKA_MODULAR_INV_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
6030 #define PKA_MODULAR_INV_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
6031 #define PKA_MODULAR_INV_IN_OP2_MOD ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
6034 #define PKA_MODULAR_INV_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output resu…
6037 #define PKA_MODULAR_SUB_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
6038 #define PKA_MODULAR_SUB_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
6039 #define PKA_MODULAR_SUB_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
6040 #define PKA_MODULAR_SUB_IN_OP3_MOD ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input opera…
6043 #define PKA_MODULAR_SUB_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output resu…
6046 #define PKA_MONTGOMERY_MUL_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
6047 #define PKA_MONTGOMERY_MUL_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
6048 #define PKA_MONTGOMERY_MUL_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
6049 #define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input modul…
6052 #define PKA_MONTGOMERY_MUL_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output resu…
6055 #define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
6056 #define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
6057 #define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
6058 #define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input opera…
6061 #define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output resu…
6079 #define PWR_CR1_SUBGHZSPINSSSEL PWR_CR1_SUBGHZSPINSSSEL_Msk /*!< Sub-GHz radio S…
6101 #define PWR_CR1_LPR PWR_CR1_LPR_Msk /*!< Regulator Low-P…
6122 … PWR_CR3_EWUP_Msk /*!< Enable all external Wake-Up lines */
6147 … PWR_CR3_APC_Msk /*!< Apply pull-up and pull-down configurat…
6151 … PWR_CR3_EWRFBUSY_Msk /*!< Enable Radio busy IRQ and wake-up for CPU1 */
6154 … PWR_CR3_EWRFIRQ_Msk /*!< Enable Radio IRQ[2:0] and wake-up for CPU1 */
6162 #define PWR_CR3_EIWUL PWR_CR3_EIWUL_Msk /*!< Internal Wake-U…
6167 #define PWR_CR4_WP1 PWR_CR4_WP1_Msk /*!< Wake-Up Pin 1 […
6170 #define PWR_CR4_WP2 PWR_CR4_WP2_Msk /*!< Wake-Up Pin 2 […
6173 #define PWR_CR4_WP3 PWR_CR4_WP3_Msk /*!< Wake-Up Pin 3 […
6184 #define PWR_CR4_WRFBUSYP PWR_CR4_WRFBUSYP_Msk /*!< Wake-up radio b…
6254 #define PWR_SR2_REGLPS PWR_SR2_REGLPS_Msk /*!< Low-power regul…
6257 #define PWR_SR2_REGLPF PWR_SR2_REGLPF_Msk /*!< Low-power regul…
6273 #define PWR_SCR_CWUF PWR_SCR_CWUF_Msk /*!< Clear Wake-up F…
6276 #define PWR_SCR_CWUF1 PWR_SCR_CWUF1_Msk /*!< Clear Wake-up P…
6279 #define PWR_SCR_CWUF2 PWR_SCR_CWUF2_Msk /*!< Clear Wake-up P…
6282 #define PWR_SCR_CWUF3 PWR_SCR_CWUF3_Msk /*!< Clear Wake-up P…
6308 #define PWR_PUCRA_PA0 PWR_PUCRA_PA0_Msk /*!< Pin PA0 Pull-Up…
6311 #define PWR_PUCRA_PA1 PWR_PUCRA_PA1_Msk /*!< Pin PA1 Pull-Up…
6314 #define PWR_PUCRA_PA2 PWR_PUCRA_PA2_Msk /*!< Pin PA2 Pull-Up…
6317 #define PWR_PUCRA_PA3 PWR_PUCRA_PA3_Msk /*!< Pin PA3 Pull-Up…
6320 #define PWR_PUCRA_PA4 PWR_PUCRA_PA4_Msk /*!< Pin PA4 Pull-Up…
6323 #define PWR_PUCRA_PA5 PWR_PUCRA_PA5_Msk /*!< Pin PA5 Pull-Up…
6326 #define PWR_PUCRA_PA6 PWR_PUCRA_PA6_Msk /*!< Pin PA6 Pull-Up…
6329 #define PWR_PUCRA_PA7 PWR_PUCRA_PA7_Msk /*!< Pin PA7 Pull-Up…
6332 #define PWR_PUCRA_PA8 PWR_PUCRA_PA8_Msk /*!< Pin PA8 Pull-Up…
6335 #define PWR_PUCRA_PA9 PWR_PUCRA_PA9_Msk /*!< Pin PA9 Pull-Up…
6338 #define PWR_PUCRA_PA10 PWR_PUCRA_PA10_Msk /*!< Pin PA10 Pull-U…
6341 #define PWR_PUCRA_PA11 PWR_PUCRA_PA11_Msk /*!< Pin PA11 Pull-U…
6344 #define PWR_PUCRA_PA12 PWR_PUCRA_PA12_Msk /*!< Pin PA12 Pull-U…
6347 #define PWR_PUCRA_PA13 PWR_PUCRA_PA13_Msk /*!< Pin PA13 Pull-U…
6350 #define PWR_PUCRA_PA14 PWR_PUCRA_PA14_Msk /*!< Pin PA14 Pull-U…
6353 #define PWR_PUCRA_PA15 PWR_PUCRA_PA15_Msk /*!< Pin PA15 Pull-U…
6358 #define PWR_PDCRA_PA0 PWR_PDCRA_PA0_Msk /*!< Pin PA0 Pull-Do…
6361 #define PWR_PDCRA_PA1 PWR_PDCRA_PA1_Msk /*!< Pin PA1 Pull-Do…
6364 #define PWR_PDCRA_PA2 PWR_PDCRA_PA2_Msk /*!< Pin PA2 Pull-Do…
6367 #define PWR_PDCRA_PA3 PWR_PDCRA_PA3_Msk /*!< Pin PA3 Pull-Do…
6370 #define PWR_PDCRA_PA4 PWR_PDCRA_PA4_Msk /*!< Pin PA4 Pull-Do…
6373 #define PWR_PDCRA_PA5 PWR_PDCRA_PA5_Msk /*!< Pin PA5 Pull-Do…
6376 #define PWR_PDCRA_PA6 PWR_PDCRA_PA6_Msk /*!< Pin PA6 Pull-Do…
6379 #define PWR_PDCRA_PA7 PWR_PDCRA_PA7_Msk /*!< Pin PA7 Pull-Do…
6382 #define PWR_PDCRA_PA8 PWR_PDCRA_PA8_Msk /*!< Pin PA8 Pull-Do…
6385 #define PWR_PDCRA_PA9 PWR_PDCRA_PA9_Msk /*!< Pin PA9 Pull-Do…
6388 #define PWR_PDCRA_PA10 PWR_PDCRA_PA10_Msk /*!< Pin PA10 Pull-D…
6391 #define PWR_PDCRA_PA11 PWR_PDCRA_PA11_Msk /*!< Pin PA11 Pull-D…
6394 #define PWR_PDCRA_PA12 PWR_PDCRA_PA12_Msk /*!< Pin PA12 Pull-D…
6397 #define PWR_PDCRA_PA13 PWR_PDCRA_PA13_Msk /*!< Pin PA13 Pull-D…
6400 #define PWR_PDCRA_PA14 PWR_PDCRA_PA14_Msk /*!< Pin PA14 Pull-D…
6403 #define PWR_PDCRA_PA15 PWR_PDCRA_PA15_Msk /*!< Pin PA15 Pull-D…
6408 #define PWR_PUCRB_PB0 PWR_PUCRB_PB0_Msk /*!< Pin PB0 Pull-Up…
6411 #define PWR_PUCRB_PB1 PWR_PUCRB_PB1_Msk /*!< Pin PB1 Pull-Up…
6414 #define PWR_PUCRB_PB2 PWR_PUCRB_PB2_Msk /*!< Pin PB2 Pull-Up…
6417 #define PWR_PUCRB_PB3 PWR_PUCRB_PB3_Msk /*!< Pin PB3 Pull-Up…
6420 #define PWR_PUCRB_PB4 PWR_PUCRB_PB4_Msk /*!< Pin PB4 Pull-Up…
6423 #define PWR_PUCRB_PB5 PWR_PUCRB_PB5_Msk /*!< Pin PB5 Pull-Up…
6426 #define PWR_PUCRB_PB6 PWR_PUCRB_PB6_Msk /*!< Pin PB6 Pull-Up…
6429 #define PWR_PUCRB_PB7 PWR_PUCRB_PB7_Msk /*!< Pin PB7 Pull-Up…
6432 #define PWR_PUCRB_PB8 PWR_PUCRB_PB8_Msk /*!< Pin PB8 Pull-Up…
6435 #define PWR_PUCRB_PB9 PWR_PUCRB_PB9_Msk /*!< Pin PB9 Pull-Up…
6438 #define PWR_PUCRB_PB10 PWR_PUCRB_PB10_Msk /*!< Pin PB10 Pull-U…
6441 #define PWR_PUCRB_PB11 PWR_PUCRB_PB11_Msk /*!< Pin PB11 Pull-U…
6444 #define PWR_PUCRB_PB12 PWR_PUCRB_PB12_Msk /*!< Pin PB12 Pull-U…
6447 #define PWR_PUCRB_PB13 PWR_PUCRB_PB13_Msk /*!< Pin PB13 Pull-U…
6450 #define PWR_PUCRB_PB14 PWR_PUCRB_PB14_Msk /*!< Pin PB14 Pull-U…
6453 #define PWR_PUCRB_PB15 PWR_PUCRB_PB15_Msk /*!< Pin PB15 Pull-U…
6458 #define PWR_PDCRB_PB0 PWR_PDCRB_PB0_Msk /*!< Pin PB0 Pull-Do…
6461 #define PWR_PDCRB_PB1 PWR_PDCRB_PB1_Msk /*!< Pin PB1 Pull-Do…
6464 #define PWR_PDCRB_PB2 PWR_PDCRB_PB2_Msk /*!< Pin PB2 Pull-Do…
6467 #define PWR_PDCRB_PB3 PWR_PDCRB_PB3_Msk /*!< Pin PB3 Pull-Do…
6470 #define PWR_PDCRB_PB4 PWR_PDCRB_PB4_Msk /*!< Pin PB4 Pull-Do…
6473 #define PWR_PDCRB_PB5 PWR_PDCRB_PB5_Msk /*!< Pin PB5 Pull-Do…
6476 #define PWR_PDCRB_PB6 PWR_PDCRB_PB6_Msk /*!< Pin PB6 Pull-Do…
6479 #define PWR_PDCRB_PB7 PWR_PDCRB_PB7_Msk /*!< Pin PB7 Pull-Do…
6482 #define PWR_PDCRB_PB8 PWR_PDCRB_PB8_Msk /*!< Pin PB8 Pull-Do…
6485 #define PWR_PDCRB_PB9 PWR_PDCRB_PB9_Msk /*!< Pin PB9 Pull-Do…
6488 #define PWR_PDCRB_PB10 PWR_PDCRB_PB10_Msk /*!< Pin PB10 Pull-D…
6491 #define PWR_PDCRB_PB11 PWR_PDCRB_PB11_Msk /*!< Pin PB11 Pull-D…
6494 #define PWR_PDCRB_PB12 PWR_PDCRB_PB12_Msk /*!< Pin PB12 Pull-D…
6497 #define PWR_PDCRB_PB13 PWR_PDCRB_PB13_Msk /*!< Pin PB13 Pull-D…
6500 #define PWR_PDCRB_PB14 PWR_PDCRB_PB14_Msk /*!< Pin PB14 Pull-D…
6503 #define PWR_PDCRB_PB15 PWR_PDCRB_PB15_Msk /*!< Pin PB15 Pull-D…
6508 #define PWR_PUCRC_PC0 PWR_PUCRC_PC0_Msk /*!< Pin PC0 Pull-Up…
6511 #define PWR_PUCRC_PC1 PWR_PUCRC_PC1_Msk /*!< Pin PC1 Pull-Up…
6514 #define PWR_PUCRC_PC2 PWR_PUCRC_PC2_Msk /*!< Pin PC2 Pull-Up…
6517 #define PWR_PUCRC_PC3 PWR_PUCRC_PC3_Msk /*!< Pin PC3 Pull-Up…
6520 #define PWR_PUCRC_PC4 PWR_PUCRC_PC4_Msk /*!< Pin PC4 Pull-Up…
6523 #define PWR_PUCRC_PC5 PWR_PUCRC_PC5_Msk /*!< Pin PC5 Pull-Up…
6526 #define PWR_PUCRC_PC6 PWR_PUCRC_PC6_Msk /*!< Pin PC6 Pull-Up…
6529 #define PWR_PUCRC_PC13 PWR_PUCRC_PC13_Msk /*!< Pin PC13 Pull-U…
6532 #define PWR_PUCRC_PC14 PWR_PUCRC_PC14_Msk /*!< Pin PC14 Pull-U…
6535 #define PWR_PUCRC_PC15 PWR_PUCRC_PC15_Msk /*!< Pin PC15 Pull-U…
6540 #define PWR_PDCRC_PC0 PWR_PDCRC_PC0_Msk /*!< Pin PC0 Pull-Do…
6543 #define PWR_PDCRC_PC1 PWR_PDCRC_PC1_Msk /*!< Pin PC1 Pull-Do…
6546 #define PWR_PDCRC_PC2 PWR_PDCRC_PC2_Msk /*!< Pin PC2 Pull-Do…
6549 #define PWR_PDCRC_PC3 PWR_PDCRC_PC3_Msk /*!< Pin PC3 Pull-Do…
6552 #define PWR_PDCRC_PC4 PWR_PDCRC_PC4_Msk /*!< Pin PC4 Pull-Do…
6555 #define PWR_PDCRC_PC5 PWR_PDCRC_PC5_Msk /*!< Pin PC5 Pull-Do…
6558 #define PWR_PDCRC_PC6 PWR_PDCRC_PC6_Msk /*!< Pin PC6 Pull-Do…
6561 #define PWR_PDCRC_PC13 PWR_PDCRC_PC13_Msk /*!< Pin PC13 Pull-D…
6564 #define PWR_PDCRC_PC14 PWR_PDCRC_PC14_Msk /*!< Pin PC14 Pull-D…
6567 #define PWR_PDCRC_PC15 PWR_PDCRC_PC15_Msk /*!< Pin PC15 Pull-D…
6572 #define PWR_PUCRH_PH3 PWR_PUCRH_PH3_Msk /*!< Pin PH3 Pull-Up…
6577 #define PWR_PDCRH_PH3 PWR_PDCRH_PH3_Msk /*!< Pin PH3 Pull-Do…
6598 … PWR_C2CR3_EWUP_Msk /*!< Enable all external Wake-Up lines for CPU2 */
6615 … PWR_C2CR3_APC_Msk /*!< Apply pull-up and pull-down configurat…
6619 … PWR_C2CR3_EWRFBUSY_Msk /*!< Enable Radio busy IRQ and wake-up for CPU2 */
6622 … PWR_C2CR3_EWRFIRQ_Msk /*!< Enable Radio IRQ[2:0] and wake-up for CPU2 */
6626 #define PWR_C2CR3_EIWUL PWR_C2CR3_EIWUL_Msk /*!< Internal Wake-U…
6671 #define PWR_SUBGHZSPICR_NSS PWR_SUBGHZSPICR_NSS_Msk /*!< Sub-GHz radio…
7843 /* Real-Time Clock (RTC) */
7997 …PALRM_PU RTC_CR_TAMPALRM_PU_Msk /*!<TAMPALARM output pull-up config */
8981 …6_FMP SYSCFG_CFGR1_I2C_PB6_FMP_Msk /*!< Fast-mode Plus (Fm+) dri…
8984 …7_FMP SYSCFG_CFGR1_I2C_PB7_FMP_Msk /*!< Fast-mode Plus (Fm+) dri…
8987 …8_FMP SYSCFG_CFGR1_I2C_PB8_FMP_Msk /*!< Fast-mode Plus (Fm+) dri…
8990 …9_FMP SYSCFG_CFGR1_I2C_PB9_FMP_Msk /*!< Fast-mode Plus (Fm+) dri…
8993 … SYSCFG_CFGR1_I2C1_FMP_Msk /*!< I2C1 Fast-mode Plus (Fm+) dri…
8996 … SYSCFG_CFGR1_I2C2_FMP_Msk /*!< I2C2 Fast-mode Plus (Fm+) dri…
8999 … SYSCFG_CFGR1_I2C3_FMP_Msk /*!< I2C3 Fast-mode Plus (Fm+) dri…
9194 …E0_Msk /*!< SRAM2 Write protection page 0 (0x20008000 - 0x200083FF) */
9197 …E1_Msk /*!< SRAM2 Write protection page 1 (0x20008400 - 0x200087FF) */
9200 …E2_Msk /*!< SRAM2 Write protection page 2 (0x20008800 - 0x20008BFF) */
9203 …E3_Msk /*!< SRAM2 Write protection page 3 (0x20008C00 - 0x20008FFF) */
9206 …E4_Msk /*!< SRAM2 Write protection page 4 (0x20009000 - 0x200093FF) */
9209 …E5_Msk /*!< SRAM2 Write protection page 5 (0x20009400 - 0x200097FF) */
9212 …E6_Msk /*!< SRAM2 Write protection page 6 (0x20009800 - 0x20009BFF) */
9215 …E7_Msk /*!< SRAM2 Write protection page 7 (0x20009C00 - 0x20009FFF) */
9218 …E8_Msk /*!< SRAM2 Write protection page 8 (0x2000A000 - 0x2000A3FF) */
9221 …E9_Msk /*!< SRAM2 Write protection page 9 (0x2000A400 - 0x2000A7FF) */
9224 …E10_Msk /*!< SRAM2 Write protection page 10 (0x2000A800 - 0x2000ABFF) */
9227 …E11_Msk /*!< SRAM2 Write protection page 11 (0x2000AC00 - 0x2000AFFF) */
9230 …E12_Msk /*!< SRAM2 Write protection page 12 (0x2000B000 - 0x2000B3FF) */
9233 …E13_Msk /*!< SRAM2 Write protection page 13 (0x2000B400 - 0x2000B7FF) */
9236 …E14_Msk /*!< SRAM2 Write protection page 14 (0x2000B800 - 0x2000BBFF) */
9239 …E15_Msk /*!< SRAM2 Write protection page 15 (0x2000BC00 - 0x2000BFFF) */
9242 …E16_Msk /*!< SRAM2 Write protection page 16 (0x2000C000 - 0x2000C3FF) */
9245 …E17_Msk /*!< SRAM2 Write protection page 17 (0x2000C400 - 0x2000C7FF) */
9248 …E18_Msk /*!< SRAM2 Write protection page 18 (0x2000C800 - 0x2000CBFF) */
9251 …E19_Msk /*!< SRAM2 Write protection page 19 (0x2000CC00 - 0x2000CFFF) */
9254 …E20_Msk /*!< SRAM2 Write protection page 20 (0x2000D000 - 0x2000D3FF) */
9257 …E21_Msk /*!< SRAM2 Write protection page 21 (0x2000D400 - 0x2000D7FF) */
9260 …E22_Msk /*!< SRAM2 Write protection page 22 (0x2000D800 - 0x2000DBFF) */
9263 …E23_Msk /*!< SRAM2 Write protection page 23 (0x2000DC00 - 0x2000DFFF) */
9266 …E24_Msk /*!< SRAM2 Write protection page 24 (0x2000E000 - 0x2000E3FF) */
9269 …E25_Msk /*!< SRAM2 Write protection page 25 (0x2000E400 - 0x2000E7FF) */
9272 …E26_Msk /*!< SRAM2 Write protection page 26 (0x2000E800 - 0x2000EBFF) */
9275 …E27_Msk /*!< SRAM2 Write protection page 27 (0x2000EC00 - 0x2000EFFF) */
9278 …E28_Msk /*!< SRAM2 Write protection page 28 (0x2000F000 - 0x2000F3FF) */
9281 …E29_Msk /*!< SRAM2 Write protection page 29 (0x2000F400 - 0x2000F7FF) */
9284 …E30_Msk /*!< SRAM2 Write protection page 30 (0x2000F800 - 0x2000FBFF) */
9287 …E31_Msk /*!< SRAM2 Write protection page 31 (0x2000FC00 - 0x2000FFFF) */
9294 …r SYSCFG_IMR1 register (Interrupt masks control and status register on CPU1 - part 1) ************…
9335 …r SYSCFG_IMR2 register (Interrupt masks control and status register on CPU1 - part 2) ************…
9343 …SYSCFG_C2IMR1 register (Interrupt masks control and status register on CPU2 - part 1) ************…
9426 …SYSCFG_C2IMR2 register (Interrupt masks control and status register on CPU2 - part 2) ************…
9486 /* Inter-integrated Circuit Interface (I2C) */
9560 #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressi…
9563 #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address …
9592 …AR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
9754 #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive d…
9759 #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit …
9762 /* Inter-Processor Communication Controller (IPCC) */
10159 #define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-B…
10175 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-b…
10340 … TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selectio…
10346 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload prel…
10598 …R1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
10623 …R1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
10640 /*----------------------------------------------------------------------------*/
10678 …R2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
10703 …R2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
10720 /*----------------------------------------------------------------------------*/
10752 …R3_OC5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */
10771 …R3_OC6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 6 Fast enable */
10863 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<Actual auto-relo…
10912 … TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
10930 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Select…
10933 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Select…
10964 …BDTR_BKDSRM TIM_BDTR_BKDSRM_Msk /*!<Break disarming/re-arming */
10967 …DTR_BK2DSRM TIM_BDTR_BK2DSRM_Msk /*!<Break2 disarming/re-arming */
11410 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
11492 /******************** UART Instances : Half-Duplex mode **********************/
11501 /******************** UART Instances : Wake-up from Stop mode **********************/