| /hal_espressif-latest/components/soc/esp32/include/soc/ |
| D | efuse_defs.h | 15 /* Write disable bits */
16 #define EFUSE_WR_DIS_RD_DIS (1<<0) /*< disable writing read disable reg */
17 #define EFUSE_WR_DIS_WR_DIS (1<<1) /*< disable writing write disable reg */
19 #define EFUSE_WR_DIS_MAC_SPI_CONFIG_HD (1<<3) /*< disable writing MAC & SPI config hd efuses */
20 #define EFUSE_WR_DIS_XPD_SDIO (1<<5) /*< disable writing SDIO config efuses */
21 #define EFUSE_WR_DIS_SPI_PAD_CONFIG (1<<6) /*< disable writing SPI_PAD_CONFIG efuses */
22 #define EFUSE_WR_DIS_BLK1 (1<<7) /*< disable writing BLK1 efuses */
23 #define EFUSE_WR_DIS_BLK2 (1<<8) /*< disable writing BLK2 efuses */
24 #define EFUSE_WR_DIS_BLK3 (1<<9) /*< disable writing BLK3 efuses */
25 #define EFUSE_WR_DIS_FLASH_CRYPT_CODING_SCHEME (1<<10) /*< disable writing FLASH_CRYPT_CONFIG and C…
[all …]
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| D | spi_struct.h | 27 …ggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
28 …ggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
29 …ggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
30 …nto high performance mode. The bit will be cleared once the operation done.1: enable 0: disable.*/
31 …and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable.*/
32 …ggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
33 …ggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
34 …ggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
35 …ggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
36 …gered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable.*/
[all …]
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| /hal_espressif-latest/tools/esptool_py/docs/en/espefuse/inc/ |
| D | summary_ESP32-S3.rst | 12 …WR_DIS (BLOCK0) Disable programming of individual eFuses …
13 …RD_DIS (BLOCK0) Disable reading from BlOCK4-10 …
14 …DIS_ICACHE (BLOCK0) Set this bit to disable Icache …
15 …DIS_DCACHE (BLOCK0) Set this bit to disable Dcache …
16 …DIS_TWAI (BLOCK0) Set this bit to disable CAN function …
17 …DIS_APP_CPU (BLOCK0) Disable app cpu …
18 …DIS_DIRECT_BOOT (BLOCK0) Disable direct boot mode …
54 …SOFT_DIS_JTAG (BLOCK0) Set these bits to disable JTAG in the soft way …
55 … d number 1 means disable ). JTAG can be enabled in
57 …DIS_PAD_JTAG (BLOCK0) Set this bit to disable JTAG in the hard way. J…
[all …]
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| D | summary_ESP32-C3.rst | 30 …WR_DIS (BLOCK0) Disable programming of individual eFuses …
31 …RD_DIS (BLOCK0) Disable reading from BlOCK4-10 …
32 …DIS_ICACHE (BLOCK0) Set this bit to disable Icache …
33 …DIS_TWAI (BLOCK0) Set this bit to disable CAN function …
34 …DIS_DIRECT_BOOT (BLOCK0) Disable direct boot mode …
65 …SOFT_DIS_JTAG (BLOCK0) Set these bits to disable JTAG in the soft way …
66 … d number 1 means disable ). JTAG can be enabled in
68 …DIS_PAD_JTAG (BLOCK0) Set this bit to disable JTAG in the hard way. J…
78 …DIS_DOWNLOAD_ICACHE (BLOCK0) Set this bit to disable Icache in download mode…
80 …DIS_FORCE_DOWNLOAD (BLOCK0) Set this bit to disable the function that force…
[all …]
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| D | summary_ESP32-C2.rst | 12 …WR_DIS (BLOCK0) Disable programming of individual eFuses …
13 …RD_DIS (BLOCK0) Disable reading from BlOCK3 …
15 …DIS_DIRECT_BOOT (BLOCK0) This bit set means disable direct_boot mode …
35 …DIS_PAD_JTAG (BLOCK0) Set this bit to disable pad jtag …
45 …DIS_DOWNLOAD_ICACHE (BLOCK0) The bit be set to disable icache in download mo…
46 …DIS_DOWNLOAD_MANUAL_ENCRYPT (BLOCK0) The bit be set to disable manual encryption …
47 …K0) Enables flash encryption when 1 or 3 bits are set = Disable R/W (0b000)
50 …DIS_DOWNLOAD_MODE (BLOCK0) Set this bit to disable download mode (boot_mod…
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| /hal_espressif-latest/components/soc/esp32c3/include/soc/ |
| D | spi_mem_struct.h | 19 …bined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable.*/
20 …ggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
21 …nto high performance mode. The bit will be cleared once the operation done.1: enable 0: disable.*/
22 …and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable.*/
23 …ggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
24 …ggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
25 …ggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
26 …ggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
27 …gered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable.*/
28 …ggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
[all …]
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| D | i2s_struct.h | 78 uint32_t rx_tdm_en: 1; /*1: Enable I2S TDM Rx mode . 0: Disable.*/
79 uint32_t rx_pdm_en: 1; /*1: Enable I2S PDM Rx mode . 0: Disable.*/
98 …uint32_t tx_stop_en: 1; /*Set this bit to stop disable output BCK signal and WS s…
104 uint32_t tx_tdm_en: 1; /*1: Enable I2S TDM Tx mode . 0: Disable.*/
105 uint32_t tx_pdm_en: 1; /*1: Enable I2S PDM Tx mode . 0: Disable.*/
212 …; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just input 0 in …
213 …; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just input 0 in …
214 …; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just input 0 in …
215 …; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just input 0 in …
216 …; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just input 0 in …
[all …]
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| /hal_espressif-latest/components/soc/esp32s2/include/soc/ |
| D | spi_mem_struct.h | 18 …bined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable.*/
19 …ggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
20 …nto high performance mode. The bit will be cleared once the operation done.1: enable 0: disable.*/
21 …and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable.*/
22 …ggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
23 …ggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
24 …ggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
25 …ggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
26 …gered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable.*/
27 …ggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
[all …]
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| /hal_espressif-latest/components/soc/esp32s3/include/soc/ |
| D | i2s_struct.h | 78 … uint32_t rx_tdm_en : 1; /*1: Enable I2S TDM Rx mode . 0: Disable.*/
79 … uint32_t rx_pdm_en : 1; /*1: Enable I2S PDM Rx mode . 0: Disable.*/
80 … uint32_t rx_pdm2pcm_en : 1; /*1: Enable PDM2PCM RX mode. 0: DIsable.*/
100 …uint32_t tx_stop_en : 1; /*Set this bit to stop disable output BCK signal a…
106 … uint32_t tx_tdm_en : 1; /*1: Enable I2S TDM Tx mode . 0: Disable.*/
107 … uint32_t tx_pdm_en : 1; /*1: Enable I2S PDM Tx mode . 0: Disable.*/
214 …; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just input 0 in …
215 …; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just input 0 in …
216 …; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just input 0 in …
217 …; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just input 0 in …
[all …]
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| /hal_espressif-latest/components/bootloader_support/src/esp32/ |
| D | secure_boot_secure_features.c | 28 ESP_LOGI(TAG, "Disable JTAG..."); in esp_secure_boot_enable_secure_features()
35 ESP_LOGI(TAG, "Disable ROM BASIC interpreter fallback..."); in esp_secure_boot_enable_secure_features()
53 ESP_LOGI(TAG, "Disable JTAG..."); in esp_secure_boot_enable_secure_features()
56 ESP_LOGE(TAG, "Disable JTAG...failed."); in esp_secure_boot_enable_secure_features()
64 ESP_LOGI(TAG, "Disable ROM BASIC interpreter fallback..."); in esp_secure_boot_enable_secure_features()
67 ESP_LOGE(TAG, "Disable ROM BASIC interpreter fallback...failed."); in esp_secure_boot_enable_secure_features()
75 ESP_LOGI(TAG, "Disable ROM Download mode..."); in esp_secure_boot_enable_secure_features()
78 ESP_LOGE(TAG, "Could not disable ROM Download mode..."); in esp_secure_boot_enable_secure_features()
88 …/* If flash encryption is not enabled yet then don't read-disable efuses yet, do it later in the b… in esp_secure_boot_enable_secure_features()
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| /hal_espressif-latest/components/soc/esp32c2/include/soc/ |
| D | spi_mem_struct.h | 20 …ined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable. */
21 …gered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
22 …to high performance mode. The bit will be cleared once the operation done.1: enable 0: disable. */
23 …nd obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable. */
24 …gered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
25 …gered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
26 …gered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
27 …gered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
28 …ered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable. */
29 …gered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
[all …]
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| /hal_espressif-latest/components/hal/esp32/include/hal/ |
| D | rwdt_ll.h | 55 * @brief Disable the RWDT
58 * @note This function does not disable the flashboot mode. Therefore, given that
111 * @brief Disable a particular stage of the RWDT
114 * @param stage Which stage to disable
137 * @brief Enable or disable RWDT edge interrupt
148 * @brief Enable or disable RWDT level interrupt
181 * @brief Enable/Disable the RWDT flashboot mode.
184 * @param enable True to enable RWDT flashboot mode, false to disable RWDT flashboot mode.
196 * @brief Enable/Disable the CPU0 to be reset on WDT_STAGE_ACTION_RESET_CPU
199 * @param enable True to enable CPU0 to be reset, false to disable.
[all …]
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| /hal_espressif-latest/components/hal/include/hal/ |
| D | apm_hal.h | 45 * @param enable Flag for HP clock auto gating enable/disable
50 * @brief enable/disable HP Region access permission filter
53 * @param enable Flag for Region access filter enable/disable
58 * @brief enable/disable HP access path(M[0:3])
61 * @param enable Flag for HP M path filter enable/disable
98 * @param enable Flag for access path interrupt enable/disable
105 * @param enable Flag for HP clock auto gating enable/disable
123 * Disable: tee_reg/apm_reg/hp_system_reg will not only be reset by power-reset,
128 * @param enable Flag for event bypass enable/disable
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| /hal_espressif-latest/components/hal/esp32s2/include/hal/ |
| D | rwdt_ll.h | 57 * @brief Disable the RWDT
60 * @note This function does not disable the flashboot mode. Therefore, given that
124 * @brief Disable a particular stage of the RWDT
127 * @param stage Which stage to disable
172 * @brief Enable/Disable the RWDT flashboot mode.
175 * @param enable True to enable RWDT flashboot mode, false to disable RWDT flashboot mode.
187 * @brief Enable/Disable the CPU0 to be reset on WDT_STAGE_ACTION_RESET_CPU
190 * @param enable True to enable CPU0 to be reset, false to disable.
198 * @brief Enable/Disable the CPU1 to be reset on WDT_STAGE_ACTION_RESET_CPU
201 * @param enable True to enable CPU1 to be reset, false to disable.
[all …]
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| /hal_espressif-latest/components/hal/esp32s3/include/hal/ |
| D | rwdt_ll.h | 77 * @brief Disable the RWDT
80 * @note This function does not disable the flashboot mode. Therefore, given that
143 * @brief Disable a particular stage of the RWDT
146 * @param stage Which stage to disable
191 * @brief Enable/Disable the RWDT flashboot mode.
194 * @param enable True to enable RWDT flashboot mode, false to disable RWDT flashboot mode.
206 * @brief Enable/Disable the CPU0 to be reset on WDT_STAGE_ACTION_RESET_CPU
209 * @param enable True to enable CPU0 to be reset, false to disable.
217 * @brief Enable/Disable the CPU1 to be reset on WDT_STAGE_ACTION_RESET_CPU
220 * @param enable True to enable CPU1 to be reset, false to disable.
[all …]
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| /hal_espressif-latest/components/hal/esp32c6/include/hal/ |
| D | lpwdt_ll.h | 75 * @brief Disable the RWDT
78 * @note This function does not disable the flashboot mode. Therefore, given that
142 * @brief Disable a particular stage of the RWDT
145 * @param stage Which stage to disable
190 * @brief Enable/Disable the RWDT flashboot mode.
193 * @param enable True to enable RWDT flashboot mode, false to disable RWDT flashboot mode.
205 * @brief Enable/Disable the CPU0 to be reset on WDT_STAGE_ACTION_RESET_CPU
208 * @param enable True to enable CPU0 to be reset, false to disable.
216 * @brief Enable/Disable the CPU1 to be reset on WDT_STAGE_ACTION_RESET_CPU
219 * @param enable True to enable CPU1 to be reset, false to disable.
[all …]
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| /hal_espressif-latest/components/hal/esp32c3/include/hal/ |
| D | rwdt_ll.h | 57 * @brief Disable the RWDT
60 * @note This function does not disable the flashboot mode. Therefore, given that
124 * @brief Disable a particular stage of the RWDT
127 * @param stage Which stage to disable
172 * @brief Enable/Disable the RWDT flashboot mode.
175 * @param enable True to enable RWDT flashboot mode, false to disable RWDT flashboot mode.
187 * @brief Enable/Disable the CPU0 to be reset on WDT_STAGE_ACTION_RESET_CPU
190 * @param enable True to enable CPU0 to be reset, false to disable.
198 * @brief Enable/Disable the CPU1 to be reset on WDT_STAGE_ACTION_RESET_CPU
201 * @param enable True to enable CPU1 to be reset, false to disable.
[all …]
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| /hal_espressif-latest/components/hal/esp32h2/include/hal/ |
| D | lpwdt_ll.h | 74 * @brief Disable the RWDT
77 * @note This function does not disable the flashboot mode. Therefore, given that
141 * @brief Disable a particular stage of the RWDT
144 * @param stage Which stage to disable
189 * @brief Enable/Disable the RWDT flashboot mode.
192 * @param enable True to enable RWDT flashboot mode, false to disable RWDT flashboot mode.
204 * @brief Enable/Disable the CPU0 to be reset on WDT_STAGE_ACTION_RESET_CPU
207 * @param enable True to enable CPU0 to be reset, false to disable.
215 * @brief Enable/Disable the CPU1 to be reset on WDT_STAGE_ACTION_RESET_CPU
218 * @param enable True to enable CPU1 to be reset, false to disable.
[all …]
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| /hal_espressif-latest/components/hal/esp32c2/include/hal/ |
| D | rwdt_ll.h | 55 * @brief Disable the RWDT
58 * @note This function does not disable the flashboot mode. Therefore, given that
122 * @brief Disable a particular stage of the RWDT
125 * @param stage Which stage to disable
170 * @brief Enable/Disable the RWDT flashboot mode.
173 * @param enable True to enable RWDT flashboot mode, false to disable RWDT flashboot mode.
185 * @brief Enable/Disable the CPU0 to be reset on WDT_STAGE_ACTION_RESET_CPU
188 * @param enable True to enable CPU0 to be reset, false to disable.
196 * @brief Enable/Disable the RWDT pause during sleep functionality
199 * @param enable True to enable, false to disable.
[all …]
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| /hal_espressif-latest/components/efuse/esp32s3/ |
| D | esp_efuse_table.csv | 14 WR_DIS, EFUSE_BLK0, 0, 32, [] Disable programming of in…
125 RD_DIS, EFUSE_BLK0, 32, 7, [] Disable reading from BlOC…
133 DIS_ICACHE, EFUSE_BLK0, 40, 1, [] Set this bit to disable I…
134 DIS_DCACHE, EFUSE_BLK0, 41, 1, [] Set this bit to disable D…
135 DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 42, 1, [] Set this bit to disable I…
136 DIS_DOWNLOAD_DCACHE, EFUSE_BLK0, 43, 1, [] Set this bit to disable D…
137 DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 44, 1, [] Set this bit to disable t…
138 … EFUSE_BLK0, 45, 1, [DIS_USB] Set this bit to disable USB function
139 … EFUSE_BLK0, 46, 1, [DIS_CAN] Set this bit to disable CAN function
140 DIS_APP_CPU, EFUSE_BLK0, 47, 1, [] Disable app cpu
[all …]
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| /hal_espressif-latest/components/efuse/esp32c3/ |
| D | esp_efuse_table.csv | 14 WR_DIS, EFUSE_BLK0, 0, 32, [] Disable programming of in…
99 RD_DIS, EFUSE_BLK0, 32, 7, [] Disable reading from BlOC…
107 DIS_ICACHE, EFUSE_BLK0, 40, 1, [] Set this bit to disable I…
108 DIS_USB_JTAG, EFUSE_BLK0, 41, 1, [] Set this bit to disable f…
109 DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 42, 1, [] Set this bit to disable I…
110 … EFUSE_BLK0, 43, 1, [DIS_USB_DEVICE] USB-Serial-JTAG {0: "Enable"; 1: "Disable"}
111 DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 44, 1, [] Set this bit to disable t…
112 … EFUSE_BLK0, 46, 1, [DIS_CAN] Set this bit to disable CAN function
114 … EFUSE_BLK0, 48, 3, [] Set these bits to disable JTAG in the soft way (odd number 1 means d…
115 DIS_PAD_JTAG, EFUSE_BLK0, 51, 1, [] Set this bit to disable J…
[all …]
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| /hal_espressif-latest/components/esp_rom/patches/ |
| D | esp_rom_wdt.c | 39 //Disable RTC WDT, all stages, and all interrupts. in wdt_hal_init()
46 //Enable or disable level interrupt. Edge interrupt is always disabled. in wdt_hal_init()
50 //Enable or disable chip reset on timeout, and length of chip reset signal in wdt_hal_init()
69 //Disable WDT and stages. in wdt_hal_init()
76 //Enable or disable level interrupt. Edge interrupt is always disabled. in wdt_hal_init()
99 //Disable WDT and clear any interrupts in wdt_hal_deinit()
109 //Disable WDT and clear/disable any interrupts in wdt_hal_deinit()
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| /hal_espressif-latest/components/esp_hw_support/include/esp_private/ |
| D | esp_modem_clock.h | 49 * @brief Disable the clock of modem module
53 * on the clock source. Each disable ops will minus 1 to the ref_cnt of the clock
55 * from 1 to 0 will the clock disable be actually configured.
87 * @brief Disable modem clock domain clock gate to ungate it's output
109 * @brief Disable lowpower clock source selection
115 * @brief Disable all modem module's lowpower clock source selection
125 … Enable clock registers which shared by both modem and ADC. Need a ref count to enable/disable them
127 * @param enable true: enable; false: disable
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| /hal_espressif-latest/components/soc/esp32c6/include/soc/ |
| D | spi_mem_struct.h | 19 …ined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable. */
20 …gered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
21 …to high performance mode. The bit will be cleared once the operation done.1: enable 0: disable. */
22 …nd obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable. */
23 …gered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
24 …gered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
25 …gered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
26 …gered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
27 …ered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable. */
28 …gered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
[all …]
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| /hal_espressif-latest/components/soc/esp32h2/include/soc/ |
| D | spi_mem_struct.h | 20 …ined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable. */
21 …gered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
22 …to high performance mode. The bit will be cleared once the operation done.1: enable 0: disable. */
23 …nd obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable. */
24 …gered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
25 …gered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
26 …gered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
27 …gered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
28 …ered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable. */
29 …gered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
[all …]
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