1.. code-block:: none 2 3 > espefuse.py -p PORT summary 4 5 Connecting.... 6 Detecting chip type... ESP32-S3 7 8 === Run "summary" command === 9 EFUSE_NAME (Block) Description = [Meaningful Value] [Readable/Writeable] (Hex Value) 10 ---------------------------------------------------------------------------------------- 11 Config fuses: 12 WR_DIS (BLOCK0) Disable programming of individual eFuses = 0 R/W (0x00000000) 13 RD_DIS (BLOCK0) Disable reading from BlOCK4-10 = 0 R/W (0b0000000) 14 DIS_ICACHE (BLOCK0) Set this bit to disable Icache = False R/W (0b0) 15 DIS_DCACHE (BLOCK0) Set this bit to disable Dcache = False R/W (0b0) 16 DIS_TWAI (BLOCK0) Set this bit to disable CAN function = False R/W (0b0) 17 DIS_APP_CPU (BLOCK0) Disable app cpu = False R/W (0b0) 18 DIS_DIRECT_BOOT (BLOCK0) Disable direct boot mode = False R/W (0b0) 19 UART_PRINT_CONTROL (BLOCK0) Set the default UART boot message output mode = Enable R/W (0b00) 20 PIN_POWER_SELECTION (BLOCK0) Set default power supply for GPIO33-GPIO37; set wh = VDD3P3_CPU R/W (0b0) 21 en SPI flash is initialized 22 BLOCK_USR_DATA (BLOCK3) User data 23 = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W 24 BLOCK_SYS_DATA2 (BLOCK10) System data part 2 (reserved) 25 = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W 26 27 Flash fuses: 28 FLASH_TPUW (BLOCK0) Configures flash waiting time after power-up; in u = 0 R/W (0x0) 29 nit of ms. If the value is less than 15; the waiti 30 ng time is the configurable value. Otherwise; the 31 waiting time is twice the configurable value 32 FLASH_ECC_MODE (BLOCK0) Flash ECC mode in ROM = 16to18 byte R/W (0b0) 33 FLASH_TYPE (BLOCK0) SPI flash type = 4 data lines R/W (0b0) 34 FLASH_PAGE_SIZE (BLOCK0) Set Flash page size = 0 R/W (0b00) 35 FLASH_ECC_EN (BLOCK0) Set 1 to enable ECC for flash boot = False R/W (0b0) 36 FORCE_SEND_RESUME (BLOCK0) Set this bit to force ROM code to send a resume co = False R/W (0b0) 37 mmand during SPI boot 38 39 Identity fuses: 40 DISABLE_WAFER_VERSION_MAJOR (BLOCK0) Disables check of wafer version major = False R/W (0b0) 41 DISABLE_BLK_VERSION_MAJOR (BLOCK0) Disables check of blk version major = False R/W (0b0) 42 WAFER_VERSION_MINOR_LO (BLOCK1) WAFER_VERSION_MINOR least significant bits = 0 R/W (0b000) 43 PKG_VERSION (BLOCK1) Package version = 0 R/W (0b000) 44 BLK_VERSION_MINOR (BLOCK1) BLK_VERSION_MINOR = 0 R/W (0b000) 45 WAFER_VERSION_MINOR_HI (BLOCK1) WAFER_VERSION_MINOR most significant bit = False R/W (0b0) 46 WAFER_VERSION_MAJOR (BLOCK1) WAFER_VERSION_MAJOR = 0 R/W (0b00) 47 OPTIONAL_UNIQUE_ID (BLOCK2) Optional unique 128-bit ID 48 = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W 49 BLK_VERSION_MAJOR (BLOCK2) BLK_VERSION_MAJOR of BLOCK2 = No calib R/W (0b00) 50 WAFER_VERSION_MINOR (BLOCK0) calc WAFER VERSION MINOR = WAFER_VERSION_MINOR_HI = 0 R/W (0x0) 51 << 3 + WAFER_VERSION_MINOR_LO (read only) 52 53 Jtag fuses: 54 SOFT_DIS_JTAG (BLOCK0) Set these bits to disable JTAG in the soft way (od = 0 R/W (0b000) 55 d number 1 means disable ). JTAG can be enabled in 56 HMAC module 57 DIS_PAD_JTAG (BLOCK0) Set this bit to disable JTAG in the hard way. JTAG = False R/W (0b0) 58 is disabled permanently 59 STRAP_JTAG_SEL (BLOCK0) Set this bit to enable selection between usb_to_jt = False R/W (0b0) 60 ag and pad_to_jtag through strapping gpio10 when b 61 oth reg_dis_usb_jtag and reg_dis_pad_jtag are equa 62 l to 0 63 64 Mac fuses: 65 MAC (BLOCK1) MAC address 66 = 7c:df:a1:e0:00:58 (OK) R/W 67 CUSTOM_MAC (BLOCK3) Custom MAC 68 = 00:00:00:00:00:00 (OK) R/W 69 70 Security fuses: 71 DIS_DOWNLOAD_ICACHE (BLOCK0) Set this bit to disable Icache in download mode (b = False R/W (0b0) 72 oot_mode[3:0] is 0; 1; 2; 3; 6; 7) 73 DIS_DOWNLOAD_DCACHE (BLOCK0) Set this bit to disable Dcache in download mode ( = False R/W (0b0) 74 boot_mode[3:0] is 0; 1; 2; 3; 6; 7) 75 DIS_FORCE_DOWNLOAD (BLOCK0) Set this bit to disable the function that forces c = False R/W (0b0) 76 hip into download mode 77 DIS_DOWNLOAD_MANUAL_ENCRYPT (BLOCK0) Set this bit to disable flash encryption when in d = False R/W (0b0) 78 ownload boot modes 79 SPI_BOOT_CRYPT_CNT (BLOCK0) Enables flash encryption when 1 or 3 bits are set = Disable R/W (0b000) 80 and disabled otherwise 81 SECURE_BOOT_KEY_REVOKE0 (BLOCK0) Revoke 1st secure boot key = False R/W (0b0) 82 SECURE_BOOT_KEY_REVOKE1 (BLOCK0) Revoke 2nd secure boot key = False R/W (0b0) 83 SECURE_BOOT_KEY_REVOKE2 (BLOCK0) Revoke 3rd secure boot key = False R/W (0b0) 84 KEY_PURPOSE_0 (BLOCK0) Purpose of Key0 = USER R/W (0x0) 85 KEY_PURPOSE_1 (BLOCK0) Purpose of Key1 = USER R/W (0x0) 86 KEY_PURPOSE_2 (BLOCK0) Purpose of Key2 = USER R/W (0x0) 87 KEY_PURPOSE_3 (BLOCK0) Purpose of Key3 = USER R/W (0x0) 88 KEY_PURPOSE_4 (BLOCK0) Purpose of Key4 = USER R/W (0x0) 89 KEY_PURPOSE_5 (BLOCK0) Purpose of Key5 = USER R/W (0x0) 90 SECURE_BOOT_EN (BLOCK0) Set this bit to enable secure boot = False R/W (0b0) 91 SECURE_BOOT_AGGRESSIVE_REVOKE (BLOCK0) Set this bit to enable revoking aggressive secure = False R/W (0b0) 92 boot 93 DIS_DOWNLOAD_MODE (BLOCK0) Set this bit to disable download mode (boot_mode[3 = False R/W (0b0) 94 :0] = 0; 1; 2; 3; 6; 7) 95 ENABLE_SECURITY_DOWNLOAD (BLOCK0) Set this bit to enable secure UART download mode = False R/W (0b0) 96 SECURE_VERSION (BLOCK0) Secure version (used by ESP-IDF anti-rollback feat = 0 R/W (0x0000) 97 ure) 98 BLOCK_KEY0 (BLOCK4) 99 Purpose: USER 100 Key0 or user data 101 = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W 102 BLOCK_KEY1 (BLOCK5) 103 Purpose: USER 104 Key1 or user data 105 = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W 106 BLOCK_KEY2 (BLOCK6) 107 Purpose: USER 108 Key2 or user data 109 = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W 110 BLOCK_KEY3 (BLOCK7) 111 Purpose: USER 112 Key3 or user data 113 = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W 114 BLOCK_KEY4 (BLOCK8) 115 Purpose: USER 116 Key4 or user data 117 = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W 118 BLOCK_KEY5 (BLOCK9) 119 Purpose: USER 120 Key5 or user data 121 = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W 122 123 Spi Pad fuses: 124 SPI_PAD_CONFIG_CLK (BLOCK1) SPI_PAD_configure CLK = 0 R/W (0b000000) 125 SPI_PAD_CONFIG_Q (BLOCK1) SPI_PAD_configure Q(D1) = 0 R/W (0b000000) 126 SPI_PAD_CONFIG_D (BLOCK1) SPI_PAD_configure D(D0) = 0 R/W (0b000000) 127 SPI_PAD_CONFIG_CS (BLOCK1) SPI_PAD_configure CS = 0 R/W (0b000000) 128 SPI_PAD_CONFIG_HD (BLOCK1) SPI_PAD_configure HD(D3) = 0 R/W (0b000000) 129 SPI_PAD_CONFIG_WP (BLOCK1) SPI_PAD_configure WP(D2) = 0 R/W (0b000000) 130 SPI_PAD_CONFIG_DQS (BLOCK1) SPI_PAD_configure DQS = 0 R/W (0b000000) 131 SPI_PAD_CONFIG_D4 (BLOCK1) SPI_PAD_configure D4 = 0 R/W (0b000000) 132 SPI_PAD_CONFIG_D5 (BLOCK1) SPI_PAD_configure D5 = 0 R/W (0b000000) 133 SPI_PAD_CONFIG_D6 (BLOCK1) SPI_PAD_configure D6 = 0 R/W (0b000000) 134 SPI_PAD_CONFIG_D7 (BLOCK1) SPI_PAD_configure D7 = 0 R/W (0b000000) 135 136 Usb fuses: 137 DIS_USB_OTG (BLOCK0) Set this bit to disable USB function = False R/W (0b0) 138 USB_EXCHG_PINS (BLOCK0) Set this bit to exchange USB D+ and D- pins = False R/W (0b0) 139 USB_EXT_PHY_ENABLE (BLOCK0) Set this bit to enable external PHY = False R/W (0b0) 140 DIS_USB_JTAG (BLOCK0) Set this bit to disable function of usb switch to = False R/W (0b0) 141 jtag in module of usb device 142 DIS_USB_SERIAL_JTAG (BLOCK0) Set this bit to disable usb device = False R/W (0b0) 143 USB_PHY_SEL (BLOCK0) This bit is used to switch internal PHY and extern 144 = internal PHY is assigned to USB Device while external PHY is assigned to USB OTG R/W (0b0) 145 al PHY for USB OTG and USB Device 146 DIS_USB_SERIAL_JTAG_ROM_PRINT (BLOCK0) USB printing = Enable R/W (0b0) 147 DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE (BLOCK0) Set this bit to disable UART download mode through = False R/W (0b0) 148 USB 149 DIS_USB_OTG_DOWNLOAD_MODE (BLOCK0) Set this bit to disable download through USB-OTG = False R/W (0b0) 150 151 Vdd fuses: 152 VDD_SPI_XPD (BLOCK0) SPI regulator power up signal = False R/W (0b0) 153 VDD_SPI_TIEH (BLOCK0) If VDD_SPI_FORCE is 1; determines VDD_SPI voltage 154 = VDD_SPI connects to 1.8 V LDO R/W (0b0) 155 VDD_SPI_FORCE (BLOCK0) Set this bit and force to use the configuration of = False R/W (0b0) 156 eFuse to configure VDD_SPI 157 158 Wdt fuses: 159 WDT_DELAY_SEL (BLOCK0) RTC watchdog timeout threshold; in unit of slow cl = 40000 R/W (0b00) 160 ock cycle 161 162 Flash voltage (VDD_SPI) determined by GPIO45 on reset (GPIO45=High: VDD_SPI pin is powered from internal 1.8V LDO 163 GPIO45=Low or NC: VDD_SPI pin is powered directly from VDD3P3_RTC_IO via resistor Rspi. Typically this voltage is 3.3 V). 164
