1 /*
2  * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 #pragma once
7 
8 #include <stdint.h>
9 
10 #ifdef __cplusplus
11 extern "C" {
12 #endif
13 
14 typedef volatile struct spi_mem_dev_s{
15     union {
16         struct {
17             uint32_t mst_st                        :    4;  /*The current status of SPI1 master FSM.*/
18             uint32_t slv_st                        :    4;  /*The current status of SPI1 slave FSM: mspi_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state.*/
19             uint32_t reserved8                     :    9;  /*reserved*/
20             uint32_t flash_pe                      :    1;  /*In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable. */
21             uint32_t usr                           :    1;  /*User define command enable.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
22             uint32_t flash_hpm                     :    1;  /*Drive Flash into high performance mode.  The bit will be cleared once the operation done.1: enable 0: disable. */
23             uint32_t flash_res                     :    1;  /*This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable. */
24             uint32_t flash_dp                      :    1;  /*Drive Flash into power down.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
25             uint32_t flash_ce                      :    1;  /*Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
26             uint32_t flash_be                      :    1;  /*Block erase enable(32KB) .  Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
27             uint32_t flash_se                      :    1;  /*Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
28             uint32_t flash_pp                      :    1;  /*Page program enable(1 byte ~256 bytes data to be programmed). Page program operation  will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable. */
29             uint32_t flash_wrsr                    :    1;  /*Write status register enable.   Write status operation  will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
30             uint32_t flash_rdsr                    :    1;  /*Read status register-1.  Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
31             uint32_t flash_rdid                    :    1;  /*Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */
32             uint32_t flash_wrdi                    :    1;  /*Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */
33             uint32_t flash_wren                    :    1;  /*Write flash enable.  Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */
34             uint32_t flash_read                    :    1;  /*Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */
35         };
36         uint32_t val;
37     } cmd;
38     uint32_t addr;
39     union {
40         struct {
41             uint32_t reserved0                     :    3;  /*reserved*/
42             uint32_t fdummy_out                    :    1;  /*In the dummy phase the signal level of spi is output by the spi controller.*/
43             uint32_t reserved4                     :    3;  /*reserved*/
44             uint32_t fcmd_dual                     :    1;  /*Apply 2 signals during command phase 1:enable 0: disable*/
45             uint32_t fcmd_quad                     :    1;  /*Apply 4 signals during command phase 1:enable 0: disable*/
46             uint32_t reserved9                     :    1;  /*reserved*/
47             uint32_t fcs_crc_en                    :    1;  /*For SPI1,  initialize crc32 module before writing encrypted data to flash. Active low.*/
48             uint32_t tx_crc_en                     :    1;  /*For SPI1,  enable crc32 when writing encrypted data to flash. 1: enable 0:disable*/
49             uint32_t reserved12                    :    1;  /*reserved*/
50             uint32_t fastrd_mode                   :    1;  /*This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QOUT AND SPI_MEM_FREAD_DOUT. 1: enable 0: disable. */
51             uint32_t fread_dual                    :    1;  /*In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. */
52             uint32_t resandres                     :    1;  /*The Device ID is read out to SPI_MEM_RD_STATUS register,  this bit combine with spi_mem_flash_res bit. 1: enable 0: disable. */
53             uint32_t reserved16                    :    2;  /*reserved*/
54             uint32_t q_pol                         :    1;  /*The bit is used to set MISO line polarity, 1: high 0, low*/
55             uint32_t d_pol                         :    1;  /*The bit is used to set MOSI line polarity, 1: high 0, low*/
56             uint32_t fread_quad                    :    1;  /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable. */
57             uint32_t wp                            :    1;  /*Write protect signal output when SPI is idle.  1: output high, 0: output low. */
58             uint32_t wrsr_2b                       :    1;  /*two bytes data will be written to status register when it is set. 1: enable 0: disable. */
59             uint32_t fread_dio                     :    1;  /*In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable. */
60             uint32_t fread_qio                     :    1;  /*In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable. */
61             uint32_t reserved25                    :    7;  /*reserved*/
62         };
63         uint32_t val;
64     } ctrl;
65     union {
66         struct {
67             uint32_t clk_mode                      :    2;  /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.*/
68             uint32_t cs_hold_dly_res               :    10;  /*After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) SPI_CLK cycles.*/
69             uint32_t reserved2                     :    18;  /*reserved*/
70             uint32_t rxfifo_rst                    :    1;  /*SPI0 RX FIFO reset signal.*/
71             uint32_t reserved31                    :    1;  /*reserved*/
72         };
73         uint32_t val;
74     } ctrl1;
75     union {
76         struct {
77             uint32_t cs_setup_time                 :    5;  /*(cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit.*/
78             uint32_t cs_hold_time                  :    5;  /*Spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit.*/
79             uint32_t reserved10                    :    15;  /*reserved*/
80             uint32_t cs_hold_delay                 :    6;  /*These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.*/
81             uint32_t sync_reset                    :    1;  /*The FSM will be reset.*/
82         };
83         uint32_t val;
84     } ctrl2;
85     union {
86         struct {
87             uint32_t clkcnt_l                      :    8;  /*In the master mode it must be equal to spi_mem_clkcnt_N. */
88             uint32_t clkcnt_h                      :    8;  /*In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).*/
89             uint32_t clkcnt_n                      :    8;  /*In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)*/
90             uint32_t reserved24                    :    7;  /*In the master mode it is pre-divider of spi_mem_clk. */
91             uint32_t clk_equ_sysclk                :    1;  /*Set this bit in 1-division mode.*/
92         };
93         uint32_t val;
94     } clock;
95     union {
96         struct {
97             uint32_t reserved0                     :    6;  /*reserved*/
98             uint32_t cs_hold                       :    1;  /*spi cs keep low when spi is in  done  phase. 1: enable 0: disable. */
99             uint32_t cs_setup                      :    1;  /*spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable. */
100             uint32_t reserved8                     :    1;  /*reserved*/
101             uint32_t ck_out_edge                   :    1;  /*the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode. */
102             uint32_t reserved10                    :    2;  /*reserved*/
103             uint32_t fwrite_dual                   :    1;  /*In the write operations read-data phase apply 2 signals*/
104             uint32_t fwrite_quad                   :    1;  /*In the write operations read-data phase apply 4 signals*/
105             uint32_t fwrite_dio                    :    1;  /*In the write operations address phase and read-data phase apply 2 signals.*/
106             uint32_t fwrite_qio                    :    1;  /*In the write operations address phase and read-data phase apply 4 signals.*/
107             uint32_t reserved16                    :    8;  /*reserved*/
108             uint32_t usr_miso_highpart             :    1;  /*read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable. */
109             uint32_t usr_mosi_highpart             :    1;  /*write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable. */
110             uint32_t usr_dummy_idle                :    1;  /*spi clock is disable in dummy phase when the bit is enable.*/
111             uint32_t usr_mosi                      :    1;  /*This bit enable the write-data phase of an operation.*/
112             uint32_t usr_miso                      :    1;  /*This bit enable the read-data phase of an operation.*/
113             uint32_t usr_dummy                     :    1;  /*This bit enable the dummy phase of an operation.*/
114             uint32_t usr_addr                      :    1;  /*This bit enable the address phase of an operation.*/
115             uint32_t usr_command                   :    1;  /*This bit enable the command phase of an operation.*/
116         };
117         uint32_t val;
118     } user;
119     union {
120         struct {
121             uint32_t usr_dummy_cyclelen            :    6;  /*The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1).*/
122             uint32_t reserved6                     :    20;  /*reserved*/
123             uint32_t usr_addr_bitlen               :    6;  /*The length in bits of address phase. The register value shall be (bit_num-1).*/
124         };
125         uint32_t val;
126     } user1;
127     union {
128         struct {
129             uint32_t usr_command_value             :    16;  /*The value of  command.*/
130             uint32_t reserved16                    :    12;  /*reserved*/
131             uint32_t usr_command_bitlen            :    4;  /*The length in bits of command phase. The register value shall be (bit_num-1)*/
132         };
133         uint32_t val;
134     } user2;
135     union {
136         struct {
137             uint32_t usr_mosi_bit_len              :    10;  /*The length in bits of write-data. The register value shall be (bit_num-1).*/
138             uint32_t reserved10                    :    22;  /*reserved*/
139         };
140         uint32_t val;
141     } mosi_dlen;
142     union {
143         struct {
144             uint32_t usr_miso_bit_len              :    10;  /*The length in bits of  read-data. The register value shall be (bit_num-1).*/
145             uint32_t reserved10                    :    22;  /*reserved*/
146         };
147         uint32_t val;
148     } miso_dlen;
149     union {
150         struct {
151             uint32_t status                        :    16;  /*The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.*/
152             uint32_t wb_mode                       :    8;  /*Mode bits in the flash fast read mode  it is combined with spi_mem_fastrd_mode bit.*/
153             uint32_t reserved24                    :    8;  /*reserved*/
154         };
155         uint32_t val;
156     } rd_status;
157     uint32_t reserved_30;
158     union {
159         struct {
160             uint32_t cs0_dis                       :    1;  /*SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI device, such as flash, external RAM and so on.*/
161             uint32_t cs1_dis                       :    1;  /*SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI device, such as flash, external RAM and so on.*/
162             uint32_t reserved0                     :    1;  /*reserved*/
163             uint32_t mst_st_trans_end              :    1;  /*The bit is used to indicate the  spi0_mst_st controlled transmitting is done.*/
164             uint32_t mst_st_trans_end_en           :    1;  /*The bit is used to enable the interrupt of  spi0_mst_st controlled transmitting is done.*/
165             uint32_t slv_st_trans_end              :    1;  /*The bit is used to indicate the  spi0_slv_st controlled transmitting is done.*/
166             uint32_t slv_st_trans_end_en           :    1;  /*The bit is used to enable the interrupt of spi0_slv_st controlled transmitting is done.*/
167             uint32_t reserved7                     :    2;  /*reserved*/
168             uint32_t ck_idle_edge                  :    1;  /*1: spi clk line is high when idle     0: spi clk line is low when idle */
169             uint32_t cs_keep_active                :    1;  /*spi cs line keep low when the bit is set.*/
170             uint32_t reserved11                    :    21;  /*reserved*/
171         };
172         uint32_t val;
173     } misc;
174     uint32_t tx_crc;
175     union {
176         struct {
177             uint32_t req_en                        :    1;  /*For SPI0, Cache access enable, 1: enable, 0:disable.*/
178             uint32_t usr_addr_4byte                :    1;  /*For SPI0,  cache  read flash with 4 bytes address, 1: enable, 0:disable.*/
179             uint32_t flash_usr_cmd                 :    1;  /*For SPI0,  cache  read flash for user define command, 1: enable, 0:disable.*/
180             uint32_t fdin_dual                     :    1;  /*For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/
181             uint32_t fdout_dual                    :    1;  /*For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/
182             uint32_t faddr_dual                    :    1;  /*For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_dio.*/
183             uint32_t fdin_quad                     :    1;  /*For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.*/
184             uint32_t fdout_quad                    :    1;  /*For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.*/
185             uint32_t faddr_quad                    :    1;  /*For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.*/
186             uint32_t reserved9                     :    23;  /*reserved*/
187         };
188         uint32_t val;
189     } cache_fctrl;
190     uint32_t reserved_40;
191     uint32_t reserved_44;
192     uint32_t reserved_48;
193     uint32_t reserved_4c;
194     uint32_t reserved_50;
195     union {
196         struct {
197             uint32_t spi0_slv_st                   :    4;  /*The current status of SPI0 slave FSM: spi0_slv_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state.*/
198             uint32_t spi0_mst_st                   :    3;  /*The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:EM_CACHE_GRANT , 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent data is stored in SPI0 TX FIFO, 5: SPI0 write data state.*/
199             uint32_t cspi_lock_delay_time          :    5;  /*The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1.*/
200             uint32_t reserved12                    :    20;  /*reserved*/
201         };
202         uint32_t val;
203     } fsm;
204     uint32_t data_buf[16];
205     union {
206         struct {
207             uint32_t reserved0                     :    1;  /*reserved*/
208             uint32_t waiti_dummy                   :    1;  /*The dummy phase enable when wait flash idle (RDSR)*/
209             uint32_t waiti_cmd                     :    8;  /*The command to wait flash idle(RDSR).*/
210             uint32_t waiti_dummy_cyclelen          :    6;  /*The dummy cycle length when wait flash idle(RDSR).*/
211             uint32_t reserved16                    :    16;  /*reserved*/
212         };
213         uint32_t val;
214     } flash_waiti_ctrl;
215     union {
216         struct {
217             uint32_t flash_per                     :    1;  /*program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
218             uint32_t flash_pes                     :    1;  /*program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
219             uint32_t flash_per_wait_en             :    1;  /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase resume command is sent. 0: SPI1 does not wait after program erase resume command is sent. */
220             uint32_t flash_pes_wait_en             :    1;  /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase suspend command is sent. 0: SPI1 does not wait after program erase suspend command is sent. */
221             uint32_t pes_per_en                    :    1;  /*Set this bit to enable PES end triggers PER transfer option. If this bit is 0, application should send PER after PES is done.*/
222             uint32_t flash_pes_en                  :    1;  /*Set this bit to enable Auto-suspending function.*/
223             uint32_t pesr_end_msk                  :    16;  /*The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is status_in[15:0](only status_in[7:0] is valid when only one byte of data is read out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0].*/
224             uint32_t frd_sus_2b                    :    1;  /*1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0:  Read one byte when check flash SUS/SUS1/SUS2 status bit*/
225             uint32_t per_end_en                    :    1;  /*1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of flash. 0: Only need to check WIP is 0.*/
226             uint32_t pes_end_en                    :    1;  /*1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status of flash. 0: Only need to check WIP is 0.*/
227             uint32_t sus_timeout_cnt               :    7;  /*When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times, it will be treated as check pass.*/
228         };
229         uint32_t val;
230     } flash_sus_ctrl;
231     union {
232         struct {
233             uint32_t flash_per_command             :    8;  /*Program/Erase resume command.*/
234             uint32_t flash_pes_command             :    8;  /*Program/Erase suspend command.*/
235             uint32_t wait_pesr_command             :    16;  /*Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash.*/
236         };
237         uint32_t val;
238     } flash_sus_cmd;
239     union {
240         struct {
241             uint32_t flash_sus                     :    1;  /*The status of flash suspend, only used in SPI1.*/
242             uint32_t wait_pesr_cmd_2b              :    1;  /*1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit.*/
243             uint32_t flash_hpm_dly_128             :    1;  /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after HPM command is sent.*/
244             uint32_t flash_res_dly_128             :    1;  /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent.*/
245             uint32_t flash_dp_dly_128              :    1;  /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent.*/
246             uint32_t flash_per_dly_128             :    1;  /*Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent.*/
247             uint32_t flash_pes_dly_128             :    1;  /*Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent.*/
248             uint32_t spi0_lock_en                  :    1;  /*1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it.*/
249             uint32_t reserved8                     :    24;  /*reserved*/
250         };
251         uint32_t val;
252     } sus_status;
253     union {
254         struct {
255             uint32_t timing_clk_ena                :    1;  /*The bit is used to enable timing adjust clock for all reading operations.*/
256             uint32_t timing_cali                   :    1;  /*The bit is used to enable timing auto-calibration for all reading operations.*/
257             uint32_t extra_dummy_cyclelen          :    3;  /*add extra dummy spi clock cycle length for spi clock calibration.*/
258             uint32_t reserved5                     :    27;  /*reserved*/
259         };
260         uint32_t val;
261     } timing_cali;
262     union {
263         struct {
264             uint32_t din0_mode                     :    2;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
265             uint32_t din1_mode                     :    2;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
266             uint32_t din2_mode                     :    2;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
267             uint32_t din3_mode                     :    2;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
268             uint32_t reserved8                     :    24;  /*reserved*/
269         };
270         uint32_t val;
271     } din_mode;
272     union {
273         struct {
274             uint32_t din0_num                      :    1;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
275             uint32_t din1_num                      :    1;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
276             uint32_t din2_num                      :    1;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
277             uint32_t din3_num                      :    1;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
278             uint32_t reserved4                     :    28;  /*reserved*/
279         };
280         uint32_t val;
281     } din_num;
282     union {
283         struct {
284             uint32_t dout0_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
285             uint32_t dout1_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
286             uint32_t dout2_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
287             uint32_t dout3_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
288             uint32_t reserved4                     :    28;  /*reserved*/
289         };
290         uint32_t val;
291     } dout_mode;
292     uint32_t reserved_b8;
293     uint32_t reserved_bc;
294     union {
295         struct {
296             uint32_t per_end_en                    :    1;  /*The enable bit for SPI_MEM_PER_END_INT interrupt.*/
297             uint32_t pes_end_en                    :    1;  /*The enable bit for SPI_MEM_PES_END_INT interrupt.*/
298             uint32_t wpe_end_en                    :    1;  /*The enable bit for SPI_MEM_WPE_END_INT interrupt.*/
299             uint32_t slv_st_end_en                 :    1;  /*The enable bit for SPI_MEM_SLV_ST_END_INT interrupt.*/
300             uint32_t mst_st_end_en                 :    1;  /*The enable bit for SPI_MEM_MST_ST_END_INT interrupt.*/
301             uint32_t brown_out_en                  :    1;  /*The enable bit for SPI_MEM_BROWN_OUT_INT interrupt.*/
302             uint32_t reserved6                     :    26;  /*reserved*/
303         };
304         uint32_t val;
305     } int_ena;
306     union {
307         struct {
308             uint32_t per_end                       :    1;  /*The clear bit for SPI_MEM_PER_END_INT interrupt.*/
309             uint32_t pes_end                       :    1;  /*The clear bit for SPI_MEM_PES_END_INT interrupt.*/
310             uint32_t wpe_end                       :    1;  /*The clear bit for SPI_MEM_WPE_END_INT interrupt.*/
311             uint32_t slv_st_end                    :    1;  /*The clear bit for SPI_MEM_SLV_ST_END_INT interrupt.*/
312             uint32_t mst_st_end                    :    1;  /*The clear bit for SPI_MEM_MST_ST_END_INT interrupt.*/
313             uint32_t brown_out                     :    1;  /*The status bit for SPI_MEM_BROWN_OUT_INT interrupt.*/
314             uint32_t reserved6                     :    26;  /*reserved*/
315         };
316         uint32_t val;
317     } int_clr;
318     union {
319         struct {
320             uint32_t per_end                       :    1;  /*The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed. 0: Others.*/
321             uint32_t pes_end                       :    1;  /*The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended. 0: Others.*/
322             uint32_t wpe_end                       :    1;  /*The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others.*/
323             uint32_t slv_st_end                    :    1;  /*The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others*/
324             uint32_t mst_st_end                    :    1;  /*The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is changed from non idle state to idle state. 0: Others.*/
325             uint32_t brown_out                     :    1;  /*The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is loosing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others.*/
326             uint32_t reserved6                     :    26;  /*reserved*/
327         };
328         uint32_t val;
329     } int_raw;
330     union {
331         struct {
332             uint32_t per_end                       :    1;  /*The status bit for SPI_MEM_PER_END_INT interrupt.*/
333             uint32_t pes_end                       :    1;  /*The status bit for SPI_MEM_PES_END_INT interrupt.*/
334             uint32_t wpe_end                       :    1;  /*The status bit for SPI_MEM_WPE_END_INT interrupt.*/
335             uint32_t slv_st_end                    :    1;  /*The status bit for SPI_MEM_SLV_ST_END_INT interrupt.*/
336             uint32_t mst_st_end                    :    1;  /*The status bit for SPI_MEM_MST_ST_END_INT interrupt.*/
337             uint32_t brown_out                     :    1;  /*The status bit for SPI_MEM_BROWN_OUT_INT interrupt.*/
338             uint32_t reserved6                     :    26;  /*reserved*/
339         };
340         uint32_t val;
341     } int_st;
342     uint32_t reserved_d0;
343     uint32_t reserved_d4;
344     uint32_t reserved_d8;
345     union {
346         struct {
347             uint32_t clk_en                        :    1;  /*Register clock gate enable signal. 1: Enable. 0: Disable.*/
348             uint32_t reserved1                     :    31;  /*reserved*/
349         };
350         uint32_t val;
351     } clock_gate;
352     union {
353         struct {
354             uint32_t spi01_clk_sel                 :    2;  /*When the digital system clock selects PLL clock and the frequency of PLL clock is 480MHz, the value of reg_spi01_clk_sel:  0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 120MHz.  2: SPI0/1 module clock (clk) 160MHz. 3: Not used. When the digital system clock selects PLL clock and the frequency of PLL clock is 320MHz, the value of reg_spi01_clk_sel:  0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 80MHz.  2: SPI0/1 module clock (clk) 160MHz. 3: Not used. */
355             uint32_t reserved2                     :    30;  /*reserved*/
356         };
357         uint32_t val;
358     } core_clk_sel;
359     uint32_t reserved_e4;
360     uint32_t reserved_e8;
361     uint32_t reserved_ec;
362     uint32_t reserved_f0;
363     uint32_t reserved_f4;
364     uint32_t reserved_f8;
365     uint32_t reserved_fc;
366     uint32_t reserved_100;
367     uint32_t reserved_104;
368     uint32_t reserved_108;
369     uint32_t reserved_10c;
370     uint32_t reserved_110;
371     uint32_t reserved_114;
372     uint32_t reserved_118;
373     uint32_t reserved_11c;
374     uint32_t reserved_120;
375     uint32_t reserved_124;
376     uint32_t reserved_128;
377     uint32_t reserved_12c;
378     uint32_t reserved_130;
379     uint32_t reserved_134;
380     uint32_t reserved_138;
381     uint32_t reserved_13c;
382     uint32_t reserved_140;
383     uint32_t reserved_144;
384     uint32_t reserved_148;
385     uint32_t reserved_14c;
386     uint32_t reserved_150;
387     uint32_t reserved_154;
388     uint32_t reserved_158;
389     uint32_t reserved_15c;
390     uint32_t reserved_160;
391     uint32_t reserved_164;
392     uint32_t reserved_168;
393     uint32_t reserved_16c;
394     uint32_t reserved_170;
395     uint32_t reserved_174;
396     uint32_t reserved_178;
397     uint32_t reserved_17c;
398     uint32_t reserved_180;
399     uint32_t reserved_184;
400     uint32_t reserved_188;
401     uint32_t reserved_18c;
402     uint32_t reserved_190;
403     uint32_t reserved_194;
404     uint32_t reserved_198;
405     uint32_t reserved_19c;
406     uint32_t reserved_1a0;
407     uint32_t reserved_1a4;
408     uint32_t reserved_1a8;
409     uint32_t reserved_1ac;
410     uint32_t reserved_1b0;
411     uint32_t reserved_1b4;
412     uint32_t reserved_1b8;
413     uint32_t reserved_1bc;
414     uint32_t reserved_1c0;
415     uint32_t reserved_1c4;
416     uint32_t reserved_1c8;
417     uint32_t reserved_1cc;
418     uint32_t reserved_1d0;
419     uint32_t reserved_1d4;
420     uint32_t reserved_1d8;
421     uint32_t reserved_1dc;
422     uint32_t reserved_1e0;
423     uint32_t reserved_1e4;
424     uint32_t reserved_1e8;
425     uint32_t reserved_1ec;
426     uint32_t reserved_1f0;
427     uint32_t reserved_1f4;
428     uint32_t reserved_1f8;
429     uint32_t reserved_1fc;
430     uint32_t reserved_200;
431     uint32_t reserved_204;
432     uint32_t reserved_208;
433     uint32_t reserved_20c;
434     uint32_t reserved_210;
435     uint32_t reserved_214;
436     uint32_t reserved_218;
437     uint32_t reserved_21c;
438     uint32_t reserved_220;
439     uint32_t reserved_224;
440     uint32_t reserved_228;
441     uint32_t reserved_22c;
442     uint32_t reserved_230;
443     uint32_t reserved_234;
444     uint32_t reserved_238;
445     uint32_t reserved_23c;
446     uint32_t reserved_240;
447     uint32_t reserved_244;
448     uint32_t reserved_248;
449     uint32_t reserved_24c;
450     uint32_t reserved_250;
451     uint32_t reserved_254;
452     uint32_t reserved_258;
453     uint32_t reserved_25c;
454     uint32_t reserved_260;
455     uint32_t reserved_264;
456     uint32_t reserved_268;
457     uint32_t reserved_26c;
458     uint32_t reserved_270;
459     uint32_t reserved_274;
460     uint32_t reserved_278;
461     uint32_t reserved_27c;
462     uint32_t reserved_280;
463     uint32_t reserved_284;
464     uint32_t reserved_288;
465     uint32_t reserved_28c;
466     uint32_t reserved_290;
467     uint32_t reserved_294;
468     uint32_t reserved_298;
469     uint32_t reserved_29c;
470     uint32_t reserved_2a0;
471     uint32_t reserved_2a4;
472     uint32_t reserved_2a8;
473     uint32_t reserved_2ac;
474     uint32_t reserved_2b0;
475     uint32_t reserved_2b4;
476     uint32_t reserved_2b8;
477     uint32_t reserved_2bc;
478     uint32_t reserved_2c0;
479     uint32_t reserved_2c4;
480     uint32_t reserved_2c8;
481     uint32_t reserved_2cc;
482     uint32_t reserved_2d0;
483     uint32_t reserved_2d4;
484     uint32_t reserved_2d8;
485     uint32_t reserved_2dc;
486     uint32_t reserved_2e0;
487     uint32_t reserved_2e4;
488     uint32_t reserved_2e8;
489     uint32_t reserved_2ec;
490     uint32_t reserved_2f0;
491     uint32_t reserved_2f4;
492     uint32_t reserved_2f8;
493     uint32_t reserved_2fc;
494     uint32_t reserved_300;
495     uint32_t reserved_304;
496     uint32_t reserved_308;
497     uint32_t reserved_30c;
498     uint32_t reserved_310;
499     uint32_t reserved_314;
500     uint32_t reserved_318;
501     uint32_t reserved_31c;
502     uint32_t reserved_320;
503     uint32_t reserved_324;
504     uint32_t reserved_328;
505     uint32_t reserved_32c;
506     uint32_t reserved_330;
507     uint32_t reserved_334;
508     uint32_t reserved_338;
509     uint32_t reserved_33c;
510     uint32_t reserved_340;
511     uint32_t reserved_344;
512     uint32_t reserved_348;
513     uint32_t reserved_34c;
514     uint32_t reserved_350;
515     uint32_t reserved_354;
516     uint32_t reserved_358;
517     uint32_t reserved_35c;
518     uint32_t reserved_360;
519     uint32_t reserved_364;
520     uint32_t reserved_368;
521     uint32_t reserved_36c;
522     uint32_t reserved_370;
523     uint32_t reserved_374;
524     uint32_t reserved_378;
525     uint32_t reserved_37c;
526     uint32_t reserved_380;
527     uint32_t reserved_384;
528     uint32_t reserved_388;
529     uint32_t reserved_38c;
530     uint32_t reserved_390;
531     uint32_t reserved_394;
532     uint32_t reserved_398;
533     uint32_t reserved_39c;
534     uint32_t reserved_3a0;
535     uint32_t reserved_3a4;
536     uint32_t reserved_3a8;
537     uint32_t reserved_3ac;
538     uint32_t reserved_3b0;
539     uint32_t reserved_3b4;
540     uint32_t reserved_3b8;
541     uint32_t reserved_3bc;
542     uint32_t reserved_3c0;
543     uint32_t reserved_3c4;
544     uint32_t reserved_3c8;
545     uint32_t reserved_3cc;
546     uint32_t reserved_3d0;
547     uint32_t reserved_3d4;
548     uint32_t reserved_3d8;
549     uint32_t reserved_3dc;
550     uint32_t reserved_3e0;
551     uint32_t reserved_3e4;
552     uint32_t reserved_3e8;
553     uint32_t reserved_3ec;
554     uint32_t reserved_3f0;
555     uint32_t reserved_3f4;
556     uint32_t reserved_3f8;
557     union {
558         struct {
559             uint32_t date                          :    28;  /*SPI register version.*/
560             uint32_t reserved28                    :    4;  /*reserved*/
561         };
562         uint32_t val;
563     } date;
564 } spi_mem_dev_t;
565 extern spi_mem_dev_t SPIMEM0;
566 extern spi_mem_dev_t SPIMEM1;
567 
568 #ifndef __cplusplus
569 _Static_assert(sizeof(spi_mem_dev_t) == 0x400, "spi_mem_dev_t size error!");
570 #endif
571 
572 #ifdef __cplusplus
573 }
574 #endif
575