1 /*
2  * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #include "sdkconfig.h"
8 #include <stddef.h>
9 
10 #include "esp_rom_caps.h"
11 
12 #include "hal/wdt_types.h"
13 #include "hal/wdt_hal.h"
14 #include "hal/mwdt_ll.h"
15 
16 #if CONFIG_HAL_WDT_USE_ROM_IMPL
17 
18 #if ESP_ROM_WDT_INIT_PATCH
wdt_hal_init(wdt_hal_context_t * hal,wdt_inst_t wdt_inst,uint32_t prescaler,bool enable_intr)19 void wdt_hal_init(wdt_hal_context_t *hal, wdt_inst_t wdt_inst, uint32_t prescaler, bool enable_intr)
20 {
21     //Initialize HAL context
22     memset(hal, 0, sizeof(wdt_hal_context_t));
23     if (wdt_inst == WDT_MWDT0) {
24         hal->mwdt_dev = &TIMERG0;
25     }
26 #if SOC_TIMER_GROUPS >= 2
27     else if (wdt_inst == WDT_MWDT1) {
28         hal->mwdt_dev = &TIMERG1;
29     }
30 #endif
31     else {
32         hal->rwdt_dev = RWDT_DEV_GET();
33     }
34     hal->inst = wdt_inst;
35 
36     if (hal->inst == WDT_RWDT) {
37         //Unlock RTC WDT
38         rwdt_ll_write_protect_disable(hal->rwdt_dev);
39         //Disable RTC WDT, all stages, and all interrupts.
40         rwdt_ll_disable(hal->rwdt_dev);
41         rwdt_ll_disable_stage(hal->rwdt_dev, WDT_STAGE0);
42         rwdt_ll_disable_stage(hal->rwdt_dev, WDT_STAGE1);
43         rwdt_ll_disable_stage(hal->rwdt_dev, WDT_STAGE2);
44         rwdt_ll_disable_stage(hal->rwdt_dev, WDT_STAGE3);
45 #ifdef CONFIG_IDF_TARGET_ESP32
46         //Enable or disable level interrupt. Edge interrupt is always disabled.
47         rwdt_ll_set_edge_intr(hal->rwdt_dev, false);
48         rwdt_ll_set_level_intr(hal->rwdt_dev, enable_intr);
49 #else
50         //Enable or disable chip reset on timeout, and length of chip reset signal
51         rwdt_ll_set_chip_reset_width(hal->rwdt_dev, 0);
52         rwdt_ll_set_chip_reset_en(hal->rwdt_dev, false);
53 #endif
54         rwdt_ll_clear_intr_status(hal->rwdt_dev);
55         rwdt_ll_set_intr_enable(hal->rwdt_dev, enable_intr);
56         //Set default values
57 #if SOC_CPU_CORES_NUM > 1
58         rwdt_ll_set_appcpu_reset_en(hal->rwdt_dev, true);
59 #endif
60         rwdt_ll_set_procpu_reset_en(hal->rwdt_dev, true);
61         rwdt_ll_set_pause_in_sleep_en(hal->rwdt_dev, true);
62         rwdt_ll_set_cpu_reset_length(hal->rwdt_dev, WDT_RESET_SIG_LENGTH_3_2us);
63         rwdt_ll_set_sys_reset_length(hal->rwdt_dev, WDT_RESET_SIG_LENGTH_3_2us);
64         //Lock RTC WDT
65         rwdt_ll_write_protect_enable(hal->rwdt_dev);
66     } else {
67         //Unlock WDT
68         mwdt_ll_write_protect_disable(hal->mwdt_dev);
69         //Disable WDT and stages.
70         mwdt_ll_disable(hal->mwdt_dev);
71         mwdt_ll_disable_stage(hal->mwdt_dev, 0);
72         mwdt_ll_disable_stage(hal->mwdt_dev, 1);
73         mwdt_ll_disable_stage(hal->mwdt_dev, 2);
74         mwdt_ll_disable_stage(hal->mwdt_dev, 3);
75 #if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
76         //Enable or disable level interrupt. Edge interrupt is always disabled.
77         mwdt_ll_set_edge_intr(hal->mwdt_dev, false);
78         mwdt_ll_set_level_intr(hal->mwdt_dev, enable_intr);
79 #endif
80         mwdt_ll_clear_intr_status(hal->mwdt_dev);
81         mwdt_ll_set_intr_enable(hal->mwdt_dev, enable_intr);
82         //Set default values
83         mwdt_ll_set_cpu_reset_length(hal->mwdt_dev, WDT_RESET_SIG_LENGTH_3_2us);
84         mwdt_ll_set_sys_reset_length(hal->mwdt_dev, WDT_RESET_SIG_LENGTH_3_2us);
85         mwdt_ll_set_clock_source(hal->mwdt_dev, MWDT_CLK_SRC_DEFAULT);
86         mwdt_ll_enable_clock(hal->mwdt_dev, true);
87         //Set tick period
88         mwdt_ll_set_prescaler(hal->mwdt_dev, prescaler);
89         //Lock WDT
90         mwdt_ll_write_protect_enable(hal->mwdt_dev);
91     }
92 }
93 
wdt_hal_deinit(wdt_hal_context_t * hal)94 void wdt_hal_deinit(wdt_hal_context_t *hal)
95 {
96     if (hal->inst == WDT_RWDT) {
97         //Unlock WDT
98         rwdt_ll_write_protect_disable(hal->rwdt_dev);
99         //Disable WDT and clear any interrupts
100         rwdt_ll_feed(hal->rwdt_dev);
101         rwdt_ll_disable(hal->rwdt_dev);
102         rwdt_ll_clear_intr_status(hal->rwdt_dev);
103         rwdt_ll_set_intr_enable(hal->rwdt_dev, false);
104         //Lock WDT
105         rwdt_ll_write_protect_enable(hal->rwdt_dev);
106     } else {
107         //Unlock WDT
108         mwdt_ll_write_protect_disable(hal->mwdt_dev);
109         //Disable WDT and clear/disable any interrupts
110         mwdt_ll_feed(hal->mwdt_dev);
111         mwdt_ll_disable(hal->mwdt_dev);
112         mwdt_ll_clear_intr_status(hal->mwdt_dev);
113         mwdt_ll_set_intr_enable(hal->mwdt_dev, false);
114         mwdt_ll_enable_clock(hal->mwdt_dev, false);
115         //Lock WDT
116         mwdt_ll_write_protect_enable(hal->mwdt_dev);
117     }
118     //Deinit HAL context
119     hal->mwdt_dev = NULL;
120 }
121 #endif // ESP_ROM_WDT_INIT_PATCH
122 
123 #endif // CONFIG_HAL_WDT_USE_ROM_IMPL
124