1.. code-block:: none 2 3 > espefuse.py -p PORT summary 4 5 Connecting.... 6 Detecting chip type... ESP32-C3 7 8 === Run "summary" command === 9 EFUSE_NAME (Block) Description = [Meaningful Value] [Readable/Writeable] (Hex Value) 10 ---------------------------------------------------------------------------------------- 11 Calibration fuses: 12 K_RTC_LDO (BLOCK1) BLOCK1 K_RTC_LDO = -36 R/W (0b1001001) 13 K_DIG_LDO (BLOCK1) BLOCK1 K_DIG_LDO = -64 R/W (0b1010000) 14 V_RTC_DBIAS20 (BLOCK1) BLOCK1 voltage of rtc dbias20 = -40 R/W (0x8a) 15 V_DIG_DBIAS20 (BLOCK1) BLOCK1 voltage of digital dbias20 = -76 R/W (0x93) 16 DIG_DBIAS_HVT (BLOCK1) BLOCK1 digital dbias when hvt = -28 R/W (0b10111) 17 THRES_HVT (BLOCK1) BLOCK1 pvt threshold when hvt = 2000 R/W (0b0111110100) 18 TEMP_CALIB (BLOCK2) Temperature calibration data = -7.2 R/W (0b101001000) 19 OCODE (BLOCK2) ADC OCode = 78 R/W (0x4e) 20 ADC1_INIT_CODE_ATTEN0 (BLOCK2) ADC1 init code at atten0 = 1560 R/W (0b0110000110) 21 ADC1_INIT_CODE_ATTEN1 (BLOCK2) ADC1 init code at atten1 = -108 R/W (0b1000011011) 22 ADC1_INIT_CODE_ATTEN2 (BLOCK2) ADC1 init code at atten2 = -232 R/W (0b1000111010) 23 ADC1_INIT_CODE_ATTEN3 (BLOCK2) ADC1 init code at atten3 = -696 R/W (0b1010101110) 24 ADC1_CAL_VOL_ATTEN0 (BLOCK2) ADC1 calibration voltage at atten0 = -212 R/W (0b1000110101) 25 ADC1_CAL_VOL_ATTEN1 (BLOCK2) ADC1 calibration voltage at atten1 = 52 R/W (0b0000001101) 26 ADC1_CAL_VOL_ATTEN2 (BLOCK2) ADC1 calibration voltage at atten2 = -152 R/W (0b1000100110) 27 ADC1_CAL_VOL_ATTEN3 (BLOCK2) ADC1 calibration voltage at atten3 = -284 R/W (0b1001000111) 28 29 Config fuses: 30 WR_DIS (BLOCK0) Disable programming of individual eFuses = 0 R/W (0x00000000) 31 RD_DIS (BLOCK0) Disable reading from BlOCK4-10 = 0 R/W (0b0000000) 32 DIS_ICACHE (BLOCK0) Set this bit to disable Icache = False R/W (0b0) 33 DIS_TWAI (BLOCK0) Set this bit to disable CAN function = False R/W (0b0) 34 DIS_DIRECT_BOOT (BLOCK0) Disable direct boot mode = False R/W (0b0) 35 UART_PRINT_CONTROL (BLOCK0) Set the default UARTboot message output mode = Enable R/W (0b00) 36 ERR_RST_ENABLE (BLOCK0) Use BLOCK0 to check error record registers = with check R/W (0b1) 37 BLOCK_USR_DATA (BLOCK3) User data 38 = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W 39 BLOCK_SYS_DATA2 (BLOCK10) System data part 2 (reserved) 40 = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W 41 42 Flash fuses: 43 FLASH_TPUW (BLOCK0) Configures flash waiting time after power-up; in u = 0 R/W (0x0) 44 nit of ms. If the value is less than 15; the waiti 45 ng time is the configurable value; Otherwise; the 46 waiting time is twice the configurable value 47 FORCE_SEND_RESUME (BLOCK0) Set this bit to force ROM code to send a resume co = False R/W (0b0) 48 mmand during SPI boot 49 50 Identity fuses: 51 DISABLE_WAFER_VERSION_MAJOR (BLOCK0) Disables check of wafer version major = False R/W (0b0) 52 DISABLE_BLK_VERSION_MAJOR (BLOCK0) Disables check of blk version major = False R/W (0b0) 53 WAFER_VERSION_MINOR_LO (BLOCK1) WAFER_VERSION_MINOR least significant bits = 3 R/W (0b011) 54 PKG_VERSION (BLOCK1) Package version = 0 R/W (0b000) 55 BLK_VERSION_MINOR (BLOCK1) BLK_VERSION_MINOR = 2 R/W (0b010) 56 WAFER_VERSION_MINOR_HI (BLOCK1) WAFER_VERSION_MINOR most significant bit = False R/W (0b0) 57 WAFER_VERSION_MAJOR (BLOCK1) WAFER_VERSION_MAJOR = 0 R/W (0b00) 58 OPTIONAL_UNIQUE_ID (BLOCK2) Optional unique 128-bit ID 59 = 25 60 04 96 c3 fd 41 6f be ed 2c 51 1d e3 7e 21 R/W 60 BLK_VERSION_MAJOR (BLOCK2) BLK_VERSION_MAJOR of BLOCK2 = With calibration R/W (0b01) 61 WAFER_VERSION_MINOR (BLOCK0) calc WAFER VERSION MINOR = WAFER_VERSION_MINOR_HI = 3 R/W (0x3) 62 << 3 + WAFER_VERSION_MINOR_LO (read only) 63 64 Jtag fuses: 65 SOFT_DIS_JTAG (BLOCK0) Set these bits to disable JTAG in the soft way (od = 0 R/W (0b000) 66 d number 1 means disable ). JTAG can be enabled in 67 HMAC module 68 DIS_PAD_JTAG (BLOCK0) Set this bit to disable JTAG in the hard way. JTAG = False R/W (0b0) 69 is disabled permanently 70 71 Mac fuses: 72 MAC (BLOCK1) MAC address 73 = 58:cf:79:0f:96:8c (OK) R/W 74 CUSTOM_MAC (BLOCK3) Custom MAC address 75 = 00:00:00:00:00:00 (OK) R/W 76 77 Security fuses: 78 DIS_DOWNLOAD_ICACHE (BLOCK0) Set this bit to disable Icache in download mode (b = False R/W (0b0) 79 oot_mode[3:0] is 0; 1; 2; 3; 6; 7) 80 DIS_FORCE_DOWNLOAD (BLOCK0) Set this bit to disable the function that forces c = False R/W (0b0) 81 hip into download mode 82 DIS_DOWNLOAD_MANUAL_ENCRYPT (BLOCK0) Set this bit to disable flash encryption when in d = False R/W (0b0) 83 ownload boot modes 84 SPI_BOOT_CRYPT_CNT (BLOCK0) Enables flash encryption when 1 or 3 bits are set = Disable R/W (0b000) 85 and disables otherwise 86 SECURE_BOOT_KEY_REVOKE0 (BLOCK0) Revoke 1st secure boot key = False R/W (0b0) 87 SECURE_BOOT_KEY_REVOKE1 (BLOCK0) Revoke 2nd secure boot key = False R/W (0b0) 88 SECURE_BOOT_KEY_REVOKE2 (BLOCK0) Revoke 3rd secure boot key = False R/W (0b0) 89 KEY_PURPOSE_0 (BLOCK0) Purpose of Key0 = USER R/W (0x0) 90 KEY_PURPOSE_1 (BLOCK0) Purpose of Key1 = USER R/W (0x0) 91 KEY_PURPOSE_2 (BLOCK0) Purpose of Key2 = USER R/W (0x0) 92 KEY_PURPOSE_3 (BLOCK0) Purpose of Key3 = USER R/W (0x0) 93 KEY_PURPOSE_4 (BLOCK0) Purpose of Key4 = USER R/W (0x0) 94 KEY_PURPOSE_5 (BLOCK0) Purpose of Key5 = USER R/W (0x0) 95 SECURE_BOOT_EN (BLOCK0) Set this bit to enable secure boot = False R/W (0b0) 96 SECURE_BOOT_AGGRESSIVE_REVOKE (BLOCK0) Set this bit to enable revoking aggressive secure = False R/W (0b0) 97 boot 98 DIS_DOWNLOAD_MODE (BLOCK0) Set this bit to disable download mode (boot_mode[3 = False R/W (0b0) 99 :0] = 0; 1; 2; 3; 6; 7) 100 ENABLE_SECURITY_DOWNLOAD (BLOCK0) Set this bit to enable secure UART download mode = False R/W (0b0) 101 SECURE_VERSION (BLOCK0) Secure version (used by ESP-IDF anti-rollback feat = 0 R/W (0x0000) 102 ure) 103 BLOCK_KEY0 (BLOCK4) 104 Purpose: USER 105 Key0 or user data 106 = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W 107 BLOCK_KEY1 (BLOCK5) 108 Purpose: USER 109 Key1 or user data 110 = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W 111 BLOCK_KEY2 (BLOCK6) 112 Purpose: USER 113 Key2 or user data 114 = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W 115 BLOCK_KEY3 (BLOCK7) 116 Purpose: USER 117 Key3 or user data 118 = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W 119 BLOCK_KEY4 (BLOCK8) 120 Purpose: USER 121 Key4 or user data 122 = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W 123 BLOCK_KEY5 (BLOCK9) 124 Purpose: USER 125 Key5 or user data 126 = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W 127 128 Spi Pad fuses: 129 SPI_PAD_CONFIG_CLK (BLOCK1) SPI PAD CLK = 0 R/W (0b000000) 130 SPI_PAD_CONFIG_Q (BLOCK1) SPI PAD Q(D1) = 0 R/W (0b000000) 131 SPI_PAD_CONFIG_D (BLOCK1) SPI PAD D(D0) = 0 R/W (0b000000) 132 SPI_PAD_CONFIG_CS (BLOCK1) SPI PAD CS = 0 R/W (0b000000) 133 SPI_PAD_CONFIG_HD (BLOCK1) SPI PAD HD(D3) = 0 R/W (0b000000) 134 SPI_PAD_CONFIG_WP (BLOCK1) SPI PAD WP(D2) = 0 R/W (0b000000) 135 SPI_PAD_CONFIG_DQS (BLOCK1) SPI PAD DQS = 0 R/W (0b000000) 136 SPI_PAD_CONFIG_D4 (BLOCK1) SPI PAD D4 = 0 R/W (0b000000) 137 SPI_PAD_CONFIG_D5 (BLOCK1) SPI PAD D5 = 0 R/W (0b000000) 138 SPI_PAD_CONFIG_D6 (BLOCK1) SPI PAD D6 = 0 R/W (0b000000) 139 SPI_PAD_CONFIG_D7 (BLOCK1) SPI PAD D7 = 0 R/W (0b000000) 140 141 Usb fuses: 142 DIS_USB_JTAG (BLOCK0) Set this bit to disable function of usb switch to = False R/W (0b0) 143 jtag in module of usb device 144 DIS_USB_SERIAL_JTAG (BLOCK0) USB-Serial-JTAG = Enable R/W (0b0) 145 USB_EXCHG_PINS (BLOCK0) Set this bit to exchange USB D+ and D- pins = False R/W (0b0) 146 DIS_USB_SERIAL_JTAG_ROM_PRINT (BLOCK0) USB printing = Enable R/W (0b0) 147 DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE (BLOCK0) Disable UART download mode through USB-Serial-JTAG = False R/W (0b0) 148 149 Vdd fuses: 150 VDD_SPI_AS_GPIO (BLOCK0) Set this bit to vdd spi pin function as gpio = False R/W (0b0) 151 152 Wdt fuses: 153 WDT_DELAY_SEL (BLOCK0) RTC watchdog timeout threshold; in unit of slow cl = 40000 R/W (0b00) 154 ock cycle 155
