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/Zephyr-latest/dts/bindings/memory-controllers/
Datmel,sam-smc.yaml2 # SPDX-License-Identifier: Apache-2.0
7 The SMC allows to interface with static-memory mapped external devices such as
19 pinctrl-0 = <&smc_default>;
20 pinctrl-names = "default";
25 atmel,smc-write-mode = "nwe";
26 atmel,smc-read-mode = "nrd";
27 atmel,smc-setup-timing = <1 1 1 1>;
28 atmel,smc-pulse-timing = <6 6 6 6>;
29 atmel,smc-cycle-timing = <7 7>;
33 The above example configures a is66wv51216dbll-55 device. The device is a
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Drenesas,ra-sdram.yaml2 # SPDX-License-Identifier: Apache-2.0
7 pinctrl-0 = <&sdram_default>;
8 pinctrl-names = "default";
10 auto-refresh-interval = <10>;
11 auto-refresh-count = <8>;
12 precharge-cycle-count = <3>;
13 multiplex-addr-shift = "10-bit";
14 edian-mode = "little-endian";
15 continuous-access;
16 bus-width = "16-bit";
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/Zephyr-latest/arch/arm/core/cortex_m/
Dtiming.c5 * SPDX-License-Identifier: Apache-2.0
10 * @brief ARM Cortex-M Timing functions interface based on DWT
16 #include <zephyr/timing/timing.h>
22 * @brief Return the current frequency of the cycle counter
24 * This routine returns the current frequency of the DWT Cycle Counter
27 * @return the cycle counter frequency value
66 * cycles are in 32-bit, and delta must be in z_arm_dwt_freq_get()
67 * calculated in 32-bit precision. Or it would be in z_arm_dwt_freq_get()
68 * wrapping around in 64-bit. in z_arm_dwt_freq_get()
70 dcyc = (uint32_t)cyc_end - (uint32_t)cyc_start; in z_arm_dwt_freq_get()
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/Zephyr-latest/tests/kernel/timer/timer_behavior/dts/bindings/
Dtimer-behavior-external.yaml3 # SPDX-License-Identifier: Apache-2.0
10 compatible: "test-kernel-timer-behavior-external"
13 timerout-gpios:
14 type: phandle-array
17 GPIO pin that will toggle on each cycle of the test, to be
19 that will collect timing information.
/Zephyr-latest/include/zephyr/timing/
Dtiming.h4 * SPDX-License-Identifier: Apache-2.0
11 #include <zephyr/timing/types.h>
18 * @brief Timing Measurement APIs
19 * @defgroup timing_api Timing Measurement APIs
22 * The timing measurement APIs can be used to obtain execution
25 * Please note that the timing functions may use a different timer
31 * @brief SoC specific Timing Measurement APIs
32 * @defgroup timing_api_soc SoC specific Timing Measurement APIs
35 * Implements the necessary bits to support timing measurement
36 * using SoC specific timing measurement mechanism.
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/Zephyr-latest/samples/basic/threads/
DREADME.rst1 .. zephyr:code-sample:: multi-thread-blinky
3 :relevant-api: gpio_interface thread_apis
15 loop control and timing logic controlled by separate functions.
17 - ``blink0()`` controls ``led0`` and has a 100ms sleep cycle
18 - ``blink1()`` controls ``led1`` and has a 1000ms sleep cycle
32 ``led0`` and ``led1`` :ref:`devicetree <dt-guide>` aliases, usually in the
33 :ref:`BOARD.dts file <devicetree-in-out-files>`.
38 .. code-block:: none
48 .. zephyr-app-commands::
49 :zephyr-app: samples/basic/threads
/Zephyr-latest/doc/kernel/services/timing/
Dclocks.rst3 Kernel Timing
6 Zephyr provides a robust and scalable timing framework to enable
7 reporting and tracking of timed events from hardware timing sources of
22 The kernel presents a "cycle" count via the :c:func:`k_cycle_get_32`
24 represents the fastest cycle counter that the operating system is able
25 to present to the user (for example, a CPU cycle counter) and that the
46 ----------
59 :c:func:`k_cyc_to_us_floor64` will convert a measured cycle count
66 word, these conversions expand to a 2-4 operation sequence, requiring
80 Apps with precise timing requirements (that are willing to do their
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/Zephyr-latest/boards/atmel/sam/sam4s_xplained/
Dsam4s_xplained.dts3 * SPDX-License-Identifier: Apache-2.0
6 /dts-v1/;
9 #include "sam4s_xplained-pinctrl.dtsi"
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
17 i2c-0 = &twi0;
18 i2c-1 = &twi1;
19 pwm-0 = &pwm0;
28 zephyr,shell-uart = &uart0;
34 compatible = "zephyr,memory-region", "mmio-sram";
37 zephyr,memory-region = "SRAM1";
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/Zephyr-latest/drivers/led_strip/
Dtlc59731.c4 * SPDX-License-Identifier: Apache-2.0
13 * TLC59731 is a 3-Channel, 8-Bit, PWM LED Driver
14 * With Single-Wire Interface (EasySet)
20 * cycle time.
24 * A zero is represented by no additional pulses within a cycle.
26 * (half a cycle) after the first one. We need at least some delay to get to
29 * the cycle. This time can be slightly shorter because the second pulse
30 * already closes the cycle.
43 /* Pulse timing */
99 rgb_write_bit(led_dev, data & BIT((idx--))); in rgb_write_data()
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/Zephyr-latest/drivers/timer/
DKconfig.x861 # Copyright (c) 2014-2015 Wind River Systems, Inc.
3 # Copyright (c) 2019-2023 Intel Corp.
4 # SPDX-License-Identifier: Apache-2.0
45 deadline capability. The use of a free-running 64 bit
47 from the handling, and the near-instruction-cycle resolution
49 limit becomes the CPU time taken to execute the timing
50 logic). SMP-safe and very fast, this should be the obvious
63 local APIC in one-shot mode as the timeout event source.
77 last IO-APIC IRQ (the timer is the first entry in the APIC
79 user-configurable and almost certainly should be managed via
Dgecko_burtc_timer.c8 * SPDX-License-Identifier: Apache-2.0
15 * @brief SiLabs Gecko BURTC-based sys_clock driver
84 * so we don't need to do make the whole read-and-modify atomic, just in burtc_isr()
90 uint32_t unannounced = (curr - prev) / g_cyc_per_tick; in burtc_isr()
99 * announce the very next tick - in that case we skip one and in burtc_isr()
102 if ((next - curr) < MIN_DELAY_CYC) { in burtc_isr()
123 * 0 - announce upcoming tick itself in sys_clock_set_timeout()
124 * 1 - skip upcoming one, but announce the one after it, etc. in sys_clock_set_timeout()
127 ticks = CLAMP(ticks - 1, 0, g_max_timeout_ticks); in sys_clock_set_timeout()
135 uint32_t unannounced = (curr - prev) / g_cyc_per_tick; in sys_clock_set_timeout()
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/Zephyr-latest/include/zephyr/drivers/
Dcharger.h4 * SPDX-License-Identifier: Apache-2.0
75 * level and timing
82 * current level and timing
107 * Reserved to demark downstream custom properties - use this value as the actual value may
322 * @brief Callback API enabling or disabling a charge cycle.
355 const struct charger_driver_api *api = (const struct charger_driver_api *)dev->api; in z_impl_charger_get_prop()
357 return api->get_property(dev, prop, val); in z_impl_charger_get_prop()
376 const struct charger_driver_api *api = (const struct charger_driver_api *)dev->api; in z_impl_charger_set_prop()
378 return api->set_property(dev, prop, val); in z_impl_charger_set_prop()
382 * @brief Enable or disable a charge cycle
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/Zephyr-latest/tests/kernel/sleep/src/
Dusleep.c4 * SPDX-License-Identifier: Apache-2.0
11 * precision timing tests in an emulation environment are not reliable.
23 * rate assumes 3 ticks for non-timeout effects so increase the
57 * fast tick rates, and cycle layer may inject another to guarantee
82 elapsed_ms = end_ms - start_ms; in ZTEST_USER()
/Zephyr-latest/include/zephyr/arch/
Darch_interface.h4 * SPDX-License-Identifier: Apache-2.0
8 * @defgroup arch-interface Architecture Interface
13 * call architecture-specific API so will have the prototypes for the
14 * architecture-specific APIs here. Architecture APIs that aren't used in this
17 * The set of architecture-specific APIs used internally by public macros and
53 * @defgroup arch-timing Architecture timing APIs
54 * @ingroup arch-interface
59 * Obtain the current cycle count, in units specified by
67 * @return The current cycle time. This should count up monotonically
81 * @return The current cycle time. This should count up monotonically
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/Zephyr-latest/soc/atmel/sam/common/
Dsoc_gpio.h2 * Copyright (c) 2016-2017 Piotr Mienkowski
4 * SPDX-License-Identifier: Apache-2.0
101 * - configure pin(s) as input with debounce filter enabled.
102 * - connect pin(s) to a peripheral B and enable pull-up.
103 * - configure pin(s) as open drain output.
111 * a pull-up and user wants to read pin's input value it is necessary
143 pin->regs->OVRS = pin->mask; in soc_gpio_set()
145 pin->regs->PIO_SODR = pin->mask; in soc_gpio_set()
161 pin->regs->OVRC = pin->mask; in soc_gpio_clear()
163 pin->regs->PIO_CODR = pin->mask; in soc_gpio_clear()
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/Zephyr-latest/boards/renesas/ek_ra8d1/
Dek_ra8d1.dts3 * SPDX-License-Identifier: Apache-2.0
6 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input-event-codes.h>
11 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
12 #include <zephyr/dt-bindings/memory-controller/renesas,ra-sdram.h>
13 #include <zephyr/dt-bindings/adc/adc.h>
14 #include "ek_ra8d1-pinctrl.dtsi"
17 model = "Renesas EK-RA8D1";
24 zephyr,shell-uart = &uart9;
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/Zephyr-latest/drivers/spi/
Dspi_xec_qmspi_ldma.c4 * SPDX-License-Identifier: Apache-2.0
20 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
21 #include <zephyr/dt-bindings/interrupt-controller/mchp-xec-ecia.h>
35 * data bytes will be left shifted by 1. Work-around for SPI Mode 3 is
123 return -ETIMEDOUT; in xec_qmspi_spin_yield()
132 * reset QMSPI controller with save/restore of timing registers.
133 * Some QMSPI timing register may be modified by the Boot-ROM OTP
144 taps[0] = regs->TM_TAPS; in qmspi_reset()
145 taps[1] = regs->TM_TAPS_ADJ; in qmspi_reset()
146 taps[2] = regs->TM_TAPS_CTRL; in qmspi_reset()
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Dspi_xec_qmspi.c4 * SPDX-License-Identifier: Apache-2.0
58 REG8(&regs->TX_FIFO) = data8; in txb_wr8()
63 return REG8(&regs->RX_FIFO); in rxb_rd8()
87 qmode = regs->MODE & ~(MCHP_QMSPI_M_FDIV_MASK); in qmspi_set_frequency()
89 regs->MODE = qmode; in qmspi_set_frequency()
95 * CPHA = 0 Transmitter changes data on trailing of preceding clock cycle.
96 * Receiver samples data on leading edge of clock cycle.
97 * 1 Transmitter changes data on leading edge of current clock cycle.
98 * Receiver samples data on the trailing edge of clock cycle.
129 if (((regs->MODE >> MCHP_QMSPI_M_FDIV_POS) & in qmspi_set_signalling_mode()
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/Zephyr-latest/boards/st/stm32l562e_dk/
Dstm32l562e_dk_common.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <st/l5/stm32l562qeixq-pinctrl.dtsi>
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
11 #include <zephyr/dt-bindings/memory-controller/stm32-fmc-nor-psram.h>
12 #include <zephyr/dt-bindings/mipi_dbi/mipi_dbi.h>
16 compatible = "gpio-leds";
28 compatible = "gpio-keys";
37 die-temp0 = &die_temp;
38 volt-sensor0 = &vref;
39 volt-sensor1 = &vbat;
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/Zephyr-latest/kernel/
DKconfig3 # Copyright (c) 2014-2015 Wind River Systems, Inc.
4 # SPDX-License-Identifier: Apache-2.0
9 module-str = kernel
13 bool "Multi-threading" if ARCH_HAS_SINGLE_THREAD_SUPPORT
35 K_PRIO_COOP(0) to K_PRIO_COOP(CONFIG_NUM_COOP_PRIORITIES - 1)
39 -CONFIG_NUM_COOP_PRIORITIES to -1
58 to priorities 0 to CONFIG_NUM_PREEMPT_PRIORITIES - 1.
71 default -2 if !PREEMPT_ENABLED
85 default -127
92 int "Number of very-high priority 'preemptor' threads"
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/Zephyr-latest/boards/native/doc/
Darch_soc.rst22 Zephyr application, eliminating the need for architecture-specific
56 You must have the 32-bit C library installed in your system
57 (in Ubuntu 16.04 install the gcc-multilib package)
67 for Linux (WSL1) because WSL1 does not support native 32-bit binaries.
72 <https://github.com/microsoft/WSL/issues/2468#issuecomment-374904520>`_ it
102 - There can **not** be busy wait loops in the application code that wait for
109 .. code-block:: c
117 .. code-block:: c
123 - Code that depends on its own execution speed will normally not
127 .. code-block:: c
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/Zephyr-latest/drivers/watchdog/
Dwdt_nxp_fs26.h4 * SPDX-License-Identifier: Apache-2.0
12 /* Main or Fail-safe register selection (M/FS) */
32 /* Interrupt notification from the Fail-Safe domain */
260 /* Reaction on RSTB or FAIL SAFE output in case of BAD Watchdog (data or timing) */
331 /* Acknowledge timing following a fault detection on ERRMON */
423 /* Watchdog window duty cycle */
459 /* Bad WD refresh, Error in the timing */
/Zephyr-latest/drivers/adc/
Dadc_max11102_17.c4 * SPDX-License-Identifier: Apache-2.0
44 const struct max11102_17_config *config = dev->config; in max11102_17_switch_channel()
45 struct max11102_17_data *data = dev->data; in max11102_17_switch_channel()
58 memcpy(&bus, &config->bus, sizeof(bus)); in max11102_17_switch_channel()
67 gpio_pin_set_dt(&config->gpio_chsel, data->current_channel_id); in max11102_17_switch_channel()
69 result = spi_read_dt(&config->bus, &rx); in max11102_17_switch_channel()
81 const struct max11102_17_config *config = dev->config; in max11102_17_channel_setup()
83 LOG_DBG("read from ADC channel %i", channel_cfg->channel_id); in max11102_17_channel_setup()
85 if (channel_cfg->reference != ADC_REF_EXTERNAL0) { in max11102_17_channel_setup()
86 LOG_ERR("invalid reference %i", channel_cfg->reference); in max11102_17_channel_setup()
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/Zephyr-latest/doc/security/
Dsecurity-overview.rst1 .. _security-overview:
14 documents are created, this document is a top-level overview and entry
32 relevant sub-modules is created, threats are identified, and
43 .. figure:: media/security-process-steps.png
64 noted in RFC-2119, "These terms are frequently used to specify behavior
98 - **Security** **Functionality** with a focus on cryptographic
104 - **Quality Assurance** is driven by using a development process that
111 - **Execution Protection** including thread separation, stack and
164 - Verifying correct functionality of the implementation
166 - Increasing the readability and maintainability of the contributed
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/Zephyr-latest/soc/ite/ec/common/
Dchip_chipregs.h3 * SPDX-License-Identifier: Apache-2.0
48 /* --- General Control (GCTRL) --- */
52 /* RISC-V JTAG Debug Interface Enable */
54 /* RISC-V JTAG Debug Interface Selection */
67 /* --- External GPIO Control (EGPIO) --- */
225 /* 0x001: Cycle Time0 */
233 /* 0x010: Cycle Time1 MSB */
257 /* 0x041: Cycle Time1 */
259 /* 0x042: Cycle Time2 */
261 /* 0x043: Cycle Time3 */
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