Lines Matching +full:cycle +full:- +full:timing
2 * Copyright (c) 2016-2017 Piotr Mienkowski
4 * SPDX-License-Identifier: Apache-2.0
101 * - configure pin(s) as input with debounce filter enabled.
102 * - connect pin(s) to a peripheral B and enable pull-up.
103 * - configure pin(s) as open drain output.
111 * a pull-up and user wants to read pin's input value it is necessary
143 pin->regs->OVRS = pin->mask; in soc_gpio_set()
145 pin->regs->PIO_SODR = pin->mask; in soc_gpio_set()
161 pin->regs->OVRC = pin->mask; in soc_gpio_clear()
163 pin->regs->PIO_CODR = pin->mask; in soc_gpio_clear()
179 return pin->regs->PVR & pin->mask; in soc_gpio_get()
181 return pin->regs->PIO_PDSR & pin->mask; in soc_gpio_get()
191 * between 1/2 selected clock cycle and one tdiv_slck clock cycle, the pulse may
192 * or may not be taken into account, depending on the precise timing of its
202 * @param div slow clock divider, valid values: from 0 to 2^14 - 1
209 pin->regs->STERS = pin->mask; in soc_gpio_debounce_length_set()
211 pin->regs->STERC = pin->mask; in soc_gpio_debounce_length_set()
214 pin->regs->PIO_SCDR = PIO_SCDR_DIV(div); in soc_gpio_debounce_length_set()