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/Zephyr-latest/dts/bindings/spi/
Despressif,esp32-spi.yaml3 compatible: "espressif,esp32-spi"
5 include: [spi-controller.yaml, pinctrl-device.yaml]
11 pinctrl-0:
14 pinctrl-names:
17 half-duplex:
20 Enable half-duplex communication mode.
24 dummy-comp:
31 Enable 3-wire mode
35 dma-enabled:
39 dma-clk:
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/Zephyr-latest/dts/bindings/mtd/
Dnxp,imx-flexspi-device.yaml2 # SPDX-License-Identifier: Apache-2.0
6 include: [spi-device.yaml, "jedec,jesd216.yaml"]
9 cs-interval-unit:
13 - 1
14 - 256
20 cs-interval:
28 cs-setup-time:
32 Chip select setup time, in serial clock cycles. See the TCSS field in
36 cs-hold-time:
40 Chip select hold time, in serial clock cycles. See the TCSH field in
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/Zephyr-latest/boards/nxp/mimxrt1050_evk/
Dmimxrt1050_evk_mimxrt1052_hyperflash.dts4 * SPDX-License-Identifier: Apache-2.0
11 zephyr,flash-controller = &s26ks512s0;
13 zephyr,code-partition = &slot0_partition;
19 ahb-prefetch;
20 ahb-read-addr-opt;
21 pinctrl-0 = <&pinmux_flexspi1>;
22 pinctrl-names = "default";
23 ahb-bufferable;
24 ahb-cacheable;
25 sck-differential-clock;
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/Zephyr-latest/boards/nxp/mimxrt1060_evk/
Dmimxrt1060_evk_mimxrt1062_hyperflash.dts4 * SPDX-License-Identifier: Apache-2.0
11 zephyr,flash-controller = &s26ks512s0;
13 zephyr,code-partition = &slot0_partition;
19 ahb-prefetch;
20 ahb-read-addr-opt;
21 ahb-bufferable;
22 ahb-cacheable;
23 sck-differential-clock;
24 combination-mode;
25 rx-clock-source = <3>;
[all …]
/Zephyr-latest/dts/bindings/qspi/
Dnxp,s32-qspi.yaml2 # SPDX-License-Identifier: Apache-2.0
10 compatible: "nxp,s32-qspi"
12 include: [base.yaml, pinctrl-device.yaml]
20 "#address-cells":
23 "#size-cells":
26 data-rate:
29 - SDR
30 - DDR
33 - Single Data Rate (SDR): sampling of incoming data occurs on single edges.
34 - Double Data Rate (DDR): sampling of incoming data occurs on both edges.
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/Zephyr-latest/boards/nxp/frdm_rw612/
Dfrdm_rw612_common.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include "frdm_rw612-pinctrl.dtsi"
15 usart-0 = &flexcomm3;
16 i2c-0 = &flexcomm2;
17 pwm-0 = &sctimer;
24 zephyr,shell-uart = &flexcomm3;
28 compatible = "gpio-leds";
36 compatible = "nxp,lpc-usart";
38 current-speed = <115200>;
39 pinctrl-0 = <&pinmux_flexcomm3_usart>;
[all …]
/Zephyr-latest/boards/nxp/frdm_mcxn947/
Dfrdm_mcxn947.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include "frdm_mcxn947-pinctrl.dtsi"
8 #include <zephyr/dt-bindings/i2c/i2c.h>
9 #include <zephyr/dt-bindings/input/input-event-codes.h>
19 mcuboot-button0 = &user_button_2;
23 compatible = "gpio-leds";
42 compatible = "gpio-keys";
58 * This node describes the GPIO pins of the LCD-PAR-S035 panel 8080 interface.
60 nxp_lcd_8080_connector: lcd-8080-connector {
61 compatible = "nxp,lcd-8080";
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/Zephyr-latest/boards/atmel/sam/sam4s_xplained/
Dsam4s_xplained.dts3 * SPDX-License-Identifier: Apache-2.0
6 /dts-v1/;
9 #include "sam4s_xplained-pinctrl.dtsi"
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
17 i2c-0 = &twi0;
18 i2c-1 = &twi1;
19 pwm-0 = &pwm0;
28 zephyr,shell-uart = &uart0;
34 compatible = "zephyr,memory-region", "mmio-sram";
37 zephyr,memory-region = "SRAM1";
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/Zephyr-latest/boards/nxp/mimxrt1062_fmurt6/
Dmimxrt1062_fmurt6.dts2 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
10 #include "mimxrt1062_fmurt6-pinctrl.dtsi"
11 #include <zephyr/dt-bindings/pwm/pwm.h>
25 telem4-gps2 = &lpuart5;
29 zephyr,flash-controller = &s26ks512s0;
31 zephyr,code-partition = &slot0_partition;
32 zephyr,uart-mcumgr = &lpuart7;
37 zephyr,shell-uart = &lpuart7;
42 compatible = "gpio-leds";
[all …]
/Zephyr-latest/boards/nxp/rd_rw612_bga/
Drd_rw612_bga.dtsi2 * Copyright 2022-2024 NXP
4 * SPDX-License-Identifier: Apache-2.0
8 #include "rd_rw612_bga-pinctrl.dtsi"
9 #include <zephyr/dt-bindings/input/input-event-codes.h>
16 usart-0 = &flexcomm3;
18 i2c-0 = &flexcomm2;
20 dmic-dev = &dmic0;
21 mcuboot-button0 = &sw_4;
22 pwm-0 = &sctimer;
28 zephyr,code-partition = &slot0_partition;
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/Zephyr-latest/include/zephyr/bluetooth/
Dconn.h6 * Copyright (c) 2015-2016 Intel Corporation
8 * SPDX-License-Identifier: Apache-2.0
73 * Connection Interval: 30-50 ms
152 /** Maximum Link Layer transmission payload time in us. */
156 /** Maximum Link Layer reception payload time in us. */
164 /** Maximum Link Layer transmission payload time in us. */
171 * @param _tx_max_time Maximum Link Layer transmission payload time in us.
182 * @param _tx_max_time Maximum Link Layer transmission payload time in us.
208 * after a packet containing a Link Layer PDU with a non-zero Length
224 * a packet containing a Link Layer PDU with a non-zero Length
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/Zephyr-latest/soc/nxp/imxrt/
Dflexspi_nor_config.h6 * SPDX-License-Identifier: Apache-2.0
183 /* !< Switch to 0-4-4/0-8-8 mode */
196 /* !< [0x000-0x003] Tag, fixed value 0x42464346UL */
198 /* !< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix */
200 /* !< [0x008-0x00b] Reserved for future use */
202 /* !< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 */
204 /* !< [0x00d-0x00d] CS hold time, default value: 3 */
206 /* !< [0x00e-0x00e] CS setup time, default value: 3 */
208 /* !< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For */
211 /* !< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable */
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/Zephyr-latest/drivers/adc/
Dadc_rpi_pico.c5 * SPDX-License-Identifier: Apache-2.0
27 #define ADC_RPI_CHANNEL_NUM (ADC_CS_RROBIN_MSB - ADC_CS_RROBIN_LSB + 1)
39 /** function pointer to irq setup */
69 hw_set_bits(&adc_hw->cs, ADC_CS_START_ONCE_BITS); in adc_start_once()
74 return (uint16_t)adc_hw->result; in adc_get_result()
79 return (adc_hw->cs & ADC_CS_ERR_BITS) ? true : false; in adc_get_err()
85 hw_set_bits(&adc_hw->fcs, ADC_FCS_OVER_BITS); in adc_clear_errors()
86 hw_set_bits(&adc_hw->fcs, ADC_FCS_UNDER_BITS); in adc_clear_errors()
87 hw_set_bits(&adc_hw->fcs, ADC_FCS_ERR_BITS); in adc_clear_errors()
88 hw_set_bits(&adc_hw->cs, ADC_CS_ERR_STICKY_BITS); in adc_clear_errors()
[all …]
/Zephyr-latest/subsys/mgmt/ec_host_cmd/backends/
Dec_host_cmd_backend_shi_npcx.c4 * SPDX-License-Identifier: Apache-2.0
32 #define HAL_INSTANCE(dev) (struct shi_reg *)(((const struct shi_npcx_config *)(dev)->config)->base)
48 * This affects the slowest SPI clock we can support. A delay of 8192 us permits a 512-byte request
62 * Space allocation of the past-end status byte (EC_SHI_PAST_END) in the out_msg buffer.
73 * one last past-end byte at the end so any additional bytes clocked out by
81 * overhead, as passed to the host command handler, must be 32-bit aligned.
87 SHI_STATE_NONE = -1,
96 /* Canceling response since CS deasserted and output NOT_READY byte */
117 /* Chip-select interrupts */
145 * With the workaround, CS assertion/de-assertion INT and SHI module's INT come from
[all …]
/Zephyr-latest/boards/nxp/mimxrt595_evk/
Dmimxrt595_evk_mimxrt595s_cm33.dts2 * Copyright 2022-2023, NXP
4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
12 #include "mimxrt595_evk_mimxrt595s_cm33-pinctrl.dtsi"
16 model = "NXP MIMXRT595-EVK board";
25 usart-0 = &flexcomm0;
30 pwm-0 = &sc_timer;
31 dmic-dev = &dmic0;
32 mcuboot-button0 = &user_button_1;
[all …]
/Zephyr-latest/drivers/bluetooth/hci/
Dhci_spi_st.c1 /* hci_spi_st.c - STMicroelectronics HCI SPI Bluetooth driver */
7 * SPDX-License-Identifier: Apache-2.0
65 #define MAX_MTU (SPI_MAX_MSG_LEN - H4_HDR_SIZE - BT_L2CAP_HDR_SIZE - BT_HCI_ACL_HDR_SIZE)
126 return -ENOTSUP; in bluenrg_bt_reset()
138 /* Give firmware some time to read the IRQ high */ in bluenrg_bt_reset()
210 /* On BlueNRG-MS, host is expected to read */
236 return -EINVAL; in bt_spi_get_header()
247 /* Make sure CS is raised before a new attempt */ in bt_spi_get_header()
248 gpio_pin_set_dt(&bus.config.cs.gpio, 0); in bt_spi_get_header()
257 attempts--; in bt_spi_get_header()
[all …]
/Zephyr-latest/subsys/bluetooth/controller/ll_sw/
Dull_peripheral.c2 * Copyright (c) 2018-2019 Nordic Semiconductor ASA
4 * SPDX-License-Identifier: Apache-2.0
96 adv = ((struct lll_adv *)ftr->param)->hdr.parent;
97 conn = lll->hdr.parent;
100 pdu_adv = (void *)rx->pdu;
102 peer_addr_type = pdu_adv->tx_addr;
103 memcpy(peer_addr, pdu_adv->connect_ind.init_addr, BDADDR_SIZE);
106 uint8_t rl_idx = ftr->rl_idx;
123 link = rx->hdr.link;
127 const uint8_t own_id_addr_type = pdu_adv->rx_addr;
[all …]
Dull_central.c2 * Copyright (c) 2018-2021 Nordic Semiconductor ASA
4 * SPDX-License-Identifier: Apache-2.0
134 lll = &scan->lll; in ll_create_connection()
135 lll_coded = &scan_coded->lll; in ll_create_connection()
144 if (!lll_coded->conn) { in ll_create_connection()
145 lll_coded->conn = lll->conn; in ll_create_connection()
150 if (!lll->conn) { in ll_create_connection()
151 lll->conn = lll_coded->conn; in ll_create_connection()
160 lll = &scan->lll; in ll_create_connection()
164 /* NOTE: non-zero PHY value enables initiating connection on that PHY */ in ll_create_connection()
[all …]
/Zephyr-latest/drivers/spi/
Dspi_xec_qmspi.c4 * SPDX-License-Identifier: Apache-2.0
35 /* Device run time data */
58 REG8(&regs->TX_FIFO) = data8; in txb_wr8()
63 return REG8(&regs->RX_FIFO); in rxb_rd8()
87 qmode = regs->MODE & ~(MCHP_QMSPI_M_FDIV_MASK); in qmspi_set_frequency()
89 regs->MODE = qmode; in qmspi_set_frequency()
129 if (((regs->MODE >> MCHP_QMSPI_M_FDIV_POS) & in qmspi_set_signalling_mode()
135 regs->MODE = (regs->MODE & ~(MCHP_QMSPI_M_SIG_MASK)) in qmspi_set_signalling_mode()
148 switch (config->operation & SPI_LINES_MASK) { in qmspi_config_get_lines()
174 * NOTE: QMSPI can control two chip selects. At this time we use CS0# only.
[all …]
Dspi_xec_qmspi_ldma.c4 * SPDX-License-Identifier: Apache-2.0
20 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
21 #include <zephyr/dt-bindings/interrupt-controller/mchp-xec-ecia.h>
35 * data bytes will be left shifted by 1. Work-around for SPI Mode 3 is
94 /* Device run time data */
123 return -ETIMEDOUT; in xec_qmspi_spin_yield()
133 * Some QMSPI timing register may be modified by the Boot-ROM OTP
144 taps[0] = regs->TM_TAPS; in qmspi_reset()
145 taps[1] = regs->TM_TAPS_ADJ; in qmspi_reset()
146 taps[2] = regs->TM_TAPS_CTRL; in qmspi_reset()
[all …]
/Zephyr-latest/drivers/ieee802154/
Dieee802154_cc13xx_cc26xx_subg.c4 * SPDX-License-Identifier: Apache-2.0
45 /* User-defined CMD_PROP_RADIO_DIV_SETUP structures */
54 /* Radio register overrides for CC13x2R (note: CC26x2 does not support sub-GHz radio)
55 * from SmartRF Studio (200kbps, 50kHz deviation, 2-GFSK, 311.8kHz Rx BW),
65 /* Tx: Configure PA ramp time, PACTL2.RC=0x3 (in ADI0, set PACTL2[4:3]=0x3) */
67 /* Tx: Configure PA ramping, set wait time before turning off
73 /* Rx: Set RSSI offset to adjust reported RSSI by -1 dB (default: -2),
77 /* Rx: Set anti-aliasing filter bandwidth to 0x8 (in ADI0, set IFAMPCTL3[7:4]=0x8) */
86 /* CC1352P overrides from SmartRF Studio (200kbps, 50kHz deviation, 2-GFSK, 311.8kHz Rx BW) */
88 /* Tx: Configure PA ramp time, PACTL2.RC=0x3 (in ADI0, set PACTL2[4:3]=0x1) */
[all …]
/Zephyr-latest/doc/releases/
Drelease-notes-3.4.rst20 * Added Power Delivery Source Support to the USB-C Stack.
22 * Cache API functions are now fully in-lined by compilers.
23 * Added an API for real-time clocks (RTC).
29 - Introduction of 3 new test harnesses into twister supporting pyTest,
31 - Transitioning to new Ztest API was completed and legacy Ztest was deprecated.
46 * CVE-2023-1901: Under embargo until 2023-07-04
48 * CVE-2023-1902: Under embargo until 2023-07-04
67 +--------------------------------------------------+
69 +--------------------------------------------------+
71 +--------------------------------------------------+
[all …]
Drelease-notes-2.4.rst33 * CVE-2020-10060: UpdateHub Might Dereference An Uninitialized Pointer
34 * CVE-2020-10064: Improper Input Frame Validation in ieee802154 Processing
35 * CVE-2020-10066: Incorrect Error Handling in Bluetooth HCI core
36 * CVE-2020-10072: all threads can access all socket file descriptors
37 * CVE-2020-13598: FS: Buffer Overflow when enabling Long File Names in FAT_FS and calling fs_stat
38 * CVE-2020-13599: Security problem with settings and littlefs
39 * CVE-2020-13601: Under embargo until 2020/11/18
40 * CVE-2020-13602: Remote Denial of Service in LwM2M do_write_op_tlv
50 <https://github.com/zephyrproject-rtos/zephyr/issues?q=is%3Aissue+is%3Aopen+label%3Abug>`_.
62 * The :c:func:`wdt_feed` function will now return ``-EAGAIN`` if
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/Zephyr-latest/boards/microchip/mec15xxevb_assy6853/doc/
Dindex.rst10 MEC150x except for an enhanced Boot-ROM SPI loader. The SPI image format has
18 - MEC1521HA0SZ ARM Cortex-M4 Processor
19 - 256 KB RAM and 64 KB boot ROM
20 - Keyboard interface
21 - ADC & GPIO headers
22 - UART0, UART1, and UART2
23 - FAN0, FAN1, FAN2 headers
24 - FAN PWM interface
25 - JTAG/SWD, ETM and MCHP Trace ports
26 - PECI interface 3.0
[all …]
/Zephyr-latest/boards/espressif/esp_wrover_kit/doc/
Dindex.rst6 ESP-WROVER-KIT is an ESP32-based development board produced by `Espressif <https://www.espressif.co…
8 ESP-WROVER-KIT features the following integrated components:
10 - ESP32-WROVER-E module
11 - LCD screen
12 - MicroSD card slot
14 Its another distinguishing feature is the embedded FTDI FT2232HL chip - an advanced multi-interface
16 without a separate JTAG debugger. ESP-WROVER-KIT makes development convenient, easy, and
17 cost-effective.
26 For more information, check `ESP32-WROVER-E Datasheet`_ and `ESP32 Datasheet`_.
31 The block diagram below shows the main components of ESP-WROVER-KIT and their interconnections.
[all …]

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