Searched +full:counter +full:- +full:size (Results 1 – 25 of 228) sorted by relevance
12345678910
| /Zephyr-Core-3.5.0/dts/arm/infineon/psoc6/psoc6_02/ |
| D | psoc6_02.dtsi | 5 * SPDX-License-Identifier: Apache-2.0
12 #address-cells = <1>;
13 #size-cells = <0>;
17 compatible = "arm,cortex-m0+";
22 compatible = "arm,cortex-m4f";
27 flash-controller@40240000 {
28 compatible = "infineon,cat1-flash-controller";
30 #address-cells = <1>;
31 #size-cells = <1>;
34 compatible = "soc-nv-flash";
[all …]
|
| /Zephyr-Core-3.5.0/dts/arm/infineon/psoc6/psoc6_01/ |
| D | psoc6_01.dtsi | 5 * SPDX-License-Identifier: Apache-2.0
12 #address-cells = <1>;
13 #size-cells = <0>;
17 compatible = "arm,cortex-m0+";
22 compatible = "arm,cortex-m4f";
27 flash-controller@40250000 {
28 compatible = "infineon,cat1-flash-controller";
30 #address-cells = <1>;
31 #size-cells = <1>;
34 compatible = "soc-nv-flash";
[all …]
|
| /Zephyr-Core-3.5.0/drivers/watchdog/ |
| D | Kconfig.nxp_fs26 | 2 # SPDX-License-Identifier: Apache-2.0
23 int "Watchdog error counter limit"
26 Sets the maximum value of the watchdog error counter. Each time a
27 watchdog failure occurs, the device increments this counter by 2. The
28 watchdog error counter is decremented by 1 each time the watchdog is
34 int "Watchdog refresh counter limit"
37 Sets the maximum value of the watchdog refresh counter. Each time the
38 watchdog is properly refreshed, this counter is incremented by 1. Each
39 time this counter reaches its maximum value and if the next refresh is
40 also good, the fault error counter is decremented by 1. Each time
[all …]
|
| /Zephyr-Core-3.5.0/dts/bindings/sensor/ |
| D | espressif,esp32-pcnt.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 Espressif's Pulse Counter Mode (PCNT) controller Node
8 The pulse counter module is designed to count the number of
14 Each pulse counter unit has a 16-bit signed counter register.
17 to either increment or decrement the counter.
23 Each pulse counter unit also features a filter on each of the four inputs,
29 Example: Use PCNT to read a rotary-enconder
38 bias-pull-up;
43 Note: Check espressif,esp32-pinctrl.yaml for complete documentation regarding pinctrl.
48 pinctrl-0 = <&pcnt_default>;
[all …]
|
| /Zephyr-Core-3.5.0/dts/arm/st/l0/ |
| D | stm32l071.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
11 compatible = "st,stm32l071", "st,stm32l0", "simple-bus";
13 pinctrl: pin-controller@50000000 {
15 compatible = "st,stm32-gpio";
16 gpio-controller;
17 #gpio-cells = <2>;
24 compatible = "st,stm32-i2c-v2";
25 clock-frequency = <I2C_BITRATE_STANDARD>;
26 #address-cells = <1>;
27 #size-cells = <0>;
[all …]
|
| /Zephyr-Core-3.5.0/dts/arm/st/f2/ |
| D | stm32f2.dtsi | 5 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv7-m.dtsi>
9 #include <zephyr/dt-bindings/clock/stm32f4_clock.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/pwm/pwm.h>
13 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
14 #include <zephyr/dt-bindings/dma/stm32_dma.h>
15 #include <zephyr/dt-bindings/adc/stm32f4_adc.h>
16 #include <zephyr/dt-bindings/reset/stm32f2_4_7_reset.h>
[all …]
|
| /Zephyr-Core-3.5.0/dts/arm/st/h5/ |
| D | stm32h562.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/flash_controller/ospi.h>
14 #clock-cells = <0>;
15 compatible = "st,stm32u5-pll-clock";
21 compatible = "st,stm32h562", "st,stm32h5", "simple-bus";
23 pinctrl: pin-controller@42020000 {
25 compatible = "st,stm32-gpio";
26 gpio-controller;
27 #gpio-cells = <2>;
33 compatible = "st,stm32-gpio";
[all …]
|
| /Zephyr-Core-3.5.0/dts/arm/st/f3/ |
| D | stm32f3.dtsi | 2 * Copyright (c) 2017 I-SENSE group of ICCS
5 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv7-m.dtsi>
9 #include <zephyr/dt-bindings/clock/stm32f3_clock.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/pwm/pwm.h>
13 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
14 #include <zephyr/dt-bindings/dma/stm32_dma.h>
15 #include <zephyr/dt-bindings/reset/stm32f0_1_3_reset.h>
[all …]
|
| /Zephyr-Core-3.5.0/dts/arm/st/f7/ |
| D | stm32f7.dtsi | 5 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv7-m.dtsi>
9 #include <zephyr/dt-bindings/clock/stm32f7_clock.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/pwm/pwm.h>
13 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
14 #include <zephyr/dt-bindings/dma/stm32_dma.h>
15 #include <zephyr/dt-bindings/adc/stm32f4_adc.h>
16 #include <zephyr/dt-bindings/reset/stm32f2_4_7_reset.h>
[all …]
|
| /Zephyr-Core-3.5.0/dts/arm/st/l4/ |
| D | stm32l4p5.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/flash_controller/ospi.h>
11 /delete-node/ &quadspi;
19 compatible = "st,stm32l4p5", "st,stm32l4", "simple-bus";
22 clk_hsi48: clk-hsi48 {
23 #clock-cells = <0>;
24 compatible = "fixed-clock";
25 clock-frequency = <DT_FREQ_M(48)>;
30 flash-controller@40022000 {
32 erase-block-size = <4096>;
[all …]
|
| D | stm32l471.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
11 compatible = "st,stm32l471", "st,stm32l4", "simple-bus";
13 pinctrl: pin-controller@48000000 {
16 compatible = "st,stm32-gpio";
17 gpio-controller;
18 #gpio-cells = <2>;
24 compatible = "st,stm32-gpio";
25 gpio-controller;
26 #gpio-cells = <2>;
32 compatible = "st,stm32-gpio";
[all …]
|
| /Zephyr-Core-3.5.0/dts/arm/st/f4/ |
| D | stm32f412.dtsi | 2 * Copyright (c) 2017 Florian Vaussard, HEIG-VD
4 * SPDX-License-Identifier: Apache-2.0
9 /delete-node/ &dac1;
10 /delete-node/ &rng;
15 #clock-cells = <0>;
16 compatible = "st,stm32f412-plli2s-clock";
22 compatible = "st,stm32f412", "st,stm32f4", "simple-bus";
24 pinctrl: pin-controller@40020000 {
28 compatible = "st,stm32-gpio";
29 gpio-controller;
[all …]
|
| D | stm32f4.dtsi | 6 * SPDX-License-Identifier: Apache-2.0
9 #include <arm/armv7-m.dtsi>
10 #include <zephyr/dt-bindings/adc/adc.h>
11 #include <zephyr/dt-bindings/clock/stm32f4_clock.h>
12 #include <zephyr/dt-bindings/i2c/i2c.h>
13 #include <zephyr/dt-bindings/gpio/gpio.h>
14 #include <zephyr/dt-bindings/pwm/pwm.h>
15 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
16 #include <zephyr/dt-bindings/dma/stm32_dma.h>
17 #include <zephyr/dt-bindings/adc/stm32f4_adc.h>
[all …]
|
| D | stm32f410.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/clock/stm32f410_clock.h>
16 compatible = "st,stm32f410", "st,stm32f4", "simple-bus";
19 compatible = "st,stm32-spi";
20 #address-cells = <1>;
21 #size-cells = <0>;
29 compatible = "st,stm32-spi";
30 #address-cells = <1>;
31 #size-cells = <0>;
39 compatible = "st,stm32-i2s";
[all …]
|
| /Zephyr-Core-3.5.0/dts/arm/st/wba/ |
| D | stm32wba.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv8-m.dtsi>
9 #include <zephyr/dt-bindings/clock/stm32wba_clock.h>
10 #include <zephyr/dt-bindings/reset/stm32wba_reset.h>
11 #include <zephyr/dt-bindings/adc/stm32u5_adc.h>
12 #include <zephyr/dt-bindings/gpio/gpio.h>
13 #include <zephyr/dt-bindings/i2c/i2c.h>
14 #include <zephyr/dt-bindings/pwm/pwm.h>
15 #include <zephyr/dt-bindings/adc/adc.h>
22 zephyr,flash-controller = &flash;
[all …]
|
| /Zephyr-Core-3.5.0/dts/arm/st/l1/ |
| D | stm32l1.dtsi | 5 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv7-m.dtsi>
9 #include <zephyr/dt-bindings/clock/stm32l1_clock.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #include <zephyr/dt-bindings/i2c/i2c.h>
12 #include <zephyr/dt-bindings/pwm/pwm.h>
13 #include <zephyr/dt-bindings/adc/adc.h>
14 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
15 #include <zephyr/dt-bindings/dma/stm32_dma.h>
16 #include <zephyr/dt-bindings/adc/stm32f4_adc.h>
[all …]
|
| /Zephyr-Core-3.5.0/dts/arm/st/f0/ |
| D | stm32f0.dtsi | 5 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv6-m.dtsi>
9 #include <zephyr/dt-bindings/clock/stm32f0_clock.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/pwm/pwm.h>
13 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
14 #include <zephyr/dt-bindings/dma/stm32_dma.h>
15 #include <zephyr/dt-bindings/adc/stm32l4_adc.h>
16 #include <zephyr/dt-bindings/reset/stm32f0_1_3_reset.h>
[all …]
|
| /Zephyr-Core-3.5.0/dts/bindings/pwm/ |
| D | atmel,sam0-tcc-pwm.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "atmel,sam0-tcc-pwm"
9 - name: base.yaml
10 - name: pwm-controller.yaml
11 - name: pinctrl-device.yaml
23 clock-names:
31 - 2
32 - 3
33 - 4
34 - 6
[all …]
|
| /Zephyr-Core-3.5.0/dts/arm/st/g0/ |
| D | stm32g0.dtsi | 6 * Copyright (c) 2021 G-Technologies Sdn. Bhd.
8 * SPDX-License-Identifier: Apache-2.0
11 #include <arm/armv6-m.dtsi>
12 #include <zephyr/dt-bindings/clock/stm32g0_clock.h>
13 #include <zephyr/dt-bindings/gpio/gpio.h>
14 #include <zephyr/dt-bindings/i2c/i2c.h>
15 #include <zephyr/dt-bindings/pwm/pwm.h>
16 #include <zephyr/dt-bindings/dma/stm32_dma.h>
17 #include <zephyr/dt-bindings/adc/adc.h>
18 #include <zephyr/dt-bindings/adc/stm32l4_adc.h>
[all …]
|
| /Zephyr-Core-3.5.0/dts/arm/atmel/ |
| D | saml21.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
12 compatible = "atmel,sam0-usb";
16 num-bidir-endpoints = <8>;
20 compatible = "atmel,sam0-dmac";
23 #dma-cells = <2>;
27 compatible = "atmel,sam0-tcc";
31 clock-names = "GCLK", "MCLK";
34 counter-size = <24>;
38 compatible = "atmel,sam0-tcc";
42 clock-names = "GCLK", "MCLK";
[all …]
|
| D | samr21.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
11 port-c = &portc;
16 compatible = "atmel,sam0-usb";
20 num-bidir-endpoints = <8>;
24 compatible = "atmel,sam0-dmac";
27 #dma-cells = <2>;
34 compatible = "atmel,sam0-gpio";
36 gpio-controller;
37 #gpio-cells = <2>;
38 #atmel,pin-cells = <2>;
[all …]
|
| D | samd21.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
11 tc-6 = &tc6;
16 compatible = "atmel,sam0-usb";
20 num-bidir-endpoints = <8>;
24 compatible = "atmel,sam0-dmac";
27 #dma-cells = <2>;
31 compatible = "atmel,sam0-tc32";
35 clock-names = "GCLK", "PM";
39 compatible = "atmel,sam0-tcc";
43 clock-names = "GCLK", "PM";
[all …]
|
| /Zephyr-Core-3.5.0/dts/arm/st/h7/ |
| D | stm32h7.dtsi | 6 * SPDX-License-Identifier: Apache-2.0
9 #include <arm/armv7-m.dtsi>
10 #include <zephyr/dt-bindings/clock/stm32h7_clock.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/i2c/i2c.h>
13 #include <zephyr/dt-bindings/pwm/pwm.h>
14 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
15 #include <zephyr/dt-bindings/dma/stm32_dma.h>
16 #include <zephyr/dt-bindings/adc/stm32h7_adc.h>
17 #include <zephyr/dt-bindings/reset/stm32h7_reset.h>
[all …]
|
| /Zephyr-Core-3.5.0/dts/arm/st/l5/ |
| D | stm32l5.dtsi | 5 * SPDX-License-Identifier: Apache-2.0
9 #include <arm/armv8-m.dtsi>
10 #include <zephyr/dt-bindings/clock/stm32l4_clock.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/i2c/i2c.h>
13 #include <zephyr/dt-bindings/pwm/pwm.h>
14 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
15 #include <zephyr/dt-bindings/dma/stm32_dma.h>
16 #include <zephyr/dt-bindings/adc/stm32l4_adc.h>
17 #include <zephyr/dt-bindings/reset/stm32g4_l4_5_reset.h>
[all …]
|
| /Zephyr-Core-3.5.0/dts/arm/st/g4/ |
| D | stm32g4.dtsi | 5 * SPDX-License-Identifier: Apache-2.0
9 #include <arm/armv7-m.dtsi>
10 #include <zephyr/dt-bindings/clock/stm32g4_clock.h>
11 #include <zephyr/dt-bindings/i2c/i2c.h>
12 #include <zephyr/dt-bindings/gpio/gpio.h>
13 #include <zephyr/dt-bindings/pwm/pwm.h>
14 #include <zephyr/dt-bindings/adc/adc.h>
15 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
16 #include <zephyr/dt-bindings/dma/stm32_dma.h>
17 #include <zephyr/dt-bindings/adc/stm32l4_adc.h>
[all …]
|
12345678910
