1/* 2 * Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or 3 * an affiliate of Cypress Semiconductor Corporation 4 * 5 * SPDX-License-Identifier: Apache-2.0 6 */ 7 8#include <mem.h> 9 10/ { 11 cpus { 12 #address-cells = <1>; 13 #size-cells = <0>; 14 15 cpu@0 { 16 device_type = "cpu"; 17 compatible = "arm,cortex-m0+"; 18 reg = <0>; 19 }; 20 cpu@1 { 21 device_type = "cpu"; 22 compatible = "arm,cortex-m4f"; 23 reg = <1>; 24 }; 25 }; 26 27 flash-controller@40250000 { 28 compatible = "infineon,cat1-flash-controller"; 29 reg = < 0x40250000 0x10000 >; 30 #address-cells = <1>; 31 #size-cells = <1>; 32 33 flash0: flash@10000000 { 34 compatible = "soc-nv-flash"; 35 reg = <0x10000000 0x100000>; 36 write-block-size = <512>; 37 erase-block-size = <512>; 38 }; 39 flash1: flash@14000000 { 40 compatible = "soc-nv-flash"; 41 reg = <0x14000000 0x8000>; 42 write-block-size = <512>; 43 erase-block-size = <512>; 44 }; 45 }; 46 47 sram0: memory@8000000 { 48 compatible = "mmio-sram"; 49 reg = <0x8000000 0x48000>; 50 }; 51 52 soc { 53 pinctrl: pinctrl@40310000 { 54 compatible = "infineon,cat1-pinctrl"; 55 reg = <0x40310000 0x20000>; 56 #address-cells = <1>; 57 #size-cells = <0>; 58 59 hsiom: hsiom@40310000 { 60 compatible = "infineon,cat1-hsiom"; 61 reg = <0x40310000 0x4000>; 62 interrupts = <15 6>, <16 6>; 63 status = "disabled"; 64 }; 65 66 gpio_prt0: gpio@40320000 { 67 compatible = "infineon,cat1-gpio"; 68 reg = <0x40320000 0x80>; 69 interrupts = <0 6>; 70 gpio-controller; 71 ngpios = <6>; 72 status = "disabled"; 73 #gpio-cells = <2>; 74 }; 75 gpio_prt1: gpio@40320080 { 76 compatible = "infineon,cat1-gpio"; 77 reg = <0x40320080 0x80>; 78 interrupts = <1 6>; 79 gpio-controller; 80 ngpios = <6>; 81 status = "disabled"; 82 #gpio-cells = <2>; 83 }; 84 gpio_prt2: gpio@40320100 { 85 compatible = "infineon,cat1-gpio"; 86 reg = <0x40320100 0x80>; 87 interrupts = <2 6>; 88 gpio-controller; 89 ngpios = <8>; 90 status = "disabled"; 91 #gpio-cells = <2>; 92 }; 93 gpio_prt3: gpio@40320180 { 94 compatible = "infineon,cat1-gpio"; 95 reg = <0x40320180 0x80>; 96 interrupts = <3 6>; 97 gpio-controller; 98 ngpios = <6>; 99 status = "disabled"; 100 #gpio-cells = <2>; 101 }; 102 gpio_prt4: gpio@40320200 { 103 compatible = "infineon,cat1-gpio"; 104 reg = <0x40320200 0x80>; 105 interrupts = <4 6>; 106 gpio-controller; 107 ngpios = <2>; 108 status = "disabled"; 109 #gpio-cells = <2>; 110 }; 111 gpio_prt5: gpio@40320280 { 112 compatible = "infineon,cat1-gpio"; 113 reg = <0x40320280 0x80>; 114 interrupts = <5 6>; 115 gpio-controller; 116 ngpios = <8>; 117 status = "disabled"; 118 #gpio-cells = <2>; 119 }; 120 gpio_prt6: gpio@40320300 { 121 compatible = "infineon,cat1-gpio"; 122 reg = <0x40320300 0x80>; 123 interrupts = <6 6>; 124 gpio-controller; 125 ngpios = <8>; 126 status = "disabled"; 127 #gpio-cells = <2>; 128 }; 129 gpio_prt7: gpio@40320380 { 130 compatible = "infineon,cat1-gpio"; 131 reg = <0x40320380 0x80>; 132 interrupts = <7 6>; 133 gpio-controller; 134 ngpios = <8>; 135 status = "disabled"; 136 #gpio-cells = <2>; 137 }; 138 gpio_prt8: gpio@40320400 { 139 compatible = "infineon,cat1-gpio"; 140 reg = <0x40320400 0x80>; 141 interrupts = <8 6>; 142 gpio-controller; 143 ngpios = <8>; 144 status = "disabled"; 145 #gpio-cells = <2>; 146 }; 147 gpio_prt9: gpio@40320480 { 148 compatible = "infineon,cat1-gpio"; 149 reg = <0x40320480 0x80>; 150 interrupts = <9 6>; 151 gpio-controller; 152 ngpios = <8>; 153 status = "disabled"; 154 #gpio-cells = <2>; 155 }; 156 gpio_prt10: gpio@40320500 { 157 compatible = "infineon,cat1-gpio"; 158 reg = <0x40320500 0x80>; 159 interrupts = <10 6>; 160 gpio-controller; 161 ngpios = <8>; 162 status = "disabled"; 163 #gpio-cells = <2>; 164 }; 165 gpio_prt11: gpio@40320580 { 166 compatible = "infineon,cat1-gpio"; 167 reg = <0x40320580 0x80>; 168 interrupts = <11 6>; 169 gpio-controller; 170 ngpios = <8>; 171 status = "disabled"; 172 #gpio-cells = <2>; 173 }; 174 gpio_prt12: gpio@40320600 { 175 compatible = "infineon,cat1-gpio"; 176 reg = <0x40320600 0x80>; 177 interrupts = <12 6>; 178 gpio-controller; 179 ngpios = <8>; 180 status = "disabled"; 181 #gpio-cells = <2>; 182 }; 183 gpio_prt13: gpio@40320680 { 184 compatible = "infineon,cat1-gpio"; 185 reg = <0x40320680 0x80>; 186 interrupts = <13 6>; 187 gpio-controller; 188 ngpios = <8>; 189 status = "disabled"; 190 #gpio-cells = <2>; 191 }; 192 gpio_prt14: gpio@40320700 { 193 compatible = "infineon,cat1-gpio"; 194 reg = <0x40320700 0x80>; 195 interrupts = <14 6>; 196 gpio-controller; 197 ngpios = <2>; 198 status = "disabled"; 199 #gpio-cells = <2>; 200 }; 201 }; 202 uid: device_uid@16000600 { 203 compatible = "infineon,cat1-uid"; 204 reg = <0x16000600 0xb>; 205 status = "disabled"; 206 }; 207 208 adc0: adc@411d0000 { 209 compatible = "infineon,cat1-adc"; 210 reg = <0x411d0000 0x10000>; 211 interrupts = <138 6>; 212 status = "disabled"; 213 #io-channel-cells = <1>; 214 }; 215 216 scb0: scb@40610000 { 217 compatible = "infineon,cat1-scb"; 218 reg = <0x40610000 0x10000>; 219 #address-cells = <1>; 220 #size-cells = <0>; 221 interrupts = <41 6>; 222 status = "disabled"; 223 }; 224 scb1: scb@40620000 { 225 compatible = "infineon,cat1-scb"; 226 reg = <0x40620000 0x10000>; 227 #address-cells = <1>; 228 #size-cells = <0>; 229 interrupts = <42 6>; 230 status = "disabled"; 231 }; 232 scb2: scb@40630000 { 233 compatible = "infineon,cat1-scb"; 234 reg = <0x40630000 0x10000>; 235 #address-cells = <1>; 236 #size-cells = <0>; 237 interrupts = <43 6>; 238 status = "disabled"; 239 }; 240 scb3: scb@40640000 { 241 compatible = "infineon,cat1-scb"; 242 reg = <0x40640000 0x10000>; 243 #address-cells = <1>; 244 #size-cells = <0>; 245 interrupts = <44 6>; 246 status = "disabled"; 247 }; 248 scb4: scb@40650000 { 249 compatible = "infineon,cat1-scb"; 250 reg = <0x40650000 0x10000>; 251 #address-cells = <1>; 252 #size-cells = <0>; 253 interrupts = <45 6>; 254 status = "disabled"; 255 }; 256 scb5: scb@40660000 { 257 compatible = "infineon,cat1-scb"; 258 reg = <0x40660000 0x10000>; 259 #address-cells = <1>; 260 #size-cells = <0>; 261 interrupts = <46 6>; 262 status = "disabled"; 263 }; 264 scb6: scb@40670000 { 265 compatible = "infineon,cat1-scb"; 266 reg = <0x40670000 0x10000>; 267 #address-cells = <1>; 268 #size-cells = <0>; 269 interrupts = <47 6>; 270 status = "disabled"; 271 }; 272 scb7: scb@40680000 { 273 compatible = "infineon,cat1-scb"; 274 reg = <0x40680000 0x10000>; 275 #address-cells = <1>; 276 #size-cells = <0>; 277 interrupts = <48 6>; 278 status = "disabled"; 279 }; 280 scb8: scb@40690000 { 281 compatible = "infineon,cat1-scb"; 282 reg = <0x40690000 0x10000>; 283 #address-cells = <1>; 284 #size-cells = <0>; 285 interrupts = <18 6>; 286 status = "disabled"; 287 }; 288 289 timer0: timer@40260200 { 290 compatible = "infineon,cat1-timer"; 291 reg = <0x40260200 0x40>; 292 interrupts = <19 6>; 293 status = "disabled"; 294 }; 295 timer1: timer@40260240 { 296 compatible = "infineon,cat1-timer"; 297 reg = <0x40260240 0x40>; 298 interrupts = <20 6>; 299 status = "disabled"; 300 }; 301 302 watchdog0: watchdog@40260180 { 303 compatible = "infineon,cat1-watchdog"; 304 reg = <0x40260180 0xc>; 305 interrupts = <22 6>; 306 status = "disabled"; 307 }; 308 309 bluetooth: bless { 310 compatible = "infineon,cat1-bless-hci"; 311 interrupts = <24 1>; 312 status = "disabled"; 313 }; 314 315 counter0_0: counter@40380100 { 316 compatible = "infineon,cat1-counter"; 317 reg = <0x40380100 0x40>; 318 interrupts = <90 6>; 319 resolution = <32>; 320 status = "disabled"; 321 }; 322 counter0_1: counter@40380140 { 323 compatible = "infineon,cat1-counter"; 324 reg = <0x40380140 0x40>; 325 interrupts = <91 6>; 326 resolution = <32>; 327 status = "disabled"; 328 }; 329 counter0_2: counter@40380180 { 330 compatible = "infineon,cat1-counter"; 331 reg = <0x40380180 0x40>; 332 interrupts = <92 6>; 333 resolution = <32>; 334 status = "disabled"; 335 }; 336 counter0_3: counter@403801c0 { 337 compatible = "infineon,cat1-counter"; 338 reg = <0x403801c0 0x40>; 339 interrupts = <93 6>; 340 resolution = <32>; 341 status = "disabled"; 342 }; 343 counter0_4: counter@40380200 { 344 compatible = "infineon,cat1-counter"; 345 reg = <0x40380200 0x40>; 346 interrupts = <94 6>; 347 resolution = <32>; 348 status = "disabled"; 349 }; 350 counter0_5: counter@40380240 { 351 compatible = "infineon,cat1-counter"; 352 reg = <0x40380240 0x40>; 353 interrupts = <95 6>; 354 resolution = <32>; 355 status = "disabled"; 356 }; 357 counter0_6: counter@40380280 { 358 compatible = "infineon,cat1-counter"; 359 reg = <0x40380280 0x40>; 360 interrupts = <96 6>; 361 resolution = <32>; 362 status = "disabled"; 363 }; 364 counter0_7: counter@403802c0 { 365 compatible = "infineon,cat1-counter"; 366 reg = <0x403802c0 0x40>; 367 interrupts = <97 6>; 368 resolution = <32>; 369 status = "disabled"; 370 }; 371 counter1_0: counter@40390100 { 372 compatible = "infineon,cat1-counter"; 373 reg = <0x40390100 0x40>; 374 interrupts = <98 6>; 375 resolution = <16>; 376 status = "disabled"; 377 }; 378 counter1_1: counter@40390140 { 379 compatible = "infineon,cat1-counter"; 380 reg = <0x40390140 0x40>; 381 interrupts = <99 6>; 382 resolution = <16>; 383 status = "disabled"; 384 }; 385 counter1_2: counter@40390180 { 386 compatible = "infineon,cat1-counter"; 387 reg = <0x40390180 0x40>; 388 interrupts = <100 6>; 389 resolution = <16>; 390 status = "disabled"; 391 }; 392 counter1_3: counter@403901c0 { 393 compatible = "infineon,cat1-counter"; 394 reg = <0x403901c0 0x40>; 395 interrupts = <101 6>; 396 resolution = <16>; 397 status = "disabled"; 398 }; 399 counter1_4: counter@40390200 { 400 compatible = "infineon,cat1-counter"; 401 reg = <0x40390200 0x40>; 402 interrupts = <102 6>; 403 resolution = <16>; 404 status = "disabled"; 405 }; 406 counter1_5: counter@40390240 { 407 compatible = "infineon,cat1-counter"; 408 reg = <0x40390240 0x40>; 409 interrupts = <103 6>; 410 resolution = <16>; 411 status = "disabled"; 412 }; 413 counter1_6: counter@40390280 { 414 compatible = "infineon,cat1-counter"; 415 reg = <0x40390280 0x40>; 416 interrupts = <104 6>; 417 resolution = <16>; 418 status = "disabled"; 419 }; 420 counter1_7: counter@403902c0 { 421 compatible = "infineon,cat1-counter"; 422 reg = <0x403902c0 0x40>; 423 interrupts = <105 6>; 424 resolution = <16>; 425 status = "disabled"; 426 }; 427 counter1_8: counter@40390300 { 428 compatible = "infineon,cat1-counter"; 429 reg = <0x40390300 0x40>; 430 interrupts = <106 6>; 431 resolution = <16>; 432 status = "disabled"; 433 }; 434 counter1_9: counter@40390340 { 435 compatible = "infineon,cat1-counter"; 436 reg = <0x40390340 0x40>; 437 interrupts = <107 6>; 438 resolution = <16>; 439 status = "disabled"; 440 }; 441 counter1_10: counter@40390380 { 442 compatible = "infineon,cat1-counter"; 443 reg = <0x40390380 0x40>; 444 interrupts = <108 6>; 445 resolution = <16>; 446 status = "disabled"; 447 }; 448 counter1_11: counter@403903c0 { 449 compatible = "infineon,cat1-counter"; 450 reg = <0x403903c0 0x40>; 451 interrupts = <109 6>; 452 resolution = <16>; 453 status = "disabled"; 454 }; 455 counter1_12: counter@40390400 { 456 compatible = "infineon,cat1-counter"; 457 reg = <0x40390400 0x40>; 458 interrupts = <110 6>; 459 resolution = <16>; 460 status = "disabled"; 461 }; 462 counter1_13: counter@40390440 { 463 compatible = "infineon,cat1-counter"; 464 reg = <0x40390440 0x40>; 465 interrupts = <111 6>; 466 resolution = <16>; 467 status = "disabled"; 468 }; 469 counter1_14: counter@40390480 { 470 compatible = "infineon,cat1-counter"; 471 reg = <0x40390480 0x40>; 472 interrupts = <112 6>; 473 resolution = <16>; 474 status = "disabled"; 475 }; 476 counter1_15: counter@403904c0 { 477 compatible = "infineon,cat1-counter"; 478 reg = <0x403904c0 0x40>; 479 interrupts = <113 6>; 480 resolution = <16>; 481 status = "disabled"; 482 }; 483 counter1_16: counter@40390500 { 484 compatible = "infineon,cat1-counter"; 485 reg = <0x40390500 0x40>; 486 interrupts = <114 6>; 487 resolution = <16>; 488 status = "disabled"; 489 }; 490 counter1_17: counter@40390540 { 491 compatible = "infineon,cat1-counter"; 492 reg = <0x40390540 0x40>; 493 interrupts = <115 6>; 494 resolution = <16>; 495 status = "disabled"; 496 }; 497 counter1_18: counter@40390580 { 498 compatible = "infineon,cat1-counter"; 499 reg = <0x40390580 0x40>; 500 interrupts = <116 6>; 501 resolution = <16>; 502 status = "disabled"; 503 }; 504 counter1_19: counter@403905c0 { 505 compatible = "infineon,cat1-counter"; 506 reg = <0x403905c0 0x40>; 507 interrupts = <117 6>; 508 resolution = <16>; 509 status = "disabled"; 510 }; 511 counter1_20: counter@40390600 { 512 compatible = "infineon,cat1-counter"; 513 reg = <0x40390600 0x40>; 514 interrupts = <118 6>; 515 resolution = <16>; 516 status = "disabled"; 517 }; 518 counter1_21: counter@40390640 { 519 compatible = "infineon,cat1-counter"; 520 reg = <0x40390640 0x40>; 521 interrupts = <119 6>; 522 resolution = <16>; 523 status = "disabled"; 524 }; 525 counter1_22: counter@40390680 { 526 compatible = "infineon,cat1-counter"; 527 reg = <0x40390680 0x40>; 528 interrupts = <120 6>; 529 resolution = <16>; 530 status = "disabled"; 531 }; 532 counter1_23: counter@403906c0 { 533 compatible = "infineon,cat1-counter"; 534 reg = <0x403906c0 0x40>; 535 interrupts = <121 6>; 536 resolution = <16>; 537 status = "disabled"; 538 }; 539 }; 540}; 541
