1/* 2 * Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or 3 * an affiliate of Cypress Semiconductor Corporation 4 * 5 * SPDX-License-Identifier: Apache-2.0 6 */ 7 8#include <mem.h> 9 10/ { 11 cpus { 12 #address-cells = <1>; 13 #size-cells = <0>; 14 15 cpu@0 { 16 device_type = "cpu"; 17 compatible = "arm,cortex-m0+"; 18 reg = <0>; 19 }; 20 cpu@1 { 21 device_type = "cpu"; 22 compatible = "arm,cortex-m4f"; 23 reg = <1>; 24 }; 25 }; 26 27 flash-controller@40240000 { 28 compatible = "infineon,cat1-flash-controller"; 29 reg = < 0x40240000 0x10000 >; 30 #address-cells = <1>; 31 #size-cells = <1>; 32 33 flash0: flash@10000000 { 34 compatible = "soc-nv-flash"; 35 reg = <0x10000000 0x200000>; 36 write-block-size = <512>; 37 erase-block-size = <512>; 38 }; 39 flash1: flash@14000000 { 40 compatible = "soc-nv-flash"; 41 reg = <0x14000000 0x8000>; 42 write-block-size = <512>; 43 erase-block-size = <512>; 44 }; 45 }; 46 47 sram0: memory@8000000 { 48 compatible = "mmio-sram"; 49 reg = <0x8000000 0x100000>; 50 }; 51 52 soc { 53 pinctrl: pinctrl@40300000 { 54 compatible = "infineon,cat1-pinctrl"; 55 reg = <0x40300000 0x20000>; 56 #address-cells = <1>; 57 #size-cells = <0>; 58 59 hsiom: hsiom@40300000 { 60 compatible = "infineon,cat1-hsiom"; 61 reg = <0x40300000 0x4000>; 62 interrupts = <15 6>, <16 6>; 63 status = "disabled"; 64 }; 65 66 gpio_prt0: gpio@40310000 { 67 compatible = "infineon,cat1-gpio"; 68 reg = <0x40310000 0x80>; 69 interrupts = <0 6>; 70 gpio-controller; 71 ngpios = <6>; 72 status = "disabled"; 73 #gpio-cells = <2>; 74 }; 75 gpio_prt1: gpio@40310080 { 76 compatible = "infineon,cat1-gpio"; 77 reg = <0x40310080 0x80>; 78 interrupts = <1 6>; 79 gpio-controller; 80 ngpios = <6>; 81 status = "disabled"; 82 #gpio-cells = <2>; 83 }; 84 gpio_prt2: gpio@40310100 { 85 compatible = "infineon,cat1-gpio"; 86 reg = <0x40310100 0x80>; 87 interrupts = <2 6>; 88 gpio-controller; 89 ngpios = <8>; 90 status = "disabled"; 91 #gpio-cells = <2>; 92 }; 93 gpio_prt3: gpio@40310180 { 94 compatible = "infineon,cat1-gpio"; 95 reg = <0x40310180 0x80>; 96 interrupts = <3 6>; 97 gpio-controller; 98 ngpios = <6>; 99 status = "disabled"; 100 #gpio-cells = <2>; 101 }; 102 gpio_prt4: gpio@40310200 { 103 compatible = "infineon,cat1-gpio"; 104 reg = <0x40310200 0x80>; 105 interrupts = <4 6>; 106 gpio-controller; 107 ngpios = <2>; 108 status = "disabled"; 109 #gpio-cells = <2>; 110 }; 111 gpio_prt5: gpio@40310280 { 112 compatible = "infineon,cat1-gpio"; 113 reg = <0x40310280 0x80>; 114 interrupts = <5 6>; 115 gpio-controller; 116 ngpios = <8>; 117 status = "disabled"; 118 #gpio-cells = <2>; 119 }; 120 gpio_prt6: gpio@40310300 { 121 compatible = "infineon,cat1-gpio"; 122 reg = <0x40310300 0x80>; 123 interrupts = <6 6>; 124 gpio-controller; 125 ngpios = <8>; 126 status = "disabled"; 127 #gpio-cells = <2>; 128 }; 129 gpio_prt7: gpio@40310380 { 130 compatible = "infineon,cat1-gpio"; 131 reg = <0x40310380 0x80>; 132 interrupts = <7 6>; 133 gpio-controller; 134 ngpios = <8>; 135 status = "disabled"; 136 #gpio-cells = <2>; 137 }; 138 gpio_prt8: gpio@40310400 { 139 compatible = "infineon,cat1-gpio"; 140 reg = <0x40310400 0x80>; 141 interrupts = <8 6>; 142 gpio-controller; 143 ngpios = <8>; 144 status = "disabled"; 145 #gpio-cells = <2>; 146 }; 147 gpio_prt9: gpio@40310480 { 148 compatible = "infineon,cat1-gpio"; 149 reg = <0x40310480 0x80>; 150 interrupts = <9 6>; 151 gpio-controller; 152 ngpios = <8>; 153 status = "disabled"; 154 #gpio-cells = <2>; 155 }; 156 gpio_prt10: gpio@40310500 { 157 compatible = "infineon,cat1-gpio"; 158 reg = <0x40310500 0x80>; 159 interrupts = <10 6>; 160 gpio-controller; 161 ngpios = <8>; 162 status = "disabled"; 163 #gpio-cells = <2>; 164 }; 165 gpio_prt11: gpio@40310580 { 166 compatible = "infineon,cat1-gpio"; 167 reg = <0x40310580 0x80>; 168 interrupts = <11 6>; 169 gpio-controller; 170 ngpios = <8>; 171 status = "disabled"; 172 #gpio-cells = <2>; 173 }; 174 gpio_prt12: gpio@40310600 { 175 compatible = "infineon,cat1-gpio"; 176 reg = <0x40310600 0x80>; 177 interrupts = <12 6>; 178 gpio-controller; 179 ngpios = <8>; 180 status = "disabled"; 181 #gpio-cells = <2>; 182 }; 183 gpio_prt13: gpio@40310680 { 184 compatible = "infineon,cat1-gpio"; 185 reg = <0x40310680 0x80>; 186 interrupts = <13 6>; 187 gpio-controller; 188 ngpios = <8>; 189 status = "disabled"; 190 #gpio-cells = <2>; 191 }; 192 gpio_prt14: gpio@40310700 { 193 compatible = "infineon,cat1-gpio"; 194 reg = <0x40310700 0x80>; 195 interrupts = <14 6>; 196 gpio-controller; 197 ngpios = <2>; 198 status = "disabled"; 199 #gpio-cells = <2>; 200 }; 201 }; 202 scb0: scb@40600000 { 203 compatible = "infineon,cat1-scb"; 204 reg = <0x40600000 0x10000>; 205 #address-cells = <1>; 206 #size-cells = <0>; 207 interrupts = <39 6>; 208 status = "disabled"; 209 }; 210 scb1: scb@40610000 { 211 compatible = "infineon,cat1-scb"; 212 reg = <0x40610000 0x10000>; 213 #address-cells = <1>; 214 #size-cells = <0>; 215 interrupts = <40 6>; 216 status = "disabled"; 217 }; 218 scb2: scb@40620000 { 219 compatible = "infineon,cat1-scb"; 220 reg = <0x40620000 0x10000>; 221 #address-cells = <1>; 222 #size-cells = <0>; 223 interrupts = <41 6>; 224 status = "disabled"; 225 }; 226 scb3: scb@40630000 { 227 compatible = "infineon,cat1-scb"; 228 reg = <0x40630000 0x10000>; 229 #address-cells = <1>; 230 #size-cells = <0>; 231 interrupts = <42 6>; 232 status = "disabled"; 233 }; 234 scb4: scb@40640000 { 235 compatible = "infineon,cat1-scb"; 236 reg = <0x40640000 0x10000>; 237 #address-cells = <1>; 238 #size-cells = <0>; 239 interrupts = <43 6>; 240 status = "disabled"; 241 }; 242 scb5: scb@40650000 { 243 compatible = "infineon,cat1-scb"; 244 reg = <0x40650000 0x10000>; 245 #address-cells = <1>; 246 #size-cells = <0>; 247 interrupts = <44 6>; 248 status = "disabled"; 249 }; 250 scb6: scb@40660000 { 251 compatible = "infineon,cat1-scb"; 252 reg = <0x40660000 0x10000>; 253 #address-cells = <1>; 254 #size-cells = <0>; 255 interrupts = <45 6>; 256 status = "disabled"; 257 }; 258 scb7: scb@40670000 { 259 compatible = "infineon,cat1-scb"; 260 reg = <0x40670000 0x10000>; 261 #address-cells = <1>; 262 #size-cells = <0>; 263 interrupts = <46 6>; 264 status = "disabled"; 265 }; 266 scb8: scb@40680000 { 267 compatible = "infineon,cat1-scb"; 268 reg = <0x40680000 0x10000>; 269 #address-cells = <1>; 270 #size-cells = <0>; 271 interrupts = <18 6>; 272 status = "disabled"; 273 }; 274 scb9: scb@40690000 { 275 compatible = "infineon,cat1-scb"; 276 reg = <0x40690000 0x10000>; 277 #address-cells = <1>; 278 #size-cells = <0>; 279 interrupts = <47 6>; 280 status = "disabled"; 281 }; 282 scb10: scb@406a0000 { 283 compatible = "infineon,cat1-scb"; 284 reg = <0x406a0000 0x10000>; 285 #address-cells = <1>; 286 #size-cells = <0>; 287 interrupts = <48 6>; 288 status = "disabled"; 289 }; 290 scb11: scb@406b0000 { 291 compatible = "infineon,cat1-scb"; 292 reg = <0x406b0000 0x10000>; 293 #address-cells = <1>; 294 #size-cells = <0>; 295 interrupts = <49 6>; 296 status = "disabled"; 297 }; 298 scb12: scb@406c0000 { 299 compatible = "infineon,cat1-scb"; 300 reg = <0x406c0000 0x10000>; 301 #address-cells = <1>; 302 #size-cells = <0>; 303 interrupts = <50 6>; 304 status = "disabled"; 305 }; 306 adc0: adc@409d0000 { 307 compatible = "infineon,cat1-adc"; 308 reg = <0x409d0000 0x10000>; 309 interrupts = <155 6>; 310 status = "disabled"; 311 #io-channel-cells = <1>; 312 }; 313 314 watchdog0: watchdog@40260180 { 315 compatible = "infineon,cat1-watchdog"; 316 reg = <0x40260180 0xc>; 317 interrupts = <22 6>; 318 status = "disabled"; 319 }; 320 counter0_0: counter@40380100 { 321 compatible = "infineon,cat1-counter"; 322 reg = <0x40380100 0x40>; 323 interrupts = <123 6>; 324 resolution = <32>; 325 status = "disabled"; 326 }; 327 counter0_1: counter@40380140 { 328 compatible = "infineon,cat1-counter"; 329 reg = <0x40380140 0x40>; 330 interrupts = <124 6>; 331 resolution = <32>; 332 status = "disabled"; 333 }; 334 counter0_2: counter@40380180 { 335 compatible = "infineon,cat1-counter"; 336 reg = <0x40380180 0x40>; 337 interrupts = <125 6>; 338 resolution = <32>; 339 status = "disabled"; 340 }; 341 counter0_3: counter@403801c0 { 342 compatible = "infineon,cat1-counter"; 343 reg = <0x403801c0 0x40>; 344 interrupts = <126 6>; 345 resolution = <32>; 346 status = "disabled"; 347 }; 348 counter0_4: counter@40380200 { 349 compatible = "infineon,cat1-counter"; 350 reg = <0x40380200 0x40>; 351 interrupts = <127 6>; 352 resolution = <32>; 353 status = "disabled"; 354 }; 355 counter0_5: counter@40380240 { 356 compatible = "infineon,cat1-counter"; 357 reg = <0x40380240 0x40>; 358 interrupts = <128 6>; 359 resolution = <32>; 360 status = "disabled"; 361 }; 362 counter0_6: counter@40380280 { 363 compatible = "infineon,cat1-counter"; 364 reg = <0x40380280 0x40>; 365 interrupts = <129 6>; 366 resolution = <32>; 367 status = "disabled"; 368 }; 369 counter0_7: counter@403802c0 { 370 compatible = "infineon,cat1-counter"; 371 reg = <0x403802c0 0x40>; 372 interrupts = <130 6>; 373 resolution = <32>; 374 status = "disabled"; 375 }; 376 counter1_0: counter@40390100 { 377 compatible = "infineon,cat1-counter"; 378 reg = <0x40390100 0x40>; 379 interrupts = <131 6>; 380 resolution = <16>; 381 status = "disabled"; 382 }; 383 counter1_1: counter@40390140 { 384 compatible = "infineon,cat1-counter"; 385 reg = <0x40390140 0x40>; 386 interrupts = <132 6>; 387 resolution = <16>; 388 status = "disabled"; 389 }; 390 counter1_2: counter@40390180 { 391 compatible = "infineon,cat1-counter"; 392 reg = <0x40390180 0x40>; 393 interrupts = <133 6>; 394 resolution = <16>; 395 status = "disabled"; 396 }; 397 counter1_3: counter@403901c0 { 398 compatible = "infineon,cat1-counter"; 399 reg = <0x403901c0 0x40>; 400 interrupts = <134 6>; 401 resolution = <16>; 402 status = "disabled"; 403 }; 404 counter1_4: counter@40390200 { 405 compatible = "infineon,cat1-counter"; 406 reg = <0x40390200 0x40>; 407 interrupts = <135 6>; 408 resolution = <16>; 409 status = "disabled"; 410 }; 411 counter1_5: counter@40390240 { 412 compatible = "infineon,cat1-counter"; 413 reg = <0x40390240 0x40>; 414 interrupts = <136 6>; 415 resolution = <16>; 416 status = "disabled"; 417 }; 418 counter1_6: counter@40390280 { 419 compatible = "infineon,cat1-counter"; 420 reg = <0x40390280 0x40>; 421 interrupts = <137 6>; 422 resolution = <16>; 423 status = "disabled"; 424 }; 425 counter1_7: counter@403902c0 { 426 compatible = "infineon,cat1-counter"; 427 reg = <0x403902c0 0x40>; 428 interrupts = <138 6>; 429 resolution = <16>; 430 status = "disabled"; 431 }; 432 counter1_8: counter@40390300 { 433 compatible = "infineon,cat1-counter"; 434 reg = <0x40390300 0x40>; 435 interrupts = <139 6>; 436 resolution = <16>; 437 status = "disabled"; 438 }; 439 counter1_9: counter@40390340 { 440 compatible = "infineon,cat1-counter"; 441 reg = <0x40390340 0x40>; 442 interrupts = <140 6>; 443 resolution = <16>; 444 status = "disabled"; 445 }; 446 counter1_10: counter@40390380 { 447 compatible = "infineon,cat1-counter"; 448 reg = <0x40390380 0x40>; 449 interrupts = <141 6>; 450 resolution = <16>; 451 status = "disabled"; 452 }; 453 counter1_11: counter@403903c0 { 454 compatible = "infineon,cat1-counter"; 455 reg = <0x403903c0 0x40>; 456 interrupts = <142 6>; 457 resolution = <16>; 458 status = "disabled"; 459 }; 460 counter1_12: counter@40390400 { 461 compatible = "infineon,cat1-counter"; 462 reg = <0x40390400 0x40>; 463 interrupts = <143 6>; 464 resolution = <16>; 465 status = "disabled"; 466 }; 467 counter1_13: counter@40390440 { 468 compatible = "infineon,cat1-counter"; 469 reg = <0x40390440 0x40>; 470 interrupts = <144 6>; 471 resolution = <16>; 472 status = "disabled"; 473 }; 474 counter1_14: counter@40390480 { 475 compatible = "infineon,cat1-counter"; 476 reg = <0x40390480 0x40>; 477 interrupts = <145 6>; 478 resolution = <16>; 479 status = "disabled"; 480 }; 481 counter1_15: counter@403904c0 { 482 compatible = "infineon,cat1-counter"; 483 reg = <0x403904c0 0x40>; 484 interrupts = <146 6>; 485 resolution = <16>; 486 status = "disabled"; 487 }; 488 counter1_16: counter@40390500 { 489 compatible = "infineon,cat1-counter"; 490 reg = <0x40390500 0x40>; 491 interrupts = <147 6>; 492 resolution = <16>; 493 status = "disabled"; 494 }; 495 counter1_17: counter@40390540 { 496 compatible = "infineon,cat1-counter"; 497 reg = <0x40390540 0x40>; 498 interrupts = <148 6>; 499 resolution = <16>; 500 status = "disabled"; 501 }; 502 counter1_18: counter@40390580 { 503 compatible = "infineon,cat1-counter"; 504 reg = <0x40390580 0x40>; 505 interrupts = <149 6>; 506 resolution = <16>; 507 status = "disabled"; 508 }; 509 counter1_19: counter@403905c0 { 510 compatible = "infineon,cat1-counter"; 511 reg = <0x403905c0 0x40>; 512 interrupts = <150 6>; 513 resolution = <16>; 514 status = "disabled"; 515 }; 516 counter1_20: counter@40390600 { 517 compatible = "infineon,cat1-counter"; 518 reg = <0x40390600 0x40>; 519 interrupts = <151 6>; 520 resolution = <16>; 521 status = "disabled"; 522 }; 523 counter1_21: counter@40390640 { 524 compatible = "infineon,cat1-counter"; 525 reg = <0x40390640 0x40>; 526 interrupts = <152 6>; 527 resolution = <16>; 528 status = "disabled"; 529 }; 530 counter1_22: counter@40390680 { 531 compatible = "infineon,cat1-counter"; 532 reg = <0x40390680 0x40>; 533 interrupts = <153 6>; 534 resolution = <16>; 535 status = "disabled"; 536 }; 537 counter1_23: counter@403906c0 { 538 compatible = "infineon,cat1-counter"; 539 reg = <0x403906c0 0x40>; 540 interrupts = <154 6>; 541 resolution = <16>; 542 status = "disabled"; 543 }; 544 }; 545}; 546
