1/*
2 * Copyright (c) 2020 Hans Unzner
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <zephyr/dt-bindings/clock/stm32f410_clock.h>
8#include <st/f4/stm32f4.dtsi>
9
10/ {
11	chosen {
12		zephyr,entropy = &rng;
13	};
14
15	soc {
16		compatible = "st,stm32f410", "st,stm32f4", "simple-bus";
17
18		spi2: spi@40003800 {
19			compatible = "st,stm32-spi";
20			#address-cells = <1>;
21			#size-cells = <0>;
22			reg = <0x40003800 0x400>;
23			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
24			interrupts = <36 5>;
25			status = "disabled";
26		};
27
28		spi5: spi@40015000 {
29			compatible = "st,stm32-spi";
30			#address-cells = <1>;
31			#size-cells = <0>;
32			reg = <0x40015000 0x400>;
33			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>;
34			interrupts = <85 5>;
35			status = "disabled";
36		};
37
38		i2s1: i2s@40013000 {
39			compatible = "st,stm32-i2s";
40			#address-cells = <1>;
41			#size-cells = <0>;
42			reg = <0x40013000 0x400>;
43			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
44			interrupts = <35 5>;
45			dmas = <&dma2 3 3 0x400 0x3
46				&dma2 2 3 0x400 0x3>;
47			dma-names = "tx", "rx";
48			status = "disabled";
49		};
50
51		i2s2: i2s@40003800 {
52			compatible = "st,stm32-i2s";
53			#address-cells = <1>;
54			#size-cells = <0>;
55			reg = <0x40003800 0x400>;
56			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
57			interrupts = <36 5>;
58			dmas = <&dma1 4 0 0x400 0x3
59				&dma1 3 0 0x400 0x3>;
60			dma-names = "tx", "rx";
61			status = "disabled";
62		};
63
64		i2s5: i2s@40015000 {
65			compatible = "st,stm32-i2s";
66			#address-cells = <1>;
67			#size-cells = <0>;
68			reg = <0x40015000 0x400>;
69			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>;
70			interrupts = <85 5>;
71			dmas = <&dma2 6 7 0x400 0x3
72				&dma2 5 7 0x400 0x3>;
73			dma-names = "tx", "rx";
74			status = "disabled";
75		};
76
77		timers6: timers@40001000 {
78			compatible = "st,stm32-timers";
79			reg = <0x40001000 0x400>;
80			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
81			resets = <&rctl STM32_RESET(APB1, 4U)>;
82			interrupts = <54 0>;
83			interrupt-names = "global";
84			st,prescaler = <0>;
85			status = "disabled";
86
87			counter {
88				compatible = "st,stm32-counter";
89				status = "disabled";
90			};
91		};
92
93		dac1: dac@40007400 {
94			compatible = "st,stm32-dac";
95			reg = <0x40007400 0x400>;
96			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
97			status = "disabled";
98			#io-channel-cells = <1>;
99		};
100
101		rng: rng@40080000 {
102			compatible = "st,stm32-rng";
103			reg = <0x40080000 0x400>;
104			interrupts = <80 0>;
105			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x80000000>;
106			status = "disabled";
107		};
108	};
109
110	die_temp: dietemp {
111		io-channels = <&adc1 18>;
112	};
113};
114