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/Zephyr-latest/dts/bindings/ipc/
Dzephyr,ipc-openamp-static-vrings.yaml35 WQ priority for the instance. This property is an array composed by the
/Zephyr-latest/dts/bindings/test/
Dvnd,pinctrl-test.yaml13 Test pin controller pin configuration nodes. Each node is composed by one or
/Zephyr-latest/samples/subsys/llext/edk/
DREADME.rst12 Kit). It is composed of one Zephyr application, which provides APIs for the
16 The application is composed of a subscriber thread, which listens for events
/Zephyr-latest/samples/tfm_integration/psa_crypto/src/
Dpsa_attestation.h32 * The initial attestation token (IAT) is composed of a series of 'claims' or
/Zephyr-latest/doc/hardware/peripherals/sensor/
Dindex.rst25 to understand. Sensors in Zephyr are composed of :ref:`sensor-channel`,
/Zephyr-latest/dts/bindings/pinctrl/
Despressif,esp32-pinctrl.yaml7 states are composed by groups of pre-defined pin muxing definitions and user
/Zephyr-latest/boards/phytec/phyboard_lyra/doc/
Dphyboard_lyra_am62xx_a53.rst10 processor, composed of a quad Cortex®-A53 cluster and a single Cortex®-M4 core.
Dphyboard_lyra_am62xx_m4.rst28 The phyBOARD-Lyra AM62x kit features the AM62x SoC, which is composed of a
/Zephyr-latest/dts/bindings/memory-controllers/
Datmel,sam-smc.yaml38 7 pulses (56ns). The atmel,smc-cycle-timing is composed of three parts:
/Zephyr-latest/include/zephyr/crypto/
Dcipher.h93 /* CTR mode counter is a split counter composed of iv and counter
/Zephyr-latest/include/zephyr/arch/arm64/
Darm_mmu.h199 * is an uint32_t composed by permission and attribute flags
/Zephyr-latest/dts/bindings/qspi/
Dnxp,s32-qspi.yaml88 In case of Octal DDR mode, specifies whether a word unit composed of two
/Zephyr-latest/boards/ti/sk_am62/doc/
Dindex.rst19 The SK-AM62 EVM features the AM62x SoC, which is composed of a quad Cortex-A53
/Zephyr-latest/boards/phytec/phyboard_electra/doc/
Dindex.rst28 The AM64x phyBOARD-Electra kit features the AM64x SoC, which is composed of a
/Zephyr-latest/boards/nxp/imx8mn_evk/doc/
Dindex.rst7 processor, composed of a quad Cortex®-A53 cluster and a single Cortex®-M7 core.
/Zephyr-latest/subsys/usb/usb_c/
Dusbc_stack.h21 * @brief Each layer of the stack is composed of state machines that can be
/Zephyr-latest/boards/technexion/pico_pi/doc/
Dindex.rst6 The i.MX7D SoC is a Hybrid multi-core processor composed of Single Cortex A7
14 The Pico-Pi Platform is composed of a CPU and IO board.
/Zephyr-latest/boards/element14/warp7/doc/
Dindex.rst6 The i.MX7S SoC is a Hybrid multi-core processor composed of Single Cortex A7
14 The WaRP7 Platform is composed of a CPU and IO board.
/Zephyr-latest/include/zephyr/arch/riscv/
Darch.h195 * is an uint8_t composed by configuration register flags
/Zephyr-latest/boards/phytec/phyboard_nash/doc/
Dindex.rst15 i.MX93 MPU is composed of one cluster of 2x Cortex-A55 cores and a single
/Zephyr-latest/boards/96boards/avenger96/doc/
Dindex.rst10 multi-core processor, composed of a dual Cortex®-A7 and a single Cortex®-M4
/Zephyr-latest/boards/nxp/imx8mq_evk/doc/
Dindex.rst7 processor, composed of a quad Cortex®-A53 cluster and a single Cortex®-M4 core.
/Zephyr-latest/scripts/ci/
Dupload_test_results_es.py333 … "This name value will be composed instead of the container's name 'children' and\n"
/Zephyr-latest/doc/services/logging/
Dcs_stm.rst94 of data is composed by STM and send over TPIU.
/Zephyr-latest/boards/st/stm32mp157c_dk2/doc/
Dstm32mp157_dk2.rst7 multi-core processor,composed of a dual Cortex®-A7 and a single Cortex®-M4 core.

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