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/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h5_core/boards/
Dcsi4.overlay13 &clk_csi {
18 clocks = <&clk_csi>;
Dpll_csi_ahb_2_100.overlay13 &clk_csi {
23 clocks = <&clk_csi>;
Dpll_csi_100.overlay13 &clk_csi {
24 clocks = <&clk_csi>;
Dpll_csi_240.overlay13 &clk_csi {
24 clocks = <&clk_csi>;
Dclear_clocks.overlay14 &clk_csi {
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_core/boards/
Dcsi_4.overlay12 &clk_csi {
17 clocks = <&clk_csi>;
Dpll_csi_96.overlay12 &clk_csi {
22 clocks = <&clk_csi>;
Dclear_clocks.overlay23 &clk_csi {
/Zephyr-latest/dts/bindings/clock/
Dst,stm32h7rs-pll-clock.yaml9 These PLLs could take one of clk_hse, clk_hsi or clk_csi as input clock, with
Dst,stm32h7-pll-clock.yaml10 These PLLs could take one of clk_hse, clk_hsi or clk_csi as input clock, with
Dst,stm32h7-rcc.yaml12 node (typically 'clk_hse, clk_csi', 'pll', ...).
Dst,stm32h7rs-rcc.yaml12 node (typically 'clk_hse, clk_csi', 'pll', ...).
/Zephyr-latest/boards/st/nucleo_h503rb/
Dnucleo_h503rb.dts53 &clk_csi {
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/boards/
Dcore_init.overlay28 &clk_csi {
/Zephyr-latest/boards/st/nucleo_h533re/
Dnucleo_h533re.dts62 &clk_csi {
/Zephyr-latest/include/zephyr/drivers/clock_control/
Dstm32_clock_control.h141 #if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_csi))
268 #if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_csi))
363 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_csi), fixed_clock, okay)
365 #define STM32_CSI_FREQ DT_PROP(DT_NODELABEL(clk_csi), clock_frequency)
/Zephyr-latest/dts/arm/st/h5/
Dstm32h5.dtsi66 clk_csi: clk-csi { label
/Zephyr-latest/dts/arm/st/h7rs/
Dstm32h7rs.dtsi112 clk_csi: clk-csi { label
/Zephyr-latest/dts/arm/st/h7/
Dstm32h7.dtsi81 clk_csi: clk-csi { label