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/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32wba_core/src/
Dtest_stm32_clock_configuration.c31 "Expected sysclk src: PLL1. Actual sysclk src: %d", in ZTEST()
35 "Expected sysclk src: HSE. Actual sysclk src: %d", in ZTEST()
39 "Expected sysclk src: HSI. Actual sysclk src: %d", in ZTEST()
/Zephyr-latest/dts/bindings/clock/
Dadi,max32-gcr.yaml17 sysclk-prescaler:
30 SYSCLK prescaler. Defines actual core clock frequency SYSCLK
Dst,stm32h7-rcc.yaml6 This node is in charge of system clock ('SYSCLK') source selection and
13 As part of this node configuration, SYSCLK frequency should also be defined, using
19 clocks = <&pll>; /* Set pll as SYSCLK source */
20 clock-frequency = <DT_FREQ_M(480)>; /* SYSCLK runs at 480MHz */
55 lower than SYSCLK frequency (actual core frequency).
Dst,stm32h7rs-rcc.yaml6 This node is in charge of system clock ('SYSCLK') source selection and
13 As part of this node configuration, SYSCLK frequency should also be defined, using
19 clocks = <&pll>; /* Set pll as SYSCLK source */
20 clock-frequency = <DT_FREQ_M(280)>; /* SYSCLK runs at 280MHz */
63 lower than SYSCLK frequency (actual core frequency).
Dst,stm32wb0-rcc.yaml6 This node is in charge of the system clock ('SYSCLK') source
48 on system frequency input (SYSCLK).
51 NOTE: if the 32MHz HSE is used as SYSCLK source, the prescaler cannot
Dst,stm32wba-rcc.yaml6 This node is in charge of system clock ('SYSCLK') source selection and controlling
15 Core clock frequency = SYSCLK / AHB prescaler
20 clocks = <&pll>; /* Select pll as SYSCLK source */
22 clock-frequency = <DT_FREQ_M(40)>; /* = SYSCLK / AHB prescaler */
Dst,stm32-rcc.yaml6 This node is in charge of system clock ('SYSCLK') source selection and controlling
15 Core clock frequency = SYSCLK / AHB prescaler
20 clocks = <&pll>; /* Select 80MHz pll as SYSCLK source */
22 clock-frequency = <DT_FREQ_M(40)>; /* = SYSCLK / AHB prescaler */
/Zephyr-latest/drivers/audio/
Dwm8904.h126 /*! @brief The SYSCLK / fs ratio. */
128 kWM8904_FsRatio64X = 0x0, /*!< SYSCLK is 64 * sample rate * frame width */
129 kWM8904_FsRatio128X = 0x1, /*!< SYSCLK is 128 * sample rate * frame width */
130 kWM8904_FsRatio192X = 0x2, /*!< SYSCLK is 192 * sample rate * frame width */
131 kWM8904_FsRatio256X = 0x3, /*!< SYSCLK is 256 * sample rate * frame width */
132 kWM8904_FsRatio384X = 0x4, /*!< SYSCLK is 384 * sample rate * frame width */
133 kWM8904_FsRatio512X = 0x5, /*!< SYSCLK is 512 * sample rate * frame width */
134 kWM8904_FsRatio768X = 0x6, /*!< SYSCLK is 768 * sample rate * frame width */
135 kWM8904_FsRatio1024X = 0x7, /*!< SYSCLK is 1024 * sample rate * frame width */
136 kWM8904_FsRatio1408X = 0x8, /*!< SYSCLK is 1408 * sample rate * frame width */
[all …]
/Zephyr-latest/boards/arm/mps3/
Dmps3_common_soc_peripheral.dtsi8 sysclk: system-clock { label
75 clocks = <&sysclk>;
85 clocks = <&sysclk>;
95 clocks = <&sysclk>;
156 clocks = <&sysclk>;
165 clocks = <&sysclk>;
174 clocks = <&sysclk>;
183 clocks = <&sysclk>;
192 clocks = <&sysclk>;
202 clocks = <&sysclk>;
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h5_core/src/
Dtest_stm32_clock_configuration.c31 "Expected sysclk src: PLL1 (0x%x). Actual: 0x%x", in ZTEST()
35 "Expected sysclk src: HSE (0x%x). Actual: 0x%x", in ZTEST()
39 "Expected sysclk src: HSI (0x%x). Actual: 0x%x", in ZTEST()
43 "Expected sysclk src: MSI (0x%x). Actual: 0x%x", in ZTEST()
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/src/
Dtest_stm32_clock_configuration.c31 "Expected sysclk src: PLL1 (0x%x). Actual: 0x%x", in ZTEST()
35 "Expected sysclk src: HSE (0x%x). Actual: 0x%x", in ZTEST()
39 "Expected sysclk src: HSI (0x%x). Actual: 0x%x", in ZTEST()
43 "Expected sysclk src: MSI (0x%x). Actual: 0x%x", in ZTEST()
/Zephyr-latest/dts/arm/aspeed/
Dast10x0.dtsi31 sysclk: sysclk { label
46 clocks = <&sysclk ASPEED_CLK_UART5>;
/Zephyr-latest/tests/cmake/hwm/board_extend/oot_root/boards/arm/mps2/
Dmps2_an521-common.dtsi7 sysclk: system-clock { label
78 clocks = <&sysclk>;
86 clocks = <&sysclk>;
95 clocks = <&sysclk>;
104 clocks = <&sysclk>;
113 clocks = <&sysclk>;
122 clocks = <&sysclk>;
/Zephyr-latest/boards/arm/mps2/
Dmps2_an521-common.dtsi7 sysclk: system-clock { label
78 clocks = <&sysclk>;
86 clocks = <&sysclk>;
95 clocks = <&sysclk>;
104 clocks = <&sysclk>;
113 clocks = <&sysclk>;
122 clocks = <&sysclk>;
Dmps2_an385.dts103 sysclk: system-clock { label
133 clocks = <&sysclk>;
142 clocks = <&sysclk>;
151 clocks = <&sysclk>;
160 clocks = <&sysclk>;
166 clocks = <&sysclk>;
175 clocks = <&sysclk>;
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_core/src/
Dtest_stm32_clock_configuration.c31 "Expected sysclk src: PLL (0x%x). Actual: 0x%x", in ZTEST()
35 "Expected sysclk src: HSE (0x%x). Actual: 0x%x", in ZTEST()
39 "Expected sysclk src: HSI (0x%x). Actual: 0x%x", in ZTEST()
43 "Expected sysclk src: CSI (0x%x). Actual: 0x%x", in ZTEST()
/Zephyr-latest/drivers/clock_control/
Dclock_stm32_ll_h7.c113 /* All h7 SoC with maximum 480MHz SYSCLK */
121 /* All h7 SoC with maximum 550MHz SYSCLK */
132 /* All h7RS SoC with maximum 500MHz SYSCLK (refer to Datasheet DS14359 rev 1) */
137 /* Default: All h7 SoC with maximum 280MHz SYSCLK */
144 #error "SYSCLK frequency is too high!"
169 * D1CPRE prescaler allows to set a HCLK frequency lower than SYSCLK frequency.
221 uint32_t sysclk = 0; in get_hclk_frequency() local
226 sysclk = STM32_HSI_FREQ/STM32_HSI_DIVISOR; in get_hclk_frequency()
229 sysclk = STM32_CSI_FREQ; in get_hclk_frequency()
232 sysclk = STM32_HSE_FREQ; in get_hclk_frequency()
[all …]
/Zephyr-latest/dts/arm/ti/
Dmsp432p4xx.dtsi24 sysclk: system-clock { label
35 clocks = <&sysclk>;
Dlm3s6965.dtsi22 sysclk: system-clock { label
45 clocks = <&sysclk>;
53 clocks = <&sysclk>;
61 clocks = <&sysclk>;
Dcc32xx.dtsi53 sysclk: system-clock { label
64 clocks = <&sysclk>;
72 clocks = <&sysclk>;
78 clocks = <&sysclk>;
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_core/src/
Dtest_stm32_clock_configuration.c40 "Expected sysclk src: PLL (0x%x). Actual: 0x%x", in ZTEST()
44 "Expected sysclk src: HSE (0x%x). Actual: 0x%x", in ZTEST()
48 "Expected sysclk src: HSI (0x%x). Actual: 0x%x", in ZTEST()
52 "Expected sysclk src: MSI (0x%x). Actual: 0x%x", in ZTEST()
/Zephyr-latest/boards/arm/v2m_beetle/
Dv2m_beetle.dts43 sysclk: system-clock { label
75 clocks = <&sysclk &syscon>;
83 clocks = <&sysclk &syscon>;
89 clocks = <&sysclk>;
/Zephyr-latest/dts/arm/infineon/cat3/xmc/
Dxmc4xxx.dtsi35 sysclk: system-clock { label
119 clocks = <&sysclk>;
125 clocks = <&sysclk>;
131 clocks = <&sysclk>;
137 clocks = <&sysclk>;
143 clocks = <&sysclk>;
149 clocks = <&sysclk>;
/Zephyr-latest/boards/arm/v2m_musca_b1/
Dv2m_musca_b1-common.dtsi30 clocks = <&sysclk>;
39 clocks = <&sysclk>;
/Zephyr-latest/boards/arm/v2m_musca_s1/
Dv2m_musca_s1-common.dtsi30 clocks = <&sysclk>;
39 clocks = <&sysclk>;

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