Lines Matching full:sysclk
114 /* All h7 SoC with maximum 480MHz SYSCLK */
122 /* All h7 SoC with maximum 550MHz SYSCLK */
133 /* All h7RS SoC with maximum 500MHz SYSCLK (refer to Datasheet DS14359 rev 1) */
138 /* Default: All h7 SoC with maximum 280MHz SYSCLK */
145 #error "SYSCLK frequency is too high!"
170 * D1CPRE prescaler allows to set a HCLK frequency lower than SYSCLK frequency.
222 uint32_t sysclk = 0; in get_hclk_frequency() local
227 sysclk = STM32_HSI_FREQ/STM32_HSI_DIVISOR; in get_hclk_frequency()
230 sysclk = STM32_CSI_FREQ; in get_hclk_frequency()
233 sysclk = STM32_HSE_FREQ; in get_hclk_frequency()
237 sysclk = get_pllout_frequency(get_pllsrc_frequency(), in get_hclk_frequency()
245 return get_bus_clock(sysclk, STM32_HPRE); in get_hclk_frequency()
469 * Get AHB Clock (= SystemCoreClock = SYSCLK/prescaler)
777 * (Switching to HSI makes sure we have a SYSCLK source in
997 uint32_t sysclk, hsivalue, pllsource, pllm, pllp, core_presc; local
1000 /* Get SYSCLK source */
1003 sysclk = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)
1008 sysclk = CSI_VALUE;
1012 sysclk = HSE_VALUE;
1018 * SYSCLK = PLL1_VCO / PLL1R
1056 sysclk = (uint32_t)(float_t)(pllvco/(float_t)pllp);
1058 sysclk = 0U;
1063 sysclk = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >> RCC_CR_HSIDIV_Pos));
1071 SystemCoreClock = (sysclk >> (core_presc - RCC_CDCFGR_CPRE_3 + 1U));
1073 SystemCoreClock = sysclk;
1117 /* AHB/AXI/HCLK clock is SYSCLK / HPRE */
1130 /* Preset the prescalers prior to choosing SYSCLK */
1155 /* Set sysclk source to HSE */
1161 /* Set sysclk source to HSI */
1164 /* Set sysclk source to CSI */
1174 /* AHB/AXI/HCLK clock is SYSCLK / HPRE */