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/Zephyr-latest/soc/silabs/silabs_sim3/sim3u/
Dgen_crossbar_config.py5 # SPDX-License-Identifier: Apache-2.0
9 The SiM3U1xx SoCs do support pinmuxing, but with many limimitations. It's also non-optional, so we
18 - crossbar 0: Controls portbanks 0 and 1
19 - crossbar 1: Controls portbanks 2 and 3
21 Each crossbar has two configuration-values which reside in different registers:
22 - config: A bitmask which tells the crossbar which peripherals should be muxed. Some peripherals
23 have multiple bits to prevent having to mux unused pins (like UART flow control).
24 - enable: A bit which enables or disables the whole crossbar. When disabled, all pins of the
28 - pbskipen: A bitmask where value `1` means, that the pin will not be muxed.
29 The index of the bit refers to the pin number.
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/Zephyr-latest/drivers/pinctrl/
Dpinctrl_rv32m1.c5 * SPDX-License-Identifier: Apache-2.0
24 #define PIN(mux) (((mux) & 0xFC00000) >> 22) argument
25 #define PORT(mux) (((mux) & 0xF0000000) >> 28) argument
26 #define PINCFG(mux) ((mux) & Z_PINCTRL_RV32M1_PCR_MASK) argument
37 uint8_t pin = PIN(pins[i]); in pinctrl_configure_pins() local
38 uint16_t mux = PINCFG(pins[i]); in pinctrl_configure_pins() local
40 base->PCR[pin] = (base->PCR[pin] & (~Z_PINCTRL_RV32M1_PCR_MASK)) | mux; in pinctrl_configure_pins()
47 const struct pinctrl_rv32m1_config *config = dev->config; in pinctrl_rv32m1_init()
49 CLOCK_EnableClock(config->clock_ip_name); in pinctrl_rv32m1_init()
Dpinctrl_nxp_port.c2 * Copyright 2022-2024 NXP
4 * SPDX-License-Identifier: Apache-2.0
33 #define PIN(mux) (((mux) & 0xFC00000) >> 22) argument
34 #define PORT(mux) (((mux) & 0xF0000000) >> 28) argument
35 #define PINCFG(mux) ((mux) & Z_PINCTRL_NXP_PORT_PCR_MASK) argument
47 uint8_t pin = PIN(pins[i]); in pinctrl_configure_pins() local
48 uint16_t mux = PINCFG(pins[i]); in pinctrl_configure_pins() local
50 base->PCR[pin] = (base->PCR[pin] & (~Z_PINCTRL_NXP_PORT_PCR_MASK)) | mux; in pinctrl_configure_pins()
57 const struct pinctrl_mcux_config *config = dev->config; in pinctrl_mcux_init()
60 if (!device_is_ready(config->clock_dev)) { in pinctrl_mcux_init()
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Dpinctrl_stm32.c2 * Copyright (c) 2016 Open-RnD Sp. z o.o.
6 * SPDX-License-Identifier: Apache-2.0
22 /** Helper to extract IO pin number from STM32PIN() encoded value */
30 /** Helper to extract IO pin number from STM32_PINMUX() encoded value */
34 /** Helper to extract IO pin func from STM32_PINMUX() encoded value */
39 /** Helper to extract IO pin remap from STM32_PINMUX() encoded value */
89 #error "Pin remap property available only on STM32G0 and STM32C0 SoC series" in stm32_pinmux_init_remap()
103 #error "Pin remap property available only on STM32F070x SoC series" in stm32_pinmux_init_remap()
121 /* ignore swj-cfg reset state (default value) */
130 /* reset state is '000' (Full SWJ, (JTAG-DP + SW-DP)) */ in stm32f1_swj_cfg_init()
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Dpinctrl_lpc_iocon.c4 * SPDX-License-Identifier: Apache-2.0
14 #define OFFSET(mux) (((mux) & 0xFFF00000) >> 20) argument
15 #define TYPE(mux) (((mux) & 0xC0000) >> 18) argument
31 /* Check if this is an analog or i2c type pin */ in pinctrl_configure_pins()
DKconfig.mci_io_mux2 # SPDX-License-Identifier: Apache-2.0
5 bool "NXP MCI IO MUX Pinctrl Driver"
9 Enable pin controller driver for NXP MCI_IO_MUX
/Zephyr-latest/dts/bindings/pinctrl/
Dnxp,mci-io-mux.yaml2 # SPDX-License-Identifier: Apache-2.0
5 MCI IO MUX pin control node. This node defines pin configurations in pin
7 group within the pin configuration defines a peripheral's pin configuration.
17 slew-rate = "normal";
21 If only the required properties are supplied, the pin will be configured
23 pin settings:
30 bias-pull-up: PAD_PU_PD_ENx= (0x1 << pin_index)
31 bias-pull-down: PAD_PU_PD_ENx= (0x10 << pin_index)
33 compatible: "nxp,mci-io-mux"
36 - name: base.yaml
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Dnxp,imx-iomuxc-scu.yaml2 # SPDX-License-Identifier: Apache-2.0
8 compatible: "nxp,imx-iomuxc-scu"
12 child-binding:
13 description: SCFW-based IOMUXC pin mux.
19 This is an array of values defining the pin mux selection
22 <pad, mux>
25 mux: Select which signal to route.
Dti,k3-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
8 offset - the pin attribute register offset from the base address.
9 value - one of the following:
16 mux_mode - The mux mode for the pin, MUX_MODE_0 -> MUX_MODE_9.
18 The default UART0_RX pin is located at 0x000f41c8 (mux mode 0).
21 compatible: "ti,k3-pinctrl"
29 child-binding:
32 pin configuration.
39 TI K3 pin configuration.
Dnxp,imx-iomuxc.yaml2 # SPDX-License-Identifier: Apache-2.0
7 These options can then be used in a pinctrl node with the "nxp,mcux-rt-pinctrl"
8 compatible string to define pin groups.
13 compatible: "nxp,imx-iomuxc"
16 - name: base.yaml
22 child-binding:
23 description: MCUX RT pin mux option
29 An array of values defining the pin mux selection, in the following format:
31 mux_register: register that will be written to make mux selection
33 input_reg: peripheral register that will direct peripheral signal to pin
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Dnxp,rt-iocon-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
5 RT600/RT500 pin control node. This node defines pin configurations in pin
7 group within the pin configuration defines a peripheral's pin configuration.
17 slew-rate = "normal";
18 drive-strength = "normal";
24 IOCON_FUNC=<pin mux selection>,
28 IOCON_SLEWRATE = <slew-rate selection>,
29 IOCON_FULLDRIVE = <drive-strength selection>,
35 drive-open-drain: IOCON_ODENA=1
36 bias-pull-up: IOCON_PUPDENA=1, IOCON_PUPSEL=1
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Dsilabs,si32-pinctrl.yaml3 # SPDX-License-Identifier: Apache-2.0
8 compatible: "silabs,si32-pinctrl"
11 - name: base.yaml
13 child-binding:
14 description: Si32 pin controller pin group
15 child-binding:
17 Si32 pin controller pin configuration node
20 - name: pincfg-node.yaml
21 property-allowlist:
22 - input-enable
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Dnxp,mcux-rt11xx-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
7 the rt_dts_gen.py script in NXP's HAL. The mux, mode, input, daisy, and cfg
15 drive-strength = "high";
16 slew-rate = "slow";
25 drive-open-drain: ODE/ODE_LPSR=1
26 input-enable: SION=1 (in SW_MUX_CTL_PAD register)
27 bias-pull-down: PUE=1, PUS=0
28 bias-pull-up: PUE=1, PUS=1
29 bias-disable: PULL=11 (in supported registers)
30 slew-rate: SRE=<enum_idx>
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Dnxp,imx93-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
7 the imx_dts_gen.py script in NXP's HAL. The mux, mode, input, daisy, and cfg
15 bias-pull-up;
16 slew-rate = "slow";
17 drive-strength = "x1";
26 input-schmitt-enable: HYS=1
27 drive-open-drain: OD=1
28 bias-pull-down: PD=0
29 bias-pull-up: PU
30 slew-rate: FSEL1=<enum_idx>
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Dnxp,imx8mp-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
7 the imx_dts_gen.py script in NXP's HAL. The mux, mode, input, daisy, and cfg
15 bias-pull-up;
16 slew-rate = "slow";
17 drive-strength = "x1";
26 input-schmitt-enable: HYS=1
27 bias-pull-up: PUE=1, PE=1
28 bias-pull-down: PUE=0, PE=1
29 drive-open-drain: ODE=1
30 slew-rate: FSEL=<enum_idx>
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Dnxp,imx7d-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
7 the imx_dts_gen.py script in NXP's HAL. The mux, mode, input, daisy, and cfg
14 bias-pull-up: PE=1, PS=<bias-pull-up-value index>
15 bias-pull-down: PE=1, PS=0
16 input-schmitt-enable: HYS=1
17 slew-rate: SRE=<enum idx>
18 drive-strength: DSE=<enum idx>
19 input-enable: SION=1 (in SW_PAD_CTL_MUX register)
21 If only required properties are supplied, the pin will have the following
26 SRE=<slew-rate>,
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Dinfineon,xmc4xxx-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
5 The Infineon XMC4XXX pin controller is responsible for connecting peripheral outputs
6 to specific port/pins (also known as alternate functions) and configures pin properties.
12 compatible = "infineon,xmc4xxx-uart";
13 pinctrl-0 = <&uart_tx_p0_1_u1c1 &uart_rx_p0_0_u1c1>;
14 pinctrl-names = "default";
15 input-src = "DX0D";
19 pinctrl-0 is the phandle that stores the pin settings for two pins: &uart_tx_p0_1_u1c1
20 and &uart_rx_p0_0_u1c1. These nodes are pre-defined and their naming convention is designed
21 to help the user select the correct pin settings. Note the use of peripheral type,
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/Zephyr-latest/include/zephyr/dt-bindings/pinctrl/
Drv32m1-pinctrl.h4 * SPDX-License-Identifier: Apache-2.0
11 * @brief Specify PORTx->PCR register MUX field
14 * @param pin Port pin number (0 to 31)
15 * @param mux Alternate function number (0 to 7)
17 #define RV32M1_MUX(port, pin, mux) \ argument
18 (((((port) - 'A') & 0xF) << 28) | \
19 (((pin) & 0x3F) << 22) | \
20 (((mux) & 0x7) << 8))
/Zephyr-latest/boards/nxp/imx93_evk/dts/bindings/
Dimx93evk-exp-sel.yaml2 # SPDX-License-Identifier: Apache-2.0
5 The i.MX 93 EVK boards has a series of MUXes that selects between 2 pin
9 compatible: "imx93evk-exp-sel"
14 mux-gpios:
15 type: phandle-array
17 description: Pin used to select the MUX
19 mux:
23 - "A"
24 - "B"
25 description: MUX choice
/Zephyr-latest/boards/nxp/imx93_evk/
Dboard.c3 * SPDX-License-Identifier: Apache-2.0
24 const struct gpio_dt_spec mux = GPIO_DT_SPEC_GET(BOARD_EXP_SEL_NODE, mux_gpios); in board_init_exp_sel() local
25 uint32_t pin_state = DT_ENUM_IDX(BOARD_EXP_SEL_NODE, mux); in board_init_exp_sel()
27 if (!gpio_is_ready_dt(&mux)) { in board_init_exp_sel()
28 LOG_ERR("EXP_SEL Pin port is not ready"); in board_init_exp_sel()
29 return -ENODEV; in board_init_exp_sel()
39 rc = gpio_pin_configure_dt(&mux, pin_state); in board_init_exp_sel()
41 LOG_ERR("Write EXP_SEL Pin error %d", rc); in board_init_exp_sel()
44 LOG_INF("EXP_SEL mux %c with priority %d", pin_state ? 'B' : 'A', in board_init_exp_sel()
/Zephyr-latest/dts/bindings/comparator/
Dnxp,kinetis-acmp.yaml3 # SPDX-License-Identifier: Apache-2.0
11 compatible = "nxp,kinetis-acmp";
32 pinctrl-0 = <&acmp0_default>;
33 pinctrl-names = "default";
35 positive-mux-input = "IN0";
36 negative-mux-input = "IN1";
39 compatible: "nxp,kinetis-acmp"
42 - base.yaml
43 - pinctrl-device.yaml
52 nxp,enable-output-pin:
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/Zephyr-latest/soc/nxp/imxrt/imxrt5xx/cm33/
Dsoc.h2 * Copyright 2022-2023, NXP
4 * SPDX-License-Identifier: Apache-2.0
11 * This header file is used to specify and describe board-level aspects for the
24 /*!<@brief Analog mux is disabled */
26 /*!<@brief Analog mux is enabled */
32 /*!<@brief Selects pin function 0 */
34 /*!<@brief Selects pin function 1 */
36 /*!<@brief Selects pin function 2 */
38 /*!<@brief Selects pin function 3 */
40 /*!<@brief Selects pin function 4 */
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/Zephyr-latest/dts/arm/nuvoton/npcx/npcx7/
Dnpcx7-alts-map.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 /* Common pin-mux configurations in npcx family */
8 #include <nuvoton/npcx/npcx-alts-map.dtsi>
10 /* Specific pin-mux configurations in npcx7 series */
12 npcx-alts-map {
13 compatible = "nuvoton,npcx-pinctrl-conf";
16 alt5_njen1_en: alt51-inv {
19 alt5_njen0_en: alt52-inv {
/Zephyr-latest/soc/nxp/imxrt/imxrt6xx/cm33/
Dsoc.h4 * SPDX-License-Identifier: Apache-2.0
11 * This header file is used to specify and describe board-level aspects for the
27 /*!<@brief Analog mux is disabled */
29 /*!<@brief Analog mux is enabled */
35 /*!<@brief Selects pin function 0 */
37 /*!<@brief Selects pin function 1 */
39 /*!<@brief Selects pin function 2 */
41 /*!<@brief Selects pin function 3 */
43 /*!<@brief Selects pin function 4 */
45 /*!<@brief Selects pin function 5 */
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/Zephyr-latest/dts/bindings/i2c/
Dti,tca954x-base.yaml2 # SPDX-License-Identifier: Apache-2.0
4 # Common fields for TI TCA954X I2C mux family
14 mux: tca9546a@77 {
18 #address-cells = <1>;
19 #size-cells = <0>;
20 reset-gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
23 compatible: "ti,tca9546a-channel"
25 #address-cells = <1>;
26 #size-cells = <0>;
35 compatible: "ti,tca9546a-channel"
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