Searched full:pll_r (Results 1 – 15 of 15) sorted by relevance
| /Zephyr-latest/soc/sifive/sifive_freedom/fe300/ |
| D | clock.c | 37 const int pll_r = 0x1; in soc_early_init_hook() local
51 prci = PLL_REFSEL(1) | PLL_R(pll_r) | PLL_F(pll_f) | PLL_Q(pll_q); in soc_early_init_hook()
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| D | prci.h | 33 #define PLL_R(x) (((x) & 0x7) << 0) macro
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| /Zephyr-latest/soc/sifive/sifive_freedom/fu700/ |
| D | clock.c | 37 PLL_R(0) | /* input divider: Fin / (0 + 1) = 26MHz */ in soc_early_init_hook()
52 PLL_R(0) | /* input divider: Fin / (0 + 1) = 26MHz */ in soc_early_init_hook()
67 PLL_R(0) | /* input divider: Fin / (0 + 1) = 26MHz */ in soc_early_init_hook()
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| D | prci.h | 33 #define PLL_R(x) (((x) & 0x3f) << 0) macro
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| /Zephyr-latest/dts/bindings/clock/ |
| D | st,stm32f4-plli2s-clock.yaml | 11 f(PLL_R) = f(VCO clock) / PLLR --> PLLI2S
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| D | st,stm32g4-pll-clock.yaml | 16 f(PLL_R) = f(VCO clock) / PLLR --> PLLCLK (System Clock)
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| D | st,stm32g0-pll-clock.yaml | 16 f(PLL_R) = f(VCO clock) / PLLR --> PLLCLK (System Clock)
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| D | st,stm32u0-pll-clock.yaml | 16 f(PLL_R) = f(VCO clock) / PLLR --> PLLCLK (System Clock)
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| D | st,stm32wba-pll-clock.yaml | 18 f(PLL_R) = f(VCO clock) / PLLR
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| D | st,stm32wb-pll-clock.yaml | 19 f(PLL_R) = f(VCO clock) / PLLR --> PLLRCLK (System Clock)
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| D | st,stm32l4-pll-clock.yaml | 19 f(PLL_R) = f(VCO clock) / PLLR --> PLLCLK (System Clock)
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| D | st,stm32u5-pll-clock.yaml | 18 f(PLL_R) = f(VCO clock) / PLLR
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| /Zephyr-latest/soc/sifive/sifive_freedom/fu500/ |
| D | clock.c | 25 PLL_R(0) | /* input divider: Fin / (0 + 1) = 33.33MHz */ in soc_early_init_hook()
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| D | prci.h | 27 #define PLL_R(x) (((x) & 0x3f) << 0) macro
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| /Zephyr-latest/doc/releases/ |
| D | release-notes-3.2.rst | 525 * STM32: PLL_P, PLL_Q, PLL_R outputs can now be used as domain clock.
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