| /Zephyr-latest/include/zephyr/drivers/clock_control/ |
| D | stm32_clock_control.h | 213 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll3), st_stm32h7_pll_clock, okay) || \
214 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll3), st_stm32u5_pll_clock, okay) || \
215 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll3), st_stm32h7rs_pll_clock, okay)
217 #define STM32_PLL3_M_DIVISOR DT_PROP(DT_NODELABEL(pll3), div_m)
218 #define STM32_PLL3_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll3), mul_n)
219 #define STM32_PLL3_P_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll3), div_p)
220 #define STM32_PLL3_P_DIVISOR DT_PROP_OR(DT_NODELABEL(pll3), div_p, 1)
221 #define STM32_PLL3_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll3), div_q)
222 #define STM32_PLL3_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(pll3), div_q, 1)
223 #define STM32_PLL3_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll3), div_r)
[all …]
|
| /Zephyr-latest/dts/bindings/clock/ |
| D | st,stm32f1-clock-mco.yaml | 30 /* PLL3 clock divided by 2 */
32 /* PLL3 clock */
|
| D | st,stm32h7-pll-clock.yaml | 7 It can be used to describe 3 different PLLs: PLL1 (Main PLL), PLL2 and PLL3.
8 Only PLL1 and PLL3 are supported for now.
|
| D | st,stm32u5-pll-clock.yaml | 7 It can be used to describe 3 different PLLs: PLL1, PLL2 and PLL3.
72 No restrictions for PLL2 and PLL3
|
| D | st,stm32h7rs-pll-clock.yaml | 7 It can be used to describe 3 different PLLs: PLL1 (Main PLL), PLL2 and PLL3.
|
| /Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/boards/ |
| D | spi1_pll3p_1_d1ppre_4.overlay | 12 &pll3 {
|
| D | core_init.overlay | 60 &pll3 {
|
| /Zephyr-latest/soc/nxp/imxrt/imxrt10xx/ |
| D | lpm_rt1064.c | 213 /* Set Flexspi divider before increasing frequency of PLL3 PDF0. */ in clock_full_power()
222 /* Init USB1 PLL. This will disable the PLL3 bypass. */ in clock_full_power()
256 /* Set PLL3 to bypass mode, output 24M clock */ in clock_low_power()
260 /* Change flexspi to use PLL3 PFD0 with no divisor (24M flexspi clock) */ in clock_low_power()
263 /* FLEXSPI1 mux to PLL3 PFD0 BYPASS */ in clock_low_power()
268 /* FLEXSPI2 mux to PLL3 PFD0 BYPASS */ in clock_low_power()
|
| D | soc.c | 202 CLOCK_SetMux(kCLOCK_UartMux, 0); /* Set UART source to PLL3 80M */ in clock_init()
|
| /Zephyr-latest/boards/shields/st_b_lcd40_dsi1_mb1166/boards/ |
| D | stm32h747i_disco_stm32h747xx_m7.overlay | 21 &pll3 {
|
| /Zephyr-latest/soc/nxp/imx/imx8m/m7/ |
| D | soc.c | 75 /* SYSTEM PLL3 configuration */
80 .postDiv = 2U, /*!< SYSTEM PLL3 frequency = 600MHZ */
89 * and SYSTEM PLL3 by U-Boot. Therefore, there is no need to configure the system PLL again in SOC_ClockInit()
|
| /Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_core/boards/ |
| D | clear_clocks.overlay | 55 &pll3 {
|
| /Zephyr-latest/soc/nxp/imxrt/imxrt118x/ |
| D | soc.c | 163 /* Init Sys Pll3. */ in clock_init()
165 /* Init System Pll3 pfd0. */ in clock_init()
167 /* Init System Pll3 pfd1. */ in clock_init()
169 /* Init System Pll3 pfd2. */ in clock_init()
171 /* Init System Pll3 pfd3. */ in clock_init()
|
| /Zephyr-latest/soc/nxp/imxrt/imxrt11xx/ |
| D | soc.c | 291 /* Init Sys Pll3. */ in clock_init()
294 /* Init System Pll3 pfd0. */ in clock_init()
297 /* Init System Pll3 pfd1. */ in clock_init()
300 /* Init System Pll3 pfd2. */ in clock_init()
303 /* Init System Pll3 pfd3. */ in clock_init()
|
| /Zephyr-latest/drivers/clock_control/ |
| D | clock_stm32_ll_h5.c | 560 /* Configure PLL3 source */ in set_up_plls()
580 /* Set VCO Input before enabling the PLL, depends on the freq of the PLL3 */ in set_up_plls()
582 /* Select VCO freq range before enabling the PLL, depends on the freq of the PLL3 */ in set_up_plls()
608 /* Init PLL3 source to None */ in set_up_plls()
|
| D | clock_stm32_ll_u5.c | 648 /* Configure PLL3 source */ in set_up_plls()
695 /* Init PLL3 source to None */ in set_up_plls()
|
| /Zephyr-latest/boards/fanke/fk750m1_vbt6/ |
| D | fk750m1_vbt6.dts | 92 &pll3 {
|
| /Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/src/ |
| D | test_stm32_clock_configuration.c | 75 "Expected SPI src: PLL3 P (0x%x). Actual: 0x%x", in ZTEST()
|
| /Zephyr-latest/dts/arm/st/h5/ |
| D | stm32h562.dtsi | 16 pll3: pll3 { label
|
| /Zephyr-latest/boards/st/stm32h750b_dk/ |
| D | stm32h750b_dk.dts | 130 &pll3 {
|
| /Zephyr-latest/boards/st/stm32h7b3i_dk/ |
| D | stm32h7b3i_dk.dts | 106 &pll3 {
|
| /Zephyr-latest/boards/st/steval_stwinbx1/ |
| D | steval_stwinbx1.dts | 106 &pll3 {
|
| /Zephyr-latest/dts/arm/st/u5/ |
| D | stm32u5.dtsi | 144 pll3: pll3 { label
|
| /Zephyr-latest/dts/arm/st/h7rs/ |
| D | stm32h7rs.dtsi | 148 pll3: pll@2 { label
|
| /Zephyr-latest/dts/arm/st/h7/ |
| D | stm32h7.dtsi | 117 pll3: pll@2 { label
|
