Searched full:mtl (Results 1 – 18 of 18) sorted by relevance
| /Zephyr-latest/tests/arch/xtensa/save_restore_hifi/ |
| D | testcase.yaml | 2 arch.xtensa.save_restore_hifi.mtl:
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| /Zephyr-latest/tests/drivers/mm/sys_mm_drv_bank/ |
| D | testcase.yaml | 6 filter: dt_compat_enabled("intel,adsp-mtl-tlb") or dt_compat_enabled("intel,adsp-tlb")
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| /Zephyr-latest/tests/drivers/mm/sys_mm_drv_api/ |
| D | testcase.yaml | 6 filter: dt_compat_enabled("intel,adsp-mtl-tlb") or dt_compat_enabled("intel,adsp-tlb")
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| /Zephyr-latest/dts/bindings/mm/ |
| D | intel,adsp-mtl-tlb.yaml | 7 compatible: "intel,adsp-mtl-tlb"
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| /Zephyr-latest/dts/bindings/ethernet/ |
| D | snps,dwcxgmac.yaml | 56 Specifies the size of the MTL Transmit FIFO
71 Specifies the size of the MTL Receive FIFO
312 mtl-raa:
318 mtl-etsalg:
359 These field control the threshold level of the MTL Tx Queue.
360 Transmission starts when the packet size within the MTL Tx
378 when the packet size within the MTL Rx queue is larger than
401 starts when a full packet resides in the MTL Tx Queue.
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| /Zephyr-latest/soc/intel/intel_adsp/ace/ |
| D | Kconfig.defconfig.series | 12 # MTL leaves the upper mapping in the same spot as cAVS, but moves the
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| /Zephyr-latest/boards/intel/adsp/ |
| D | board.cmake | 28 board_set_rimage_target(mtl)
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| /Zephyr-latest/drivers/ethernet/dwc_xgmac/ |
| D | eth_dwc_xgmac_priv.h | 597 /* Transmit Threshold Control. These bits control the threshold level of the MTL TX Queue.
598 * Transmission starts when the packet size within the MTL TX Queue is larger than the
608 * packet resides in the MTL TX Queue. When this bit is set, the values specified in the TTC
631 /* Receive Queue Threshold Control. These bits control the threshold level of the MTL Rx
667 * MTL interrupt status register value
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| D | eth_dwc_xgmac.c | 132 /* XGMAC MTL configuration */
343 /* Configure MTL operation mode options */ in dwxgmac_dma_mtl_init()
363 * Below sequence of register initializations are required for the MTL transmit in dwxgmac_dma_mtl_init()
368 * - Configure MTL TX queue options and enable the TX queue. in dwxgmac_dma_mtl_init()
824 /* Handle MTL interrupts */ in eth_dwc_xgmac_mtl_isr()
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| /Zephyr-latest/drivers/ethernet/eth_nxp_enet_qos/ |
| D | eth_nxp_enet_qos_mac.c | 522 * MTL = MAC Translation Layer. in eth_nxp_enet_qos_mac_init()
523 * MTL is an asynchronous circuit needed because the MAC transmitter/receiver in eth_nxp_enet_qos_mac_init()
524 * and the DMA interface are on different clock domains, MTL compromises the two. in eth_nxp_enet_qos_mac_init()
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| /Zephyr-latest/dts/xtensa/intel/ |
| D | intel_adsp_ace15_mtpm.dtsi | 544 * masking layer makes it easier for MTL to handle
605 compatible = "intel,adsp-mtl-tlb";
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| D | intel_adsp_ace30.dtsi | 612 * masking layer makes it easier for MTL to handle
626 compatible = "intel,adsp-mtl-tlb";
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| D | intel_adsp_ace30_ptl.dtsi | 617 * masking layer makes it easier for MTL to handle
631 compatible = "intel,adsp-mtl-tlb";
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| D | intel_adsp_ace20_lnl.dtsi | 463 compatible = "intel,adsp-mtl-tlb";
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| /Zephyr-latest/drivers/ethernet/ |
| D | eth_cyclonev_priv.h | 454 /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */
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| D | eth_dwmac_priv.h | 645 * MTL Register Definitions
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| /Zephyr-latest/soc/intel/intel_adsp/tools/ |
| D | cavstool.py | 499 # Resize fw_bytes for MTL
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| /Zephyr-latest/doc/releases/ |
| D | release-notes-3.2.rst | 1099 * :dtcompatible:`intel,adsp-mtl-tlb`
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