1# Copyright (c) 2022-2024 Intel Corporation 2# SPDX-License-Identifier: Apache-2.0 3 4if SOC_SERIES_INTEL_ADSP_ACE 5 6config SMP 7 default y 8 9config POWER_DOMAIN 10 default y 11 12# MTL leaves the upper mapping in the same spot as cAVS, but moves the 13# lower one inexplicably. 14config XTENSA_UNCACHED_REGION 15 default 2 16 17# Parameters for gen_isr_tables.py: 18 19config 2ND_LVL_INTR_00_OFFSET 20 default 4 21 22config MULTI_LEVEL_INTERRUPTS 23 default y 24 25config MAX_IRQ_PER_AGGREGATOR 26 default 29 27 28config NUM_2ND_LEVEL_AGGREGATORS 29 default 1 30 31config 2ND_LVL_ISR_TBL_OFFSET 32 default 9 33 34config 2ND_LEVEL_INTERRUPTS 35 default y 36 37config XTENSA_TIMER 38 default n 39 40config XTENSA_TIMER_ID 41 default 0 42 43config SYS_CLOCK_TICKS_PER_SEC 44 default 100 if INTEL_ADSP_SIM 45 default 12000 46 47config INTEL_ADSP_TIMER 48 default y 49 50config DYNAMIC_INTERRUPTS 51 default y 52 53if LOG 54 55config LOG_BACKEND_ADSP 56 default y 57 58endif # LOG 59 60config XTENSA_MORE_SPIN_RELAX_NOPS 61 default y if SMP && MP_MAX_NUM_CPUS > 1 62 63if XTENSA_MORE_SPIN_RELAX_NOPS 64 65config XTENSA_NUM_SPIN_RELAX_NOPS 66 default 32 if MP_MAX_NUM_CPUS = 1 67 default 64 if MP_MAX_NUM_CPUS = 2 68 default 96 if MP_MAX_NUM_CPUS = 3 69 default 128 if MP_MAX_NUM_CPUS = 4 70 default 160 if MP_MAX_NUM_CPUS = 5 71 72endif # XTENSA_MORE_SPIN_RELAX_NOPS 73 74if KERNEL_VM_SUPPORT 75 76config KERNEL_VM_SIZE 77 default 0xfe0000 78 79endif 80 81rsource "Kconfig.defconfig.ace*" 82 83endif # SOC_SERIES_INTEL_ADSP_ACE 84
