| /Zephyr-latest/drivers/pinctrl/ |
| D | pinctrl_lpc_iocon.c | 21 static volatile uint32_t *iocon =
22 (volatile uint32_t *)DT_REG_ADDR(DT_NODELABEL(iocon));
47 *(iocon + offset) = pin_mux; in pinctrl_configure_pins()
53 /* LPC family (except 11u6x) needs iocon clock to be enabled */
57 /* Enable IOCon clock */ in pinctrl_clock_init()
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| D | Kconfig.lpc_iocon | 5 bool "IOCON Pin controller driver for NXP LPC MCUs"
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| /Zephyr-latest/dts/bindings/pinctrl/ |
| D | nxp,rt-iocon-pinctrl.yaml | 40 compatible: "nxp,rt-iocon-pinctrl"
45 description: iMX RT IOCON pin controller pin group
48 iMX RT IOCON pin controller pin configuration node
72 Pin output slew rate. Sets the SLEWRATE field in the IOCON register.
83 IOCON register.
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| D | nxp,lpc-iocon.yaml | 4 description: LPC I/O Pin Configuration (IOCON)
6 compatible: "nxp,lpc-iocon"
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| D | nxp,lpc-iocon-pio.yaml | 4 description: LPC I/O Pin Configuration (IOCON) Port I/O (PIO)
6 compatible: "nxp,lpc-iocon-pio"
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| D | nxp,lpc11u6x-pinctrl.yaml | 8 - name: nxp,lpc-iocon-pinctrl.yaml
19 description: LPC IOCON pin controller pin group
22 LPC IOCON pin controller pin configuration node
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| D | nxp,lpc-iocon-pinctrl.yaml | 50 compatible: "nxp,lpc-iocon-pinctrl"
55 description: LPC IOCON pin controller pin group
58 LPC IOCON pin controller pin configuration node
83 Pin output slew rate. Sets the SLEW field in the IOCON register.
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| /Zephyr-latest/dts/arm/nxp/ |
| D | nxp_lpc11u6x.dtsi | 54 iocon: iocon@40044000 { label
55 compatible = "nxp,lpc-iocon";
65 compatible = "nxp,lpc-iocon-pio";
70 compatible = "nxp,lpc-iocon-pio";
75 compatible = "nxp,lpc-iocon-pio";
92 iocon = <&pio0>;
108 iocon = <&pio1>;
126 iocon = <&pio2>;
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| D | nxp_lpc51u68.dtsi | 51 iocon: iocon@40001000 { label
52 compatible = "nxp,lpc-iocon";
58 compatible = "nxp,lpc-iocon-pinctrl";
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| D | nxp_lpc54xxx.dtsi | 106 iocon: iocon@40001000 { label
107 compatible = "nxp,lpc-iocon";
113 compatible = "nxp,lpc-iocon-pinctrl";
|
| D | nxp_lpc55S0x_common.dtsi | 109 iocon: iocon@1000 { label
110 compatible = "nxp,lpc-iocon";
116 compatible = "nxp,lpc-iocon-pinctrl";
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| D | nxp_lpc55S2x_common.dtsi | 123 iocon: iocon@1000 { label
124 compatible = "nxp,lpc-iocon";
130 compatible = "nxp,lpc-iocon-pinctrl";
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| D | nxp_lpc55S1x_common.dtsi | 116 iocon: iocon@1000 { label
117 compatible = "nxp,lpc-iocon";
123 compatible = "nxp,lpc-iocon-pinctrl";
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| D | nxp_lpc55S3x_common.dtsi | 109 iocon: iocon@1000 { label
110 compatible = "nxp,lpc-iocon";
116 compatible = "nxp,lpc-iocon-pinctrl";
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| D | nxp_lpc55S6x_common.dtsi | 153 iocon: iocon@1000 { label
154 compatible = "nxp,lpc-iocon";
160 compatible = "nxp,lpc-iocon-pinctrl";
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| D | nxp_rt6xx_common.dtsi | 113 iocon: iocon@4000 { label
114 compatible = "nxp,lpc-iocon";
117 compatible = "nxp,rt-iocon-pinctrl";
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| D | nxp_rt5xx_common.dtsi | 133 iocon: iocon@4000 { label
134 compatible = "nxp,lpc-iocon";
137 compatible = "nxp,rt-iocon-pinctrl";
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| /Zephyr-latest/dts/bindings/gpio/ |
| D | nxp,lpc11u6x-gpio.yaml | 28 iocon:
|
| /Zephyr-latest/drivers/gpio/ |
| D | gpio_mcux_lpc.c | 47 #ifdef IOCON
92 #ifdef IOCON /* LPC SOCs */ in gpio_mcux_lpc_configure()
138 #ifdef IOCON /* LPC SOCs */ in gpio_mcux_lpc_configure()
151 #ifdef IOCON /* LPC SOCs */ in gpio_mcux_lpc_configure()
433 #ifdef IOCON
434 #define PINMUX_BASE IOCON
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| D | gpio_mcp23xxx.c | 75 * @brief Writes to the IOCON register of the mcp23xxx.
77 * IOCON is the only register that is not 16 bits wide on 16-pin devices; instead, it is mirrored in
79 * 16-pin devices, make sure we write the same value to both IOCON locations.
82 * @param value the IOCON value to write
94 drv_data->reg_cache.iocon = extended_value; in write_iocon()
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| D | gpio_mcp23xxx.h | 90 uint16_t iocon; member
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| D | gpio_mcp230xx.c | 82 .reg_cache.defval = 0x0, .reg_cache.intcon = 0x0, .reg_cache.iocon = 0x0, \
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| D | gpio_mcp23sxx.c | 120 .reg_cache.defval = 0x0, .reg_cache.intcon = 0x0, .reg_cache.iocon = 0x0, \
|
| /Zephyr-latest/boards/seagate/faze/doc/ |
| D | index.rst | 56 | IOCON | on-chip | pinmux |
73 The IOCON controller can be used to configure the LPC11U67 pins.
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| /Zephyr-latest/boards/nxp/lpcxpresso11u68/doc/ |
| D | index.rst | 54 | IOCON | on-chip | pinmux |
73 The IOCON controller can be used to configure the LPC11U68 pins.
|
