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/Zephyr-latest/dts/bindings/pwm/
Dinfineon,xmc4xxx-ccu8-pwm.yaml2 # SPDX-License-Identifier: Apache-2.0
7 The PWM CCU8 module can automatically generate a high-side
8 and a low-side PWM signal, where the two signals are complementary
11 The module supports adding a dead time between the high-side and
12 low-side PWM signals.
15 transitions from 0 to 1, preventing the high-side and low-side
20 two channels. A channel consists of a corresponding high-side
21 and low-side PWM signal.
25 defined by the 'slice-prescaler' property. Additionally, each
38 slice-prescaler = <15 15 15 15>;
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/Zephyr-latest/dts/bindings/qspi/
Dnxp,s32-qspi.yaml2 # SPDX-License-Identifier: Apache-2.0
10 compatible: "nxp,s32-qspi"
12 include: [base.yaml, pinctrl-device.yaml]
20 "#address-cells":
23 "#size-cells":
26 data-rate:
29 - SDR
30 - DDR
33 - Single Data Rate (SDR): sampling of incoming data occurs on single edges.
34 - Double Data Rate (DDR): sampling of incoming data occurs on both edges.
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/Zephyr-latest/subsys/logging/backends/
DKconfig.swo2 # SPDX-License-Identifier: Apache-2.0
15 …default $(dt_node_int_prop_int,$(dt_nodelabel_path,itm),swo-ref-frequency) if $(dt_nodelabel_enabl…
16 …default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) if $(dt_node_has_prop,/cpus/cpu@0,cloc…
27 supported by the given MCU. Not all debug probes support high
44 Use UART-like NRZ encoding. This is the most common option, but requires the SWO output
45 frequency to be known on the receiving side.
51 recovered automatically on the receiving side.
56 backend-str = swo
/Zephyr-latest/dts/bindings/serial/
Dst,stm32-uart-base.yaml2 # SPDX-License-Identifier: Apache-2.0
5 description: STM32 UART-BASE
8 - name: uart-controller.yaml
9 property-blocklist:
10 - clock-frequency
11 - name: pinctrl-device.yaml
12 - name: reset-device.yaml
13 - name: uart-controller-pin-inversion.yaml
28 single-wire:
31 Enable the single wire half-duplex communication.
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/Zephyr-latest/boards/adafruit/qt_py_esp32s3/
Dadafruit_qt_py_esp32s3_procpu.dts5 * SPDX-License-Identifier: Apache-2.0
8 /dts-v1/;
11 #include <zephyr/dt-bindings/led/led.h>
12 #include <zephyr/dt-bindings/input/input-event-codes.h>
13 #include "adafruit_qt_py_esp32s3-pinctrl.dtsi"
19 compatible = "seeed,xiao-esp32s3";
24 zephyr,shell-uart = &usb_serial;
26 zephyr,code-partition = &slot0_partition;
27 zephyr,bt-hci = &esp32_bt_hci;
31 i2c-0 = &i2c0;
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/Zephyr-latest/include/zephyr/drivers/
Dipm.h4 * @brief Generic low-level inter-processor mailbox communication API.
10 * SPDX-License-Identifier: Apache-2.0
37 * interrupt-safe APIS. Registration of callbacks is done via
115 * finishes. If there is deferred processing on the remote side,
117 * event/semaphore, a high-level driver can implement that.
123 * The @a size parameter is used only on the sending side to determine
125 * to the receiving side. The upper-level protocol dictates the amount of
129 * @param wait If nonzero, busy-wait for remote to consume the message. The
131 * finishes. If there is deferred processing on the remote side,
133 * event/semaphore, you can implement that in a high-level driver
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Despi_emul.h4 * SPDX-License-Identifier: Apache-2.0
43 * @param level The level of signal requested LOW(0) or HIGH(1).
46 * @retval -EIO General input / output error.
60 * @retval -EIO General input / output error.
83 * @param chipsel Chip-select value
90 * Triggers an event on the emulator of eSPI controller side which causes
97 * @retval -EIO General input / output error.
113 /** Target emulator - REQUIRED for all emulated bus nodes of any type */
117 /** eSPI chip-select of the emulated device */
142 * Sets the eSPI virtual wire on the host side, which will
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/Zephyr-latest/boards/infineon/xmc47_relax_kit/
Dxmc47_relax_kit.dts2 * SPDX-License-Identifier: Apache-2.0
8 /dts-v1/;
11 #include <infineon/cat3/xmc/xmc4700_F144x2048-intc.dtsi>
12 #include <zephyr/dt-bindings/pwm/pwm.h>
13 #include "xmc47_relax_kit-pinctrl.dtsi"
22 die-temp0 = &die_temp;
23 pwm-led0 = &pwm_led1;
29 compatible = "gpio-leds";
40 compatible = "pwm-leds";
55 zephyr,shell-uart = &usic0ch0;
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/Zephyr-latest/samples/drivers/i2s/echo/src/
Dcodec.c4 * SPDX-License-Identifier: Apache-2.0
44 * [4:0] LINVOL = 0x07 (-24 dB) in init_wm8731_i2c()
56 * [7:6] SIDEATT = 0 (-6 dB) in init_wm8731_i2c()
57 * [5] SIDETONE = 0 (Disable Side Tone) in init_wm8731_i2c()
70 * [0] ADCHPD = 1 (Disable High Pass Filter) in init_wm8731_i2c()
78 * [4] LRP = 1 (Right Channel DAC data when DACLRC high) in init_wm8731_i2c()
99 * Down Control register to 0 at the very end of the power-on in init_wm8731_i2c()
106 printk("%s is not ready\n", i2c_dev->name); in init_wm8731_i2c()
/Zephyr-latest/soc/intel/intel_adsp/common/include/
Dcavs-idc.h4 * SPDX-License-Identifier: Apache-2.0
21 * the system (including itself). When the high bit becomes 1 in an
29 * the high bit of TFC is written with a 1, the value becomes ZERO,
41 * the PRID of the CPU, equal to arch_curr_cpu()->id in Zephyr) to
47 * And the other side (on cpu "dst", generally in the IDC interrupt
51 * IDC[dst].core[src].tfc = BIT(31); // clear high bit to signal completion
59 * to signal with an interrupt via either ITC (set high "BUSY" bit) or
60 * TFC (clear high "DONE" bit). This masking is in ADDITION to the
61 * level 2 bit for IDC in the per-core INTCTRL DSP register AND the
89 * level 2-5 interrupts). The "mask" field shows the current masking
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/Zephyr-latest/soc/nordic/nrf53/
Dsync_rtc.c4 * SPDX-License-Identifier: Apache-2.0
18 * Setting high value prolongs synchronization process but setting too low may
25 static int32_t nrf53_sync_offset = -EBUSY;
37 /* Algorithm for establishing RTC offset on the network side.
42 * consists of two stages: Getting offset on APP side, passing this offset to
54 * to the value captured on APP side.
64 * Note, arbitrary delay is used to accommodate for the case when NET-APP offset
65 * is small enough that interrupt latency would impact it. NET-APP offset depends
124 return -ENOSYS; in z_nrf_rtc_timer_nrf53net_offset_get()
180 nrf53_sync_offset = cc - RTC_SYNC_ARBITRARY_DELAY - 2 * sync_cc; in remote_callback()
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/Zephyr-latest/boards/adafruit/qt_py_rp2040/
Dadafruit_qt_py_rp2040.dts5 * SPDX-License-Identifier: Apache-2.0
8 /dts-v1/;
11 #include "adafruit_qt_py_rp2040-pinctrl.dtsi"
14 #include <zephyr/dt-bindings/led/led.h>
20 zephyr,flash-controller = &ssi;
22 zephyr,shell-uart = &uart1;
23 zephyr,code-partition = &code_partition;
28 led-strip = &ws2812;
36 compatible = "fixed-partitions";
37 #address-cells = <1>;
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/Zephyr-latest/boards/seeed/xiao_rp2040/
Dxiao_rp2040.dts5 * SPDX-License-Identifier: Apache-2.0
8 /dts-v1/;
11 #include "xiao_rp2040-pinctrl.dtsi"
14 #include <zephyr/dt-bindings/led/led.h>
15 #include <zephyr/dt-bindings/pwm/pwm.h>
21 zephyr,flash-controller = &ssi;
23 zephyr,shell-uart = &uart0;
24 zephyr,code-partition = &code_partition;
29 led-strip = &ws2812;
30 pwm-led0 = &pwm_led0;
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/Zephyr-latest/soc/native/inf_clock/
Dsoc.c4 * SPDX-License-Identifier: Apache-2.0
8 * For all purposes, Zephyr threads see a CPU running at an infinitely high
48 * other side.
/Zephyr-latest/dts/bindings/gpio/
Dadi,max14916-gpio.yaml3 # SPDX-License-Identifier: Apache-2.0
7 compatible: "adi,max14916-gpio"
10 "#gpio-cells":
17 drdy-gpios:
19 High-Side Open-Drain Output. READY is passive low when the internal
22 type: phandle-array
23 fault-gpios:
27 type: phandle-array
28 sync-gpios:
31 type: phandle-array
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Dadi,max14906-gpio.yaml3 # SPDX-License-Identifier: Apache-2.0
7 compatible: "adi,max14906-gpio"
10 "#gpio-cells":
17 drdy-gpios:
19 High-Side Open-Drain Output. READY is passive low when the internal
22 type: phandle-array
23 fault-gpios:
27 type: phandle-array
28 sync-gpios:
31 type: phandle-array
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/Zephyr-latest/drivers/spi/
Dspi_rpi_pico_pio.c4 * SPDX-License-Identifier: Apache-2.0
56 /* ------------ */
58 /* ------------ */
66 0x6101, /* 0: out pins, 1 side 0 [1] */
67 0x5101, /* 1: in pins, 1 side 1 [1] */
71 /* ------------ */
73 /* ------------ */
81 0x7021, /* 0: out x, 1 side 1 */
82 0xa101, /* 1: mov pins, x side 0 [1] */
83 0x5001, /* 2: in pins, 1 side 1 */
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Dspi_nrfx_spis.c4 * SPDX-License-Identifier: Apache-2.0
65 const struct spi_nrfx_config *dev_config = dev->config; in configure()
66 struct spi_nrfx_data *dev_data = dev->data; in configure()
67 struct spi_context *ctx = &dev_data->ctx; in configure()
74 if (spi_cfg->operation & SPI_HALF_DUPLEX) { in configure()
75 LOG_ERR("Half-duplex not supported"); in configure()
76 return -ENOTSUP; in configure()
79 if (SPI_OP_MODE_GET(spi_cfg->operation) == SPI_OP_MODE_MASTER) { in configure()
80 LOG_ERR("Master mode is not supported on %s", dev->name); in configure()
81 return -EINVAL; in configure()
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/Zephyr-latest/tests/bsim/bluetooth/mesh/
DREADME.rst4 This directory contains a set of high level system tests for the Bluetooth Mesh
37 device number with -dXXX to the process.
42 ..code-block::
51 ...code-block::
54 -s=mesh_transport_seg_block -d=0 -RealEncryption=1 \
55 -testid=transport_tx_seg_block
71 ..code-block::
81 Common target side mesh behavior is collected in mesh_test.c and mesh_test.h.
109 has been called - otherwise, it will fail.
/Zephyr-latest/tests/kernel/stack/stack/src/
Dtest_stack_contexts.c4 * SPDX-License-Identifier: Apache-2.0
41 for (int i = STACK_LEN - 1; i >= 0; i--) { in tstack_pop()
70 /**TESTPOINT: thread-thread data passing via stack*/ in tstack_thread_thread()
81 /* clear the spawn thread to avoid side effect */ in tstack_thread_thread()
88 /**TESTPOINT: thread-isr data passing via stack*/ in tstack_thread_isr()
168 /**TESTPOINT: thread-thread data passing via stack*/ in ZTEST()
179 /* clear the spawn thread to avoid side effect */ in ZTEST()
185 zassert_true(ret == -ENOMEM, in ZTEST()
220 * @brief Test multi-threads to get data from stack.
224 * creating the two high priority threads.
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/Zephyr-latest/boards/st/stm32h747i_disco/doc/
Dindex.rst7 from audio, multi-sensor support, graphics, security, video,
8 and high-speed connectivity features.
10 The board includes an STM32H747XI SoC with a high-performance DSP, Arm Cortex-M7 + Cortex-M4 MCU,
12 large set of peripherals, SMPS, and MIPI-DSI.
16 - On-board ST-LINK/V3E supporting USB reenumeration capability
17 - USB ST-LINK functions: virtual COM port, mass storage, debug port
18 - Flexible power-supply options:
20 - ST-LINK USB VBUS, USB OTG HS connector, or external sources
22 - 4” capacitive touch LCD display module with MIPI® DSI interface
23 - Ethernet compliant with IEEE802.3-2002
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/Zephyr-latest/boards/st/nucleo_h745zi_q/doc/
Dindex.rst6 The STM32 Nucleo-144 board provides an affordable and flexible way for users
15 The STM32 Nucleo-144 board does not require any separate probe as it integrates
16 the ST-LINK V3 debugger/programmer.
18 The STM32 Nucleo-144 board comes with the STM32 comprehensive free software
23 - STM32 microcontroller in LQFP144 package
24 - Ethernet compliant with IEEE-802.3-2002 (depending on STM32 support)
25 - USB OTG or full-speed device (depending on STM32 support)
26 - 3 user LEDs
27 - 2 user and reset push-buttons
28 - 32.768 kHz crystal oscillator
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/Zephyr-latest/drivers/interrupt_controller/
Dintc_ioapic.c2 * Copyright (c) 1997-1998, 2000-2002, 2004, 2006-2008, 2011-2015 Wind River
5 * SPDX-License-Identifier: Apache-2.0
19 * The 8259A interrupt controller is intended for use in a uni-processor
20 * system, IO APIC can be used in either a uni-processor or multi-processor
23 * - Method of Interrupt Transmission. The IO APIC transmits interrupts
24 * through a 3-wire bus and interrupts are handled without the need for
26 * - Interrupt Priority. The priority of interrupts in the IO APIC is
29 * - More Interrupts. The IO APIC supports a total of 24 interrupts.
31 * The IO APIC unit consists of a set of interrupt input signals, a 24-entry
32 * by 64-bit Interrupt Redirection Table, programmable registers, and a message
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/Zephyr-latest/doc/services/sensing/
Dindex.rst13 Sensing Subsystem is a high level sensor framework inside the OS user
33 sensor device driver can focus on low layer device side works, can keep
38 protocols, the target is to support various up-layer frameworks and
40 such as `CHRE <https://github.com/zephyrproject-rtos/chre>`_, HID sensors Applications,
42 Applications with different up-layer sensor protocols at the same time
48 The diagram below illustrates how the Sensing Subsystem integrates with up-layer frameworks.
58 * Based on Zephyr existing low-level Sensor API (reuse 100+ existing sensor device drivers)
59 * Provide Zephyr high-level Sensing Subsystem API for Applications.
127 This method is suitable for supporting some up-layer frameworks like ``CHRE``, ``HID`` which need
137 .. code-block:: c
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/Zephyr-latest/boards/st/nucleo_h743zi/doc/
Dindex.rst6 The STM32 Nucleo-144 boards offer combinations of performance and power that
8 out new concepts. For compatible boards, the SMPS (Switched-Mode Power Supply)
11 The Arduino-compatible ST Zio connector expands functionality of the Nucleo
15 The STM32 Nucleo-144 board does not require any separate probe as it integrates
16 the ST-LINK/V2-1 debugger/programmer.
18 The STM32 Nucleo-144 board comes with the STM32 comprehensive free software
23 - STM32 microcontroller in LQFP144 package
24 - Ethernet compliant with IEEE-802.3-2002 (depending on STM32 support)
25 - USB OTG or full-speed device (depending on STM32 support)
26 - 3 user LEDs
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