1# Copyright (c) 2024 Analog Devices Inc.
2# Copyright (c) 2024 BayLibre SAS
3# SPDX-License-Identifier: Apache-2.0
4
5description: ADI  MAX14916 is octal industrial output with advanced diagnostics
6
7compatible: "adi,max14916-gpio"
8
9properties:
10  "#gpio-cells":
11    const: 2
12  ngpios:
13    type: int
14    required: true
15    const: 8
16    description: Number of gpios supported
17  drdy-gpios:
18    description: |
19      High-Side Open-Drain Output. READY is passive low when the internal
20      logic supply is higher than the UVLO threshold, indicating that the
21      registers have adequate supply voltage.
22    type: phandle-array
23  fault-gpios:
24    description: |
25      Fault pin indicates when there is Fault state in either FAULT1 or FAULT2
26      bothe of which are cleaned on read once problem is not persistent
27    type: phandle-array
28  sync-gpios:
29    description: |
30      Latch the data so it could be read (partially duplicate CS)
31    type: phandle-array
32  en-gpios:
33    description: |
34      DOI Enable Pin. Drive the EN pin high to enable the DOI_ outputs.
35      Drive EN low to disable/three-state all DOI_ outputs.
36    type: phandle-array
37  crc-en:
38    description: |
39      Notify driver if crc pin is enabled.
40    type: boolean
41  spi-addr:
42    type: int
43    default: 0
44    required: true
45    enum:
46      - 0
47      - 1
48      - 2
49      - 3
50    description: |
51      On MAX14906PMB module default address is 0 (A0-LOW, A1-LOW)
52      Selectable device address, configurable from A0 and A1
53  ow-on-en:
54    type: array
55    default: [0, 0, 0, 0, 0, 0, 0, 0]
56    description: |
57      Default values are from documentation.
58      Enable or disable open-wire-on functionality per channel.
59      - 0 mean disable
60      - 1 mean enable
61      channels indentation start from CH0...CH7
62  ow-off-en:
63    type: array
64    default: [0, 0, 0, 0, 0, 0, 0, 0]
65    description: |
66      Default values are from documentation.
67      Enable or disable open-wire-off functionality per channel.
68      - 0 mean disable
69      - 1 mean enable
70      channels indentation start from CH0...CH7
71  sh-vdd-en:
72    type: array
73    default: [0, 0, 0, 0, 0, 0, 0, 0]
74    description: |
75      Default values are from documentation.
76      ShVddEN - Short to VDD enable
77      Enable or disable short to VDD functionality per channel.
78      - 0 mean disable
79      - 1 mean enable
80      channels indentation start from CH0...CH3
81  fled-set:
82    type: boolean
83    description: |
84      Internal fault diagnostics include (if enabled): SafeDemagF_, SHVDD_,
85      VDDOV_, OWOff_, AboveVDD_, CL_, OVL_, VDDOKFault_.
86  sled-set:
87    type: boolean
88    description: |
89      Enable status LEDs
90  fled-stretch:
91    type: int
92    default: 0
93    enum:
94      - 0
95      - 1
96      - 2
97      - 3
98    description: |
99      Default values are from documentation.
100      Set minimum on time for FLEDs in case of fault
101      0 - Disable minimum fault LED (FLED) on-time
102      1 - Minimum fault LED (FLED) on-time = 1s (typ)
103      2 - Minimum fault LED (FLED) on-time = 2s (typ)
104      3 - Minimum fault LED (FLED) on-time = 3s (typ)
105  ffilter-en:
106    type: boolean
107    description: |
108      When the fault LEDs (FLEDs) are controlled internally (FLEDSet = 0), open-
109      wire and short-to-V DD diagnostics always use filtering and cannot be disabled
110      by the FFilterEn bit.
111  filter-long:
112    type: boolean
113    description: |
114      false: To select regular blanking time (4ms, typ) for diagnostic fault bits, OWOff_
115             and SHVDD_
116      true:  To select long blanking time (8ms, typ) for diagnostic fault bits, OWOff_
117             and SHVDD_
118  flatch-en:
119    type: boolean
120    description: |
121      false: Disable latching of diagnostic fault bits in the OvrLdChF, OpnWirChF, and
122             ShtVDDChF registers
123      true:  Enable latching of diagnostic fault bits in the OvrLdChF, OpnWirChF, and
124             ShtVDDChF registers
125  led-cur-lim:
126    type: boolean
127    description: |
128      false: Disable fault LEDs (FLEDs) signaling current limit
129      true:  Enable fault LEDs (FLEDs) signaling current limit
130  vdd-on-thr:
131    type: boolean
132    description: |
133      Enable higher voltage thresholds for VDD and VDD_ undervoltage monitoring
134  synch-wd-en:
135    type: boolean
136    description: |
137      The SYNCH watchdog timeout is defined by the WDTo[1:0] bits if the SPI
138      watchdog is enabled. When WDTo[1:0] = 00 (SPI watchdog disabled), the
139      SYNCH watchdog timeout is 600ms (typ) if enabled.
140  sht-vdd-thr:
141    type: int
142    default: 0
143    enum:
144      - 0
145      - 1
146      - 2
147      - 3
148    description: |
149      Default values are from documentation.
150      Set threshold voltage for short-to-V DD detection
151      0: Set threshold voltage for short-to-VDD detection to 9V (typ)
152      1: Set threshold voltage for short-to-VDD detection to 10V (typ)
153      2: Set threshold voltage for short-to-VDD detection to 12V (typ)
154      3: Set threshold voltage for short-to-VDD detection to 14V (typ)
155  ow-off-cs:
156    type: int
157    default: 0
158    enum:
159      - 0
160      - 1
161      - 2
162      - 3
163    description: |
164      Default values are from documentation.
165      Set the pullup current for open-wire and short-to-VDD detection
166      0: Set open-wire and short-to-VDD detection current to 60μA (typ)
167      1: Set open-wire and short-to-VDD detection current to 100μA (typ)
168      2: Set open-wire and short-to-VDD detection current to 300μA (typ)
169      3: Set open-wire and short-to-VDD detection current to 600μA (typ)
170  wd-to:
171    type: int
172    default: 0
173    enum:
174      - 0
175      - 1
176      - 2
177      - 3
178    description: |
179      Default values are from documentation.
180      SPI Watchdog Status, set SPI and SYNCH Watchdog Timeout
181      0: Disable SPI Watchdog Status and SPI Watchdog Timeout
182      1: Enable SPI Watchdog Status, set SPI and SYNCH Watchdog Timeout to 200ms (typ)
183      2: Enable SPI Watchdog Status, set SPI and SYNCH Watchdog Timeout to 600ms (typ)
184      3: Enable SPI Watchdog Status, set SPI and SYNCH Watchdog Timeout to 1.2s (typ)
185
186gpio-cells:
187  - pin
188  - flags
189
190include: [gpio-controller.yaml, spi-device.yaml]
191