Lines Matching +full:high +full:- +full:side

2  * Copyright (c) 1997-1998, 2000-2002, 2004, 2006-2008, 2011-2015 Wind River
5  * SPDX-License-Identifier: Apache-2.0
19  * The 8259A interrupt controller is intended for use in a uni-processor
20  * system, IO APIC can be used in either a uni-processor or multi-processor
23  *  - Method of Interrupt Transmission. The IO APIC transmits interrupts
24  *    through a 3-wire bus and interrupts are handled without the need for
26  *  - Interrupt Priority. The priority of interrupts in the IO APIC is
29  *  - More Interrupts. The IO APIC supports a total of 24 interrupts.
31  * The IO APIC unit consists of a set of interrupt input signals, a 24-entry
32  * by 64-bit Interrupt Redirection Table, programmable registers, and a message
34  * Front-Side (system) bus.  IO devices inject interrupts into the system by
42  * or the Front-Side (system) bus).  IO APIC is used in the Symmetric IO Mode.
46  * to 15 are edge triggered positive high, and for IRQ 16 to 23 are level
81  * In this case, LDR is read-only to system software and supports up to 16
343 		ret = -ENOTSUP;  in ioapic_pm_action()
475  * This routine reads the low-order 32 bits of a Redirection Table entry.
478  * @return 32 low-order bits
491  * This routine writes the low-order 32 bits of a Redirection Table entry.
505  * @brief Set high 32 bits of Redirection Table entry
507  * This routine writes the high-order 32 bits of a Redirection Table entry.
523  * This routine modifies selected portions of the low-order 32 bits of a