Home
last modified time | relevance | path

Searched full:apb2 (Results 1 – 25 of 282) sorted by relevance

12345678910>>...12

/Zephyr-latest/include/zephyr/dt-bindings/clock/
Dch32v00x-clocks.h22 #define CH32V00X_CLOCK_AFIO CH32V00X_CLOCK_CONFIG(APB2, 0)
23 #define CH32V00X_CLOCK_IOPA CH32V00X_CLOCK_CONFIG(APB2, 2)
24 #define CH32V00X_CLOCK_IOPB CH32V00X_CLOCK_CONFIG(APB2, 3)
25 #define CH32V00X_CLOCK_IOPC CH32V00X_CLOCK_CONFIG(APB2, 4)
26 #define CH32V00X_CLOCK_IOPD CH32V00X_CLOCK_CONFIG(APB2, 5)
27 #define CH32V00X_CLOCK_ADC1 CH32V00X_CLOCK_CONFIG(APB2, 9)
28 #define CH32V00X_CLOCK_ADC2 CH32V00X_CLOCK_CONFIG(APB2, 10)
29 #define CH32V00X_CLOCK_TIM1 CH32V00X_CLOCK_CONFIG(APB2, 11)
30 #define CH32V00X_CLOCK_SPI1 CH32V00X_CLOCK_CONFIG(APB2, 12)
31 #define CH32V00X_CLOCK_USART1 CH32V00X_CLOCK_CONFIG(APB2, 14)
/Zephyr-latest/dts/arm/st/f0/
Dstm32f091.dtsi31 clocks = <&rcc STM32_CLOCK(APB2, 5U)>;
32 resets = <&rctl STM32_RESET(APB2, 5U)>;
40 clocks = <&rcc STM32_CLOCK(APB2, 6U)>;
41 resets = <&rctl STM32_RESET(APB2, 6U)>;
49 clocks = <&rcc STM32_CLOCK(APB2, 7U)>;
50 resets = <&rctl STM32_RESET(APB2, 7U)>;
Dstm32f0.dtsi176 clocks = <&rcc STM32_CLOCK(APB2, 14U)>;
177 resets = <&rctl STM32_RESET(APB2, 14U)>;
203 clocks = <&rcc STM32_CLOCK(APB2, 12U)>;
236 clocks = <&rcc STM32_CLOCK(APB2, 11U)>;
237 resets = <&rctl STM32_RESET(APB2, 11U)>;
297 clocks = <&rcc STM32_CLOCK(APB2, 17U)>;
298 resets = <&rctl STM32_RESET(APB2, 17U)>;
319 clocks = <&rcc STM32_CLOCK(APB2, 18U)>;
320 resets = <&rctl STM32_RESET(APB2, 18U)>;
341 clocks = <&rcc STM32_CLOCK(APB2, 9U)>;
Dstm32f070.dtsi25 clocks = <&rcc STM32_CLOCK(APB2, 16U)>;
26 resets = <&rctl STM32_RESET(APB2, 16U)>;
/Zephyr-latest/dts/arm/st/f1/
Dstm32f103Xg.dtsi35 clocks = <&rcc STM32_CLOCK(APB2, 19U)>;
36 resets = <&rctl STM32_RESET(APB2, 19U)>;
52 clocks = <&rcc STM32_CLOCK(APB2, 20U)>;
53 resets = <&rctl STM32_RESET(APB2, 20U)>;
69 clocks = <&rcc STM32_CLOCK(APB2, 21U)>;
70 resets = <&rctl STM32_RESET(APB2, 21U)>;
Dstm32f103Xc.dtsi109 clocks = <&rcc STM32_CLOCK(APB2, 7U)>;
117 clocks = <&rcc STM32_CLOCK(APB2, 8U)>;
124 clocks = <&rcc STM32_CLOCK(APB2, 10U)>;
134 clocks = <&rcc STM32_CLOCK(APB2, 15U)>;
143 clocks = <&rcc STM32_CLOCK(APB2, 13U)>;
144 resets = <&rctl STM32_RESET(APB2, 13U)>;
Dstm32f1.dtsi139 clocks = <&rcc STM32_CLOCK(APB2, 2U)>;
147 clocks = <&rcc STM32_CLOCK(APB2, 3U)>;
155 clocks = <&rcc STM32_CLOCK(APB2, 4U)>;
163 clocks = <&rcc STM32_CLOCK(APB2, 5U)>;
171 clocks = <&rcc STM32_CLOCK(APB2, 6U)>;
178 clocks = <&rcc STM32_CLOCK(APB2, 14U)>;
179 resets = <&rctl STM32_RESET(APB2, 14U)>;
231 clocks = <&rcc STM32_CLOCK(APB2, 12U)>;
253 clocks = <&rcc STM32_CLOCK(APB2, 11U)>;
254 resets = <&rctl STM32_RESET(APB2, 11U)>;
[all …]
/Zephyr-latest/dts/arm/st/f4/
Dstm32f411.dtsi26 clocks = <&rcc STM32_CLOCK(APB2, 20U)>;
36 clocks = <&rcc STM32_CLOCK(APB2, 12U)>;
49 clocks = <&rcc STM32_CLOCK(APB2, 13U)>;
62 clocks = <&rcc STM32_CLOCK(APB2, 20U)>;
Dstm32f413.dtsi52 clocks = <&rcc STM32_CLOCK(APB2, 6U)>;
53 resets = <&rctl STM32_RESET(APB2, 6U)>;
61 clocks = <&rcc STM32_CLOCK(APB2, 7U)>;
62 resets = <&rctl STM32_RESET(APB2, 7U)>;
Dstm32f429.dtsi27 clocks = <&rcc STM32_CLOCK(APB2, 26U)>;
28 resets = <&rctl STM32_RESET(APB2, 26U)>;
Dstm32f4.dtsi240 clocks = <&rcc STM32_CLOCK(APB2, 4U)>;
241 resets = <&rctl STM32_RESET(APB2, 4U)>;
258 clocks = <&rcc STM32_CLOCK(APB2, 5U)>;
259 resets = <&rctl STM32_RESET(APB2, 5U)>;
305 clocks = <&rcc STM32_CLOCK(APB2, 12U)>;
327 clocks = <&rcc STM32_CLOCK(APB2, 0U)>;
328 resets = <&rctl STM32_RESET(APB2, 0U)>;
462 clocks = <&rcc STM32_CLOCK(APB2, 16U)>;
463 resets = <&rctl STM32_RESET(APB2, 16U)>;
484 clocks = <&rcc STM32_CLOCK(APB2, 17U)>;
[all …]
Dstm32f410.dtsi33 clocks = <&rcc STM32_CLOCK(APB2, 20U)>;
43 clocks = <&rcc STM32_CLOCK(APB2, 12U)>;
69 clocks = <&rcc STM32_CLOCK(APB2, 20U)>;
Dstm32f427.dtsi58 clocks = <&rcc STM32_CLOCK(APB2, 13U)>;
71 clocks = <&rcc STM32_CLOCK(APB2, 20U)>;
84 clocks = <&rcc STM32_CLOCK(APB2, 21U)>;
/Zephyr-latest/dts/arm/st/l0/
Dstm32l051.dtsi38 clocks = <&rcc STM32_CLOCK(APB2, 14U)>;
39 resets = <&rctl STM32_RESET(APB2, 14U)>;
47 clocks = <&rcc STM32_CLOCK(APB2, 5U)>;
48 resets = <&rctl STM32_RESET(APB2, 5U)>;
Dstm32l031.dtsi16 clocks = <&rcc STM32_CLOCK(APB2, 5U)>;
17 resets = <&rctl STM32_RESET(APB2, 5U)>;
Dstm32l010Xb.dtsi29 clocks = <&rcc STM32_CLOCK(APB2, 5U)>;
30 resets = <&rctl STM32_RESET(APB2, 5U)>;
/Zephyr-latest/dts/arm/st/f7/
Dstm32f746.dtsi19 clocks = <&rcc STM32_CLOCK(APB2, 26U)>;
20 resets = <&rctl STM32_RESET(APB2, 26U)>;
Dstm32f767.dtsi20 clocks = <&rcc STM32_CLOCK(APB2, 26U)>;
21 resets = <&rctl STM32_RESET(APB2, 26U)>;
Dstm32f7.dtsi257 clocks = <&rcc STM32_CLOCK(APB2, 4U)>;
258 resets = <&rctl STM32_RESET(APB2, 4U)>;
302 clocks = <&rcc STM32_CLOCK(APB2, 5U)>;
303 resets = <&rctl STM32_RESET(APB2, 5U)>;
367 clocks = <&rcc STM32_CLOCK(APB2, 12U)>;
397 clocks = <&rcc STM32_CLOCK(APB2, 13U)>;
407 clocks = <&rcc STM32_CLOCK(APB2, 20U)>;
424 clocks = <&rcc STM32_CLOCK(APB2, 0U)>;
425 resets = <&rctl STM32_RESET(APB2, 0U)>;
561 clocks = <&rcc STM32_CLOCK(APB2, 1U)>;
[all …]
Dstm32f722.dtsi38 clocks = <&rcc STM32_CLOCK(APB2, 7U)>,
40 resets = <&rctl STM32_RESET(APB2, 7U)>;
Dstm32f765.dtsi66 clocks = <&rcc STM32_CLOCK(APB2, 21U)>;
87 clocks = <&rcc STM32_CLOCK(APB2, 7U)>,
89 resets = <&rctl STM32_RESET(APB2, 7U)>;
/Zephyr-latest/dts/arm/st/l4/
Dstm32l4r9.dtsi20 clocks = <&rcc STM32_CLOCK(APB2, 26U)>;
21 resets = <&rctl STM32_RESET(APB2, 26U)>;
/Zephyr-latest/dts/arm/st/f3/
Dstm32f303.dtsi78 clocks = <&rcc STM32_CLOCK(APB2, 11U)>;
79 resets = <&rctl STM32_RESET(APB2, 11U)>;
112 clocks = <&rcc STM32_CLOCK(APB2, 13U)>;
113 resets = <&rctl STM32_RESET(APB2, 13U)>;
129 clocks = <&rcc STM32_CLOCK(APB2, 20U)>;
130 resets = <&rctl STM32_RESET(APB2, 20U)>;
Dstm32f334.dtsi17 clocks = <&rcc STM32_CLOCK(APB2, 11U)>;
18 resets = <&rctl STM32_RESET(APB2, 11U)>;
/Zephyr-latest/dts/arm/st/f2/
Dstm32f2.dtsi234 clocks = <&rcc STM32_CLOCK(APB2, 4U)>;
235 resets = <&rctl STM32_RESET(APB2, 4U)>;
261 clocks = <&rcc STM32_CLOCK(APB2, 5U)>;
262 resets = <&rctl STM32_RESET(APB2, 5U)>;
290 clocks = <&rcc STM32_CLOCK(APB2, 12U)>;
368 clocks = <&rcc STM32_CLOCK(APB2, 8U)>;
412 clocks = <&rcc STM32_CLOCK(APB2, 0U)>;
413 resets = <&rctl STM32_RESET(APB2, 0U)>;
544 clocks = <&rcc STM32_CLOCK(APB2, 1U)>;
545 resets = <&rctl STM32_RESET(APB2, 1U)>;
[all …]

12345678910>>...12