Searched +full:96 +full:mhz (Results 1 – 25 of 148) sorted by relevance
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| /Zephyr-latest/dts/arm/nuvoton/npcm/ |
| D | npcm4.dtsi | 27 clock-frequency = <DT_FREQ_M(96)>; /* OFMCLK runs at 96MHz */
28 core-prescaler = <1>; /* CORE_CLK runs at 96MHz */
29 apb1-prescaler = <8>; /* APB1_CLK runs at 12MHz */
30 apb2-prescaler = <1>; /* APB2_CLK runs at 96MHz */
31 apb3-prescaler = <1>; /* APB3_CLK runs at 96MHz */
32 ahb6-prescaler = <1>; /* APB6_CLK runs at 96MHz */
33 fiu-prescaler = <1>; /* FIU_CLK runs at 96MHz */
34 i3c-prescaler = <1>; /* I3C_CLK runs at 96MHz */
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| /Zephyr-latest/dts/bindings/clock/ |
| D | nuvoton,npcm-pcc.yaml | 14 clock-frequency = <DT_FREQ_M(96)>; /* OFMCLK runs at 96MHz */
15 core-prescaler = <1>; /* CORE_CLK runs at 96MHz */
16 apb1-prescaler = <8>; /* APB1_CLK runs at 12MHz */
17 apb2-prescaler = <1>; /* APB2_CLK runs at 96MHz */
18 apb3-prescaler = <1>; /* APB3_CLK runs at 96MHz */
19 apb6-prescaler = <1>; /* APB6_CLK runs at 96MHz */
20 fiu-prescaler = <1>; /* FIU_CLK runs at 96MHz */
21 i3c-prescaler = <1>; /* I3C_CLK runs at 96MHz */
38 100000000, 100 MHz
39 96000000, 96 MHz
[all …]
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| D | st,stm32l0-pll-clock.yaml | 8 input frequency from 2 to 24 MHz.
16 The PLL output frequency must not exceed 32 MHz.
45 - 96 MHz when the product is in Range 1
46 - 48 MHz when the product is in Range 2
47 - 24 MHz when the product is in Range 3
49 programmed to output a 96 MHz frequency (USBCLK = PLLVCO/2).
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| D | microchip,xec-pcr.yaml | 17 description: Divide 96 MHz PLL clock to produce Cortex-M4 core clock
22 PWM and TACH clock domain divided down from 48 MHz AHB clock. The
43 32KHz clock monitor minimum valid 32KHz period in 48MHz units
49 32KHz clock monitor maximum valid 32KHz period in 48MHz units
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| D | nuvoton,npcx-pcc.yaml | 14 clock-frequency = <DT_FREQ_M(100)>; /* OFMCLK runs at 100MHz */
15 core-prescaler = <5>; /* CORE_CLK runs at 20MHz */
16 apb1-prescaler = <5>; /* APB1_CLK runs at 20MHz */
17 apb2-prescaler = <5>; /* APB2_CLK runs at 20MHz */
18 apb3-prescaler = <5>; /* APB3_CLK runs at 20MHz */
35 120000000, 120 MHz
36 100000000, 100 MHz
37 96000000, 96 MHz
38 90000000, 90 MHz
39 80000000, 80 MHz
[all …]
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| /Zephyr-latest/boards/96boards/stm32_sensor_mez/doc/ |
| D | index.rst | 3 96Boards STM32 Sensor Mezzanine
9 96Boards STM32 Sensor Mezzanine is based on the ST Microelectronics
12 This board acts as a mezzanine platform for all 96Boards CE compliant
15 .. figure:: img/96b_stm32_sensor_mez.jpg
17 :alt: 96Boards STM32 Sensor Mezzanine
19 96Boards STM32 Sensor Mezzanine
24 96Boards STM32 Sensor Mezzanine provides the following hardware components:
28 - 180 MHz max CPU frequency
49 The Zephyr 96b_stm32_sensor_mez board configuration supports the following
77 :zephyr_file:`boards/96boards/stm32_sensor_mez/96b_stm32_sensor_mez_defconfig`
[all …]
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| /Zephyr-latest/boards/google/dragonclaw/ |
| D | google_dragonclaw.dts | 26 /* HSI clock frequency is 16MHz */
37 mul-n = <192>; /* 16MHz * 192/8 = 384MHz VCO clock */
38 div-p = <4>; /* 96MHz PLL general clock output */
39 div-q = <8>; /* 48MHz PLL output for USB, SDIO, RNG */
46 clocks = <&pll>; /* Select PLL as SYSCLK source (96MHz) */
48 clock-frequency = <DT_FREQ_M(96)>; /* AHB frequency */
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| /Zephyr-latest/boards/96boards/argonkey/doc/ |
| D | index.rst | 3 96Boards Argonkey
9 96Boards Argonkey board is based on the ST Microelectronics STM32F412CG
12 This board acts as a sensor hub platform for all 96Boards compliant
15 .. figure:: img/96b_argonkey.jpg
17 :alt: 96Boards Argonkey
19 96Boards Argonkey
24 96Boards Argonkey provides the following hardware components:
28 - 100 MHz max CPU frequency
54 The Zephyr 96b_argonkey board configuration supports the following hardware
81 :zephyr_file:`boards/96boards/argonkey/96b_argonkey_defconfig`
[all …]
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| /Zephyr-latest/boards/96boards/avenger96/doc/ |
| D | index.rst | 3 96Boards Avenger96
9 96Boards Avenger96 board is based on ST Microelectronics STM32MP157A
16 - RAM: 1024 Mbyte @ 533MHz
44 .. image:: img/96b_avenger96.jpg
46 :alt: 96Boards Avenger96
49 `96Boards website`_.
66 - Up to 209 MHz (Up to 703 CoreMark®)
78 - Internal oscillators: 64 MHz HSI oscillator, 4 MHz CSI oscillator, 32 kHz
80 - External oscillators: 8-48 MHz HSE oscillator, 32.768 kHz LSE oscillator
108 - 2 × 12-bit D/A converters (1 MHz)
[all …]
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| /Zephyr-latest/soc/ene/kb1200/ |
| D | soc.c | 31 /* AHB/APB clock select 96MHz/48MHz */ in clock_init()
34 /* AHB/APB clock select 48MHz/24MHz */ in clock_init()
37 /* AHB/APB clock select 24MHz/12MHz */ in clock_init()
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| /Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_core/boards/ |
| D | pll_hsi_96.overlay | 13 hsi-div = <8>; /* HSI RC: 64MHz, hsi_clk = 8MHz */
29 clock-frequency = <DT_FREQ_M(96)>;
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| D | pll_csi_96.overlay | 13 status = "okay"; /* CSI RC: 4MHz */
28 clock-frequency = <DT_FREQ_M(96)>;
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| D | pll_hse_96.overlay | 14 clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
30 clock-frequency = <DT_FREQ_M(96)>;
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| /Zephyr-latest/soc/microchip/mec/mec174x/ |
| D | soc.h | 10 #define SYSCLK_DEFAULT_IOSC_HZ MHZ(96)
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| /Zephyr-latest/soc/microchip/mec/mec175x/ |
| D | soc.h | 10 #define SYSCLK_DEFAULT_IOSC_HZ MHZ(96)
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| /Zephyr-latest/soc/microchip/mec/mech172x/ |
| D | soc.h | 10 #define SYSCLK_DEFAULT_IOSC_HZ MHZ(96)
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| /Zephyr-latest/soc/telink/tlsr/tlsr951x/ |
| D | soc.c | 24 /* Define 48 MHz and 96 MHz CCLK clock options (not present in HAL) */
66 #error "Unsupported clock-frequency. Supported values: 16, 24, 32, 48, 64 and 96 MHz"
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| /Zephyr-latest/boards/96boards/neonkey/doc/ |
| D | index.rst | 3 96Boards Neonkey
9 96Boards Neonkey board is based on the STMicroelectronics STM32F411CE
12 .. figure:: img/96b_neonkey.jpg
14 :alt: 96Boards Neonkey
16 96Boards Neonkey
18 This board acts as a sensor hub platform for all 96Boards compliant
24 96Boards Neonkey provides the following hardware components:
28 - 84 MHz max CPU frequency
52 The Zephyr 96b_neonkey board configuration supports the following hardware
75 More details about the board can be found at `96Boards website`_.
[all …]
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| /Zephyr-latest/boards/microchip/mec172xevb_assy6906/ |
| D | Kconfig.defconfig | 26 # SYSTICK. SYSTICK frequency is 96 MHz divided down by the MEC172x PCR
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| /Zephyr-latest/boards/microchip/mec172xmodular_assy6930/ |
| D | Kconfig.defconfig | 26 # SYSTICK. SYSTICK frequency is 96 MHz divided down by the MEC172x PCR
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| /Zephyr-latest/boards/96boards/carbon/doc/ |
| D | nrf51822.rst | 3 96Boards Carbon nRF51
9 This is the secondary nRF51822 chip on the 96Boards Carbon and provides
15 :ref:`96b_carbon_board`. Users should not use this configuration
23 The 96Boards Carbon nRF51 has two external oscillators. The frequency
25 MHz.
27 See :ref:`96b_carbon_board` for other general information about the
53 :zephyr_file:`boards/96boards/carbon/96b_carbon_nrf51822_defconfig`
61 96Boards Carbon nRF51 has one SPI, which for providing Bluetooth
80 The 96Boards Carbon nRF51 can be flashed using an external SWD
85 .. figure:: img/96b_carbon_nrf51.jpg
[all …]
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| /Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h5_core/boards/ |
| D | pll_hse25_240.overlay | 19 hse-bypass; /* X3 is a 25MHz oscillator on PH0 */
26 mul-n = <96>;
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| /Zephyr-latest/samples/boards/96boards/argonkey/microphone/ |
| D | README.rst | 22 - mezzanine mode, plugging the ArgonKey to HiKey board through its 96Board
29 - :ref:`96b_argonkey`
35 :zephyr-app: samples/boards/96boards/argonkey/microphone
37 :board: 96b_argonkey
65 oversampling/decimation factor equal to 128, resulting in a 2.048MHz bit clock.
67 See pcm and pdm configuration in file :zephyr_file:`samples/boards/96boards/argonkey/microphone/src…
74 following macro, off by default, in :zephyr_file:`samples/boards/96boards/argonkey/microphone/src/m…
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| /Zephyr-latest/soc/nxp/lpc/lpc55xxx/ |
| D | soc.c | 41 /*Should be in the range of 12MHz to 32MHz */
97 /* Set up FRO to the 12 MHz, to ensure we can change the clock freq */ in clock_init()
99 /* Switch to FRO 12MHz first to ensure we can change the clock */ in clock_init()
106 /* Setting the Core Clock to either 96MHz or in the case of using PLL, 144MHz */ in clock_init()
134 /* Enable FRO HF(SystemCoreClock) output (Default expected value 96MHz) */ in clock_init()
196 /* attach 12 MHz clock to FLEXCOMM4 */ in clock_init()
217 /* Attach 12 MHz clock to HSLSPI */ in clock_init()
222 /* Enable 1 MHz FRO clock for WWDT */ in clock_init()
381 /* Initialize FRO/system clock to 96 MHz */ in nxp_lpc55xxx_init()
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| /Zephyr-latest/boards/ene/kb1200_evb/doc/ |
| D | index.rst | 63 The KB1200 MCU is configured to use the 96Mhz internal oscillator with the
64 on-chip DPLL to generate a resulting EC clock rate of 96MHz/48MHz/24MHz/12MHz.
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