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/Zephyr-latest/dts/bindings/cpu/
Despressif,riscv.yaml16 - 0: ESP32_CPU_CLK_SRC_XTAL - Uses the external crystal clock typically at 40 MHz.
18 320 MHz or 480 MHz.
20 frequency of 17.5 MHz.
29 description: Value of the external XTAL connected to ESP32. This is typically 40 MHz.
Despressif,xtensa-lx6.yaml16 - 0: ESP32_CPU_CLK_SRC_XTAL - Uses the external crystal clock typically at 40 MHz.
18 320 MHz or 480 MHz.
20 frequency of 17.5 MHz. 8 MHz for ESP32S2.
21 - 3: APLL_CLK - 16 Mhz ~ 128 MHz
Despressif,xtensa-lx7.yaml16 - 0: ESP32_CPU_CLK_SRC_XTAL - Uses the external crystal clock typically at 40 MHz.
18 320 MHz or 480 MHz.
20 frequency of 17.5 MHz. 8 MHz for ESP32S2.
21 - 3: APLL_CLK - 16 Mhz ~ 128 MHz (ESP32S2 Only)
/Zephyr-latest/include/zephyr/dt-bindings/ethernet/
Dxlnx_gem.h28 #define XLNX_GEM_MDC_DIVIDER_8 0 /* cpu_1x or IOU_SWITCH_CLK < 20 MHz */
29 #define XLNX_GEM_MDC_DIVIDER_16 1 /* cpu_1x or IOU_SWITCH_CLK 20 - 40 MHz */
30 #define XLNX_GEM_MDC_DIVIDER_32 2 /* cpu_1x or IOU_SWITCH_CLK 40 - 80 MHz */
31 #define XLNX_GEM_MDC_DIVIDER_48 3 /* cpu_1x or IOU_SWITCH_CLK 80 - 120 MHz */
32 #define XLNX_GEM_MDC_DIVIDER_64 4 /* cpu_1x or IOU_SWITCH_CLK 120 - 160 MHz */
33 #define XLNX_GEM_MDC_DIVIDER_96 5 /* cpu_1x or IOU_SWITCH_CLK 160 - 240 MHz */
34 #define XLNX_GEM_MDC_DIVIDER_128 6 /* cpu_1x or IOU_SWITCH_CLK 240 - 320 MHz */
35 #define XLNX_GEM_MDC_DIVIDER_224 7 /* cpu_1x or IOU_SWITCH_CLK 320 - 540 MHz */
/Zephyr-latest/dts/bindings/pinctrl/
Dnxp,imx8m-pinctrl.yaml15 drive-strength = "40-ohm";
81 - "40-ohm"
93 110 45_OHM — 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
94 111 40_OHM — 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
105 00 SLOW — Slow Frequency Slew Rate (50Mhz)
106 01 MEDIUM — Medium Frequency Slew Rate (100Mhz)
107 10 FAST — Fast Frequency Slew Rate (150Mhz)
108 11 MAX — Max Frequency Slew Rate (200Mhz)
/Zephyr-latest/drivers/spi/
Dspi_esp32_spim.h17 #define SPI_MASTER_FREQ_9M (APB_CLK_FREQ/9) /* 8.89MHz */
18 #define SPI_MASTER_FREQ_10M (APB_CLK_FREQ/8) /* 10MHz */
19 #define SPI_MASTER_FREQ_11M (APB_CLK_FREQ/7) /* 11.43MHz */
20 #define SPI_MASTER_FREQ_13M (APB_CLK_FREQ/6) /* 13.33MHz */
21 #define SPI_MASTER_FREQ_16M (APB_CLK_FREQ/5) /* 16MHz */
22 #define SPI_MASTER_FREQ_20M (APB_CLK_FREQ/4) /* 20MHz */
23 #define SPI_MASTER_FREQ_26M (APB_CLK_FREQ/3) /* 26.67MHz */
24 #define SPI_MASTER_FREQ_40M (APB_CLK_FREQ/2) /* 40MHz */
25 #define SPI_MASTER_FREQ_80M (APB_CLK_FREQ/1) /* 80MHz */
/Zephyr-latest/tests/drivers/can/timing/
DKconfig33 - 20 MHz
34 - 40 MHz
35 - 80 MHz
/Zephyr-latest/soc/espressif/common/
DKconfig.esptool88 bool "120 MHz"
92 - Flash 120 MHz SDR mode is stable.
93 - Flash 120 MHz DDR mode is an experimental feature, it works when
102 bool "80 MHz"
104 bool "60 MHz"
106 bool "40 MHz"
108 bool "26 MHz"
111 bool "20 MHz"
119 This is an invisible item, used to define the targets that defaults to use 80MHz Flash SPI speed.
128 default '40m' if ESPTOOLPY_FLASHFREQ_40M
DKconfig.spiram87 bool "20MHz clock speed"
91 bool "26MHz clock speed"
95 bool "40MHz clock speed"
98 bool "80MHz clock speed"
102 bool "120MHz clock speed"
111 default 40 if SPIRAM_SPEED_40M || SPIRAM_SPEED_26M || SPIRAM_SPEED_20M
/Zephyr-latest/soc/nuvoton/npcx/
DKconfig51 bool "SPI flash max clock rate of 20 MHz"
54 bool "SPI flash max clock rate of 25 MHz"
57 bool "SPI flash max clock rate of 33 MHz"
61 bool "SPI flash max clock rate of 40 MHz"
64 bool "SPI flash max clock rate of 50 MHz"
72 default 40 if NPCX_HEADER_SPI_MAX_CLOCK_40
/Zephyr-latest/soc/altr/zephyr_nios2f/cpu/
Dghrd_10m50da.qsf200 set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to user_led[0]
201 set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to user_led[2]
202 set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to user_pb[1]
231 set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[0] -ta…
233 set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[1] -ta…
235 set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[2] -ta…
237 set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[3] -ta…
239 set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[4] -ta…
241 set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[5] -ta…
243 set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[6] -ta…
[all …]
/Zephyr-latest/dts/bindings/can/
Dti,tcan4x5x.yaml39 TCAN4x5x oscillator clock frequency in Hz (20MHz or 40MHz).
Dmicrochip,mcp251xfd.yaml65 is not set, then an internal clock (typically 40MHz or 20MHz) will be
/Zephyr-latest/boards/renesas/ek_ra4e2/doc/
Dindex.rst9 The RA4E2 Group delivers up to 100 MHz of CPU performance using an Arm® Cortex®-M33 core
10 with 128 KB of code flash memory, 4 KB of data flash memory, and 40 KB of SRAM. RA4E2 MCUs
16 100 MHz with the following features:
20 - 100 MHz, Arm® Cortex®-M33 core
21 - 128 kB Code Flash, 40 kB SRAM
23 - Native pin access through 2 x 14-pin and 1 x 40-pin male headers
26 20.000 MHz and 32,768 Hz reference clock. Additional low-precision clocks are available internal to…
148 * Target Interface Speed: 4 MHz
164 …ucts/microcontrollers-microprocessors/ra-cortex-m-mcus/ra4e2-entry-line-100mhz-arm-cortex-m33-gene…
/Zephyr-latest/dts/bindings/clock/
Dnuvoton,npcm-pcc.yaml14 clock-frequency = <DT_FREQ_M(96)>; /* OFMCLK runs at 96MHz */
15 core-prescaler = <1>; /* CORE_CLK runs at 96MHz */
16 apb1-prescaler = <8>; /* APB1_CLK runs at 12MHz */
17 apb2-prescaler = <1>; /* APB2_CLK runs at 96MHz */
18 apb3-prescaler = <1>; /* APB3_CLK runs at 96MHz */
19 apb6-prescaler = <1>; /* APB6_CLK runs at 96MHz */
20 fiu-prescaler = <1>; /* FIU_CLK runs at 96MHz */
21 i3c-prescaler = <1>; /* I3C_CLK runs at 96MHz */
38 100000000, 100 MHz
39 96000000, 96 MHz
[all …]
/Zephyr-latest/tests/boards/espressif/rtc_clk/
DREADME.rst55 Testing CPU frequency: 80 MHz
56 Testing CPU frequency: 160 MHz
57 Testing CPU frequency: 240 MHz
61 Testing CPU frequency: 40 MHz
62 Testing CPU frequency: 20 MHz
63 Testing CPU frequency: 10 MHz
64 Testing CPU frequency: 5 MHz
68 Testing RTC FAST CLK freq: 20000000 MHz
69 Testing RTC FAST CLK freq: 17500000 MHz
73 Testing RTC SLOW CLK freq: 136000 MHz
[all …]
/Zephyr-latest/samples/boards/ti/cc13x2_cc26x2/system_off/src/
Dext_flash.c42 * 3 cycles per loop: 8 loops @ 48 Mhz = 0.5 us. in CC1352R1_LAUNCHXL_sendExtFlashByte()
51 * Keep CS high at least 40 us in CC1352R1_LAUNCHXL_sendExtFlashByte()
52 * 3 cycles per loop: 700 loops @ 48 Mhz ~= 44 us in CC1352R1_LAUNCHXL_sendExtFlashByte()
69 /* 3 cycles per loop: 1 loop @ 48 Mhz ~= 62 ns */ in CC1352R1_LAUNCHXL_wakeUpExtFlash()
72 /* 3 cycles per loop: 560 loops @ 48 Mhz ~= 35 us */ in CC1352R1_LAUNCHXL_wakeUpExtFlash()
/Zephyr-latest/boards/shields/p3t1755dp_ard_i2c/doc/
Dindex.rst10 with a -40 °C to 125 °C range.
22 or shutdown mode. The device supports 2-wire serial I3C (up to 12.5 MHz)
23 and I²C (up to 3.4 MHz) as communication interface.
/Zephyr-latest/boards/shields/p3t1755dp_ard_i3c/doc/
Dindex.rst10 with a -40 °C to 125 °C range.
22 or shutdown mode. The device supports 2-wire serial I3C (up to 12.5 MHz)
23 and I²C (up to 3.4 MHz) as communication interface.
/Zephyr-latest/boards/st/stm32u083c_dk/doc/
Dindex.rst13 featuring 256 Kbytes of flash memory and 40 Kbytes of SRAM in an LQFP80 package.
43 They operate at a frequency of up to 56 MHz.
49 - -40 °C to +85/125 °C temperature range
57 - 52 µA/MHz Run mode (LDO mode)
62 - 32-bit Arm |reg| Cortex |reg|-M0+ CPU, frequency up to 56 MHz
70 - 1.13 DMIPS/MHz (Drystone 2.1)
71 - 134 CoreMark |reg| (2.4 CoreMark/MHz at 56 MHz)
79 - 40-Kbyte SRAM with hardware parity check
87 - 4 to 48 MHz crystal oscillator
89 - Internal 16 MHz factory-trimmed RC (±1%)
[all …]
/Zephyr-latest/dts/bindings/sensor/
Dti,fdc2x1x.yaml46 The internal clock oscillates at around 43360 KHz (43.36 MHz)
48 Recommended external clock source frequency is 40000 KHz (40 MHz).
97 1 = 1MHz
98 4 = 3.3MHz
99 5 = 10MHz
100 7 = 33MHz
234 0.01MHz and 8.75MHz
235 2 = divide by 2. Choose for sensor frequencies between 5MHz
236 and 10MHz
240 0.01MHz and 10MHz
/Zephyr-latest/soc/ti/lm3s6965/
Dsoc.h23 #define SYSCLK_DEFAULT_IOSC_HZ MHZ(12)
64 #define IRQ_RESERVED4 40
/Zephyr-latest/boards/shields/lcd_par_s035/
Dlcd_par_s035_8080.overlay40 /* Baud rate on each pin is 1MHz */
53 doca = [40 8A 00 00 29 19 A5 33];
/Zephyr-latest/boards/st/nucleo_u5a5zj_q/doc/
Dindex.rst35 They operate at a frequency of up to 160 MHz.
41 - -40 °C to +85/125 °C temperature range
48 - 2 µA Stop 3 mode with 40-Kbyte SRAM
50 - 4.65 µA Stop 2 mode with 40-Kbyte SRAM
52 - 18.5 µA/MHz Run mode at 3.3 V
59 memories: frequency up to 160 MHz, 240 DMIPS
69 - 1.5 DMIPS/MHz (Drystone 2.1)
70 - 655 CoreMark® (4.09 CoreMark®/MHz)
84 - 16-bit HSPI memory interface up to 160 MHz
104 - 4 to 50 MHz crystal oscillator
[all …]
/Zephyr-latest/boards/gaisler/generic_leon3/doc/
Dindex.rst45 Detected frequency: 50.0 MHz
67 400040A8 initlevel 40B [===============>] 100%
97 system frequency: 50.000 MHz
106 section: initlevel, addr: 0x400040a8, size 40 bytes

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