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/Zephyr-latest/dts/bindings/pinctrl/
Dnxp,mcux-rt-pinctrl.yaml103 default: "47k"
106 - "47k"
107 - "100k"
108 - "22k"
112 47k resistor selected as default due to this being the default pullup
115 01 PUS_1_47K_Ohm_Pull_Up — 47K Ohm Pull Up
116 10 PUS_2_100K_Ohm_Pull_Up — 100K Ohm Pull Up
117 11 PUS_2_22K_Ohm_Pull_Up — 22K Ohm Pull Up
121 default: "100k"
123 - "100k"
[all …]
/Zephyr-latest/soc/ite/ec/it8xxx2/
Dilm.c29 * 0x80100000..0x80101000 (the first 4k block of RAM).
129 "ILM physical base address (%p) must be 4k-aligned", __ilm_ram_start); in it8xxx2_ilm_init()
131 "ILM flash base address (%p) must be 4k-aligned", __ilm_flash_start); in it8xxx2_ilm_init()
201 SCAR_REG(22), SCAR_REG(22), SCAR_REG(22), SCAR_REG(22),
202 SCAR_REG(22), SCAR_REG(22), SCAR_REG(22), SCAR_REG(22),
/Zephyr-latest/boards/ezurio/bt510/
Dbt510.dts32 gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>;
136 /* 96K */
141 /* 396K */
146 /* 396K */
151 /* 8K */
166 /* 128K */
/Zephyr-latest/subsys/net/lib/lwm2m/
Dlwm2m_util.c69 f |= 1 << (22 - i); in lwm2m_float_to_b32()
95 /* fraction: bits 22-0 */ in lwm2m_float_to_b32()
193 int32_t f, k, i, e; in lwm2m_b32_to_float() local
215 /* calc fraction: bits 22-0 */ in lwm2m_b32_to_float()
231 k = PRECISION32; in lwm2m_b32_to_float()
235 k /= 2; in lwm2m_b32_to_float()
239 for (i = 22 - e; i >= 0; i--) { in lwm2m_b32_to_float()
240 k /= 2; in lwm2m_b32_to_float()
242 val2 += k; in lwm2m_b32_to_float()
259 int64_t f, k; in lwm2m_b64_to_float() local
[all …]
/Zephyr-latest/boards/sifive/hifive_unleashed/
Dhifive_unleashed.dtsi29 gpio-map = <22 0 &gpio0 0 0>, /* GPIO-A */
39 <32 0 &gpio0 15 0>; /* GPIO-K */
/Zephyr-latest/boards/pjrc/teensy4/
Dteensy4-pinctrl.dtsi33 bias-pull-up-value = "100k";
47 bias-pull-up-value = "100k";
53 /* FLEXCAN1 TX, RX on Teensy-Pins 22/23 */
170 bias-pull-up-value = "100k";
198 bias-pull-up-value = "100k";
226 bias-pull-up-value = "100k";
254 bias-pull-up-value = "100k";
282 bias-pull-up-value = "100k";
310 bias-pull-up-value = "100k";
338 bias-pull-up-value = "100k";
[all …]
/Zephyr-latest/boards/nxp/mimxrt1062_fmurt6/
Dmimxrt1062_fmurt6-pinctrl.dtsi29 bias-pull-down-value = "100k";
41 bias-pull-up-value = "100k";
47 bias-pull-down-value = "100k";
56 bias-pull-up-value = "100k";
179 bias-pull-up-value = "47k";
191 bias-pull-down-value = "100k";
275 bias-pull-up-value = "47k";
327 bias-pull-up-value = "100k";
339 bias-pull-up-value = "100k";
360 bias-pull-up-value = "100k";
[all …]
/Zephyr-latest/dts/arm/nxp/
Dnxp_lpc55S3x_common.dtsi41 * LPC55x36: RAMX: 16K, SRAM0: 16K, SRAM1: 16K, SRAM2: 32K, SRAM3: 32K, SRAM4: 16K
289 interrupts = <22 0>;
299 dmas = <&dma0 21>, <&dma0 22>;
Dnxp_lpc55S6x_common.dtsi72 * LPC55S66: 144KB RAM, RAMX: 32K, SRAM0: 32K
73 * LPC55S69: 320KB RAM, RAMX: 32K, SRAM0: 64K, SRAM1: 64K,
74 * SRAM2: 64K, SRAM3: 64K, SRAM4: 16K
363 interrupts = <22 0>;
Dnxp_mcxn94x_common.dtsi58 * MCXN94X: 512KB RAM, RAMX: 96K, RAMA: 32K, RAMB: 32K,
59 * RAMC: 64K, RAMD: 64K, RAME: 64K
60 * RAMF: 64K, RAMG: 64K, RAMH: 32K
142 interrupts = <21 0>,<22 0>;
Dnxp_mcxn23x_common.dtsi53 * MCXN23X: 352KB RAM, RAMX: 96K, RAMA: 32K, RAMB: 32K,
54 * RAMC: 64K, RAMD: 64K, RAME: 64K
136 interrupts = <21 0>,<22 0>;
/Zephyr-latest/samples/tfm_integration/psa_crypto/
DREADME.rst270 00000010 58 40 00 11 22 33 44 55 66 77 88 99 AA BB CC DD X@.."3DUfw......
271 00000020 EE FF 00 11 22 33 44 55 66 77 88 99 AA BB CC DD ...."3DUfw......
272 00000030 EE FF 00 11 22 33 44 55 66 77 88 99 AA BB CC DD ...."3DUfw......
273 00000040 EE FF 00 11 22 33 44 55 66 77 88 99 AA BB CC DD ...."3DUfw......
278 00000090 13 24 8C AE 7A D9 E2 98 4B 90 28 0E FC BC B5 02 .$..z...K.(.....
287 00000120 24 25 2B EB 70 D7 2C 6B FC 92 CD BE 5B 65 9E C7 $%+.p.,k....[e..
289 00000140 30 2E 30 2E 30 05 58 20 B3 60 CA F5 C9 8C 6B 94 0.0.0.X .`....k.
294 00000190 A9 22 AD 3A 00 01 25 01 77 77 77 77 2E 74 72 75 .".:..%.wwww.tru
332 00000020 A6 22 2C 64 7A C7 E4 0A FB 99 D1 8B 67 37 F7 13 .",dz.......g7..
345 00000040 92 FF F2 A3 22 4D 2D F6 62 39 6D A5 DD E1 E1 C4 ...."M-.b9m.....
[all …]
/Zephyr-latest/dts/arm/atmel/
Dsam4l.dtsi41 * HRAM1 are 4k SRAM that can be used by PicoCache or just extra
56 interrupts = <22 0>;
116 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>;
/Zephyr-latest/dts/arm/microchip/
Dmec172x_common.dtsi17 pll-32k-src = <MCHP_XEC_PLL_CLK32K_SRC_SIL_OSC>;
18 periph-32k-src = <MCHP_XEC_PERIPH_CLK32K_SRC_SO_SO>;
44 16 17 18 21 22 24 25
55 16 17 18 19 20 21 22 23
66 16 17 18 19 20 21 22 23
77 16 17 18 19 20 21 22 23
88 16 17 18 19 20 21 22 23
116 16 17 18 19 20 22>;
133 16 17 20 21 22 23>;
142 10 20 21 22 23
[all …]
/Zephyr-latest/lib/utils/
Dbase64.c31 'K', 'L', 'M', 'N', 'O', 'P', 'Q', 'R', 'S', 'T',
33 'e', 'f', 'g', 'h', 'i', 'j', 'k', 'l', 'm', 'n',
48 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
/Zephyr-latest/soc/microchip/mec/mec172x/
Dsoc.h16 * from hal_cmsis based on the k-config CPU selection.
19 * MPU present to 0. We define these two symbols here based on our k-config
96 I2C_SMB_2_IRQn = 22, /*!< GIRQ13 b[2] */
136 P80BD_0_IRQn = 62, /*!< GIRQ15 b[22] */
149 RPMFAN_1_FAIL_IRQn = 76, /*!< GIRQ17 b[22] */
214 CCT_CAP1_IRQn = 148, /*!< GIRQ18 b[22] */
/Zephyr-latest/doc/build/cmake/
Dbuild-build-phase-5.svg4 …K+cSc7yS9G9BseLmFI7hsy5x9OLVg2lupQCvOyK4Goa/hSENfxKqrhoOhCimzplEcdcuHOL8DCslioicyIiH9SA4djcOoVLrzd…
Dbuild-build-phase-4.svg4 …K+cSc7yS9G9BseLmFI7hsy5x9OLVg2lupQCvOyK4Goa/hSENfxKqrhoOhCimzplEcdcuHOL8DCslioicyIiH9SA4djcOoVLrzd…
/Zephyr-latest/samples/drivers/ethernet/eth_ivshmem/
DREADME.rst36 * Enable SSH access by appending ``,hostfwd=tcp::2222-:22`` to
143 iperf -l 1K -V -c 192.168.19.2 -p 5001
/Zephyr-latest/drivers/edac/
Dibecc.h78 /* Size of Host Memory Mapped Configuration space (64K) */
164 #define DIMM_S_SIZE(v) (BITFIELD(v, 22, 16) << 29)
/Zephyr-latest/drivers/usb/uhc/
Duhc_max3421e.h83 #define MAX3421E_REG_GPINIRQ 22U
204 /* K-state instead of response */
/Zephyr-latest/arch/arm64/core/
Dmmu.h29 /* Only 4K granule is supported */
65 * (22 <= va_bits <= 30) - base level 2
/Zephyr-latest/tests/net/lib/coap/src/
Dmain.c102 uint8_t result_pdu[] = { 0x55, 0xA5, 0x12, 0x34, 't', 'o', 'k', 'e', in ZTEST()
219 uint8_t pdu[] = { 0x55, 0xA5, 0x12, 0x34, 't', 'o', 'k', 'e', 'n', in ZTEST()
322 uint8_t opt[] = { 0x55, 0xA5, 0x12, 0x34, 't', 'o', 'k', 'e', 'n', in ZTEST()
336 uint8_t opt[] = { 0x55, 0xA5, 0x12, 0x34, 't', 'o', 'k', 'e', 'n', in ZTEST()
350 uint8_t opt[] = { 0x55, 0xA5, 0x12, 0x34, 't', 'o', 'k', 'e', 'n', in ZTEST()
364 uint8_t opt[] = { 0x55, 0xA5, 0x12, 0x34, 't', 'o', 'k', 'e', 'n', in ZTEST()
392 uint8_t pdu[] = { 0x45, 0xA5, 0x12, 0x34, 't', 'o', 'k', 'e', 'n', in ZTEST()
395 uint8_t ack_pdu[] = { 0x65, 0x80, 0x12, 0x34, 't', 'o', 'k', 'e', 'n' }; in ZTEST()
419 uint8_t pdu[] = { 0x45, 0xA5, 0xDE, 0xAD, 't', 'o', 'k', 'e', 'n', in ZTEST()
458 uri = "/k"; in ZTEST()
[all …]
/Zephyr-latest/dts/arm/st/f0/
Dstm32f0.dtsi98 /* maximum erase time for a 2K sector */
169 clocks = <&rcc STM32_CLOCK(AHB1, 22U)>;
321 interrupts = <22 0>;
/Zephyr-latest/dts/arm/st/l5/
Dstm32l5.dtsi138 /* using maximum erase time(ms) for 4K page, since
140 * for a 2K(dual-bank) page.
167 <19 0>, <20 0>, <21 0>, <22 0>,
381 clocks = <&rcc STM32_CLOCK(APB1, 22U)>;
400 clocks = <&rcc STM32_CLOCK(AHB2, 22U)>,
402 resets = <&rctl STM32_RESET(AHB2, 22U)>;

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