Home
last modified time | relevance | path

Searched +full:16 +full:mhz (Results 1 – 25 of 466) sorted by relevance

12345678910>>...19

/Zephyr-latest/dts/bindings/clock/
Dst,stm32g0-hsi-clock.yaml6 On STM32G0, HSI is a 16MHz fixed clock.
12 - 1 ==> HSISYS = 16MHZ
13 - 2 ==> HSISYS = 8MHZ
14 - 4 ==> HSISYS = 4MHZ
15 - 8 ==> HSISYS = 2MHZ
16 - 16 ==> HSISYS = 1MHZ
17 - 32 ==> HSISYS = 0.5MHz
18 - 64 ==> HSISYS = 0.25MHZ
19 - 128 ==> HSISYS = 0.125MHz
38 - 16
Dst,stm32c0-hsi-clock.yaml6 On STM32C0, HSI is a 48MHz fixed clock.
12 - 1 ==> HSISYS = 48MHZ
13 - 2 ==> HSISYS = 24MHZ
14 - 4 ==> HSISYS = 12MHZ
15 - 8 ==> HSISYS = 6MHZ
16 - 16 ==> HSISYS = 3MHZ
17 - 32 ==> HSISYS = 1.5MHz
18 - 64 ==> HSISYS = 0.75MHZ
19 - 128 ==> HSISYS = 0.375MHz
36 - 16
Dst,stm32u5-msi-clock.yaml22 - 0 # range 0 around 48 MHz
23 - 1 # range 1 around 24 MHz
24 - 2 # range 2 around 16 MHz
25 - 3 # range 3 around 12 MHz
26 - 4 # range 4 around 4 MHz (reset value)
27 - 5 # range 5 around 2 MHz
28 - 6 # range 6 around 1.33 MHz
29 - 7 # range 7 around 1 MHz
30 - 8 # range 8 around 3.072 MHz
31 - 9 # range 9 around 1.536 MHz
[all …]
Dst,stm32h7-hsi-clock.yaml17 - 1 # hsi_clk = 64MHz
18 - 2 # hsi_clk = 32MHz
19 - 4 # hsi_clk = 16MHz
20 - 8 # hsi_clk = 8MHz
Dst,stm32-msi-clock.yaml23 - 5 # range 5 around 2 MHz
24 - 6 # range 6 around 4 MHz (reset value)
25 - 7 # range 7 around 8 MHz
26 - 8 # range 8 around 16 MHz
27 - 9 # range 9 around 24 MHz
28 - 10 # range 10 around 32 MHz
29 - 11 # range 11 around 48 MHz
Dst,stm32l0-pll-clock.yaml8 input frequency from 2 to 24 MHz.
16 The PLL output frequency must not exceed 32 MHz.
45 - 96 MHz when the product is in Range 1
46 - 48 MHz when the product is in Range 2
47 - 24 MHz when the product is in Range 3
49 programmed to output a 96 MHz frequency (USBCLK = PLLVCO/2).
56 - 16
/Zephyr-latest/soc/sifive/sifive_freedom/fe300/
Dclock.c20 * HFXOSC (16 MHz) is used to produce coreclk (and therefore tlclk / in soc_early_init_hook()
22 * - 16 MHz (bypass HFPLL). in soc_early_init_hook()
23 * - 48 MHz - 320 MHz, in 8 MHz steps (use HFPLL). in soc_early_init_hook()
25 BUILD_ASSERT(MHZ(16) == CORECLK_HZ || in soc_early_init_hook()
26 (MHZ(48) <= CORECLK_HZ && MHZ(320) >= CORECLK_HZ && in soc_early_init_hook()
27 (CORECLK_HZ % MHZ(8)) == 0), in soc_early_init_hook()
32 if (MHZ(16) == CORECLK_HZ) { in soc_early_init_hook()
36 /* refr = 8 MHz. */ in soc_early_init_hook()
40 /* Select Q divisor to produce vco on [384 MHz, 768 MHz]. */ in soc_early_init_hook()
41 if (MHZ(768) / 8 >= CORECLK_HZ) { in soc_early_init_hook()
[all …]
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_core/boards/
Dhsi_16.overlay12 &clk_hsi { /* HSI RC: 16MHz, hsi_clk = 16MHz */
18 clock-frequency = <DT_FREQ_M(16)>;
Dhsi_g0_16.overlay12 &clk_hsi { /* HSI RC: 16MHz, hsi_clk = 16MHz */
19 clock-frequency = <DT_FREQ_M(16)>;
Dhsi_g0_16_div_2.overlay12 /* hsi_clk = 16MHz */
15 hsi-div = <2>; /* HSISYS = 8Mhz */
Dhsi_g0_16_div_4.overlay12 /* hsi_clk = 16MHz */
15 hsi-div = <4>; /* HSISYS = 4Mhz */
/Zephyr-latest/dts/bindings/cpu/
Despressif,xtensa-lx6.yaml16 - 0: ESP32_CPU_CLK_SRC_XTAL - Uses the external crystal clock typically at 40 MHz.
18 320 MHz or 480 MHz.
20 frequency of 17.5 MHz. 8 MHz for ESP32S2.
21 - 3: APLL_CLK - 16 Mhz ~ 128 MHz
Despressif,xtensa-lx7.yaml16 - 0: ESP32_CPU_CLK_SRC_XTAL - Uses the external crystal clock typically at 40 MHz.
18 320 MHz or 480 MHz.
20 frequency of 17.5 MHz. 8 MHz for ESP32S2.
21 - 3: APLL_CLK - 16 Mhz ~ 128 MHz (ESP32S2 Only)
/Zephyr-latest/soc/snps/arc_iot/
Dsysconf.c11 #define SYSCLK_DEFAULT_IOSC_HZ MHZ(16)
30 /* the following configuration is based on Fin = 16 Mhz */
32 {100, PLL_CONF_VAL(1, 25, 2)}, /* 100 Mhz */
33 {50, PLL_CONF_VAL(1, 25, 3)}, /* 50 Mhz */
34 {150, PLL_CONF_VAL(4, 75, 1)}, /* 150 Mhz */
35 {75, PLL_CONF_VAL(4, 75, 2)}, /* 75 Mhz */
36 {25, PLL_CONF_VAL(2, 25, 3)}, /* 25 Mhz */
37 {72, PLL_CONF_VAL(8, 144, 2)}, /* 72 Mhz */
38 {144, PLL_CONF_VAL(8, 144, 1)}, /* 144 Mhz */
51 * 1 Mhz <= Fref <= 50 Mhz
[all …]
/Zephyr-latest/boards/st/stm32g081b_eval/
Dstm32g081b_eval.dts164 * UCPD is fed directly from HSI which is @ 16MHz. The ucpd_clk goes to
167 * designed to work in freq ranges of 6 <--> 18 MHz, however recommended
168 * range is 9 <--> 18 MHz.
170 * +-------+ @ 16 MHz +-------+ @ ~600 kHz +-----------+
177 * 1. hbit_clk ~= 600 kHz: 16 MHz / 600 kHz = 26.67
195 * UCPD is fed directly from HSI which is @ 16MHz. The ucpd_clk goes to
198 * designed to work in freq ranges of 6 <--> 18 MHz, however recommended
199 * range is 9 <--> 18 MHz.
201 * +-------+ @ 16 MHz +-------+ @ ~600 kHz +-----------+
208 * 1. hbit_clk ~= 600 kHz: 16 MHz / 600 kHz = 26.67
/Zephyr-latest/tests/drivers/clock_control/nrf_clock_control/src/
Dmain.c21 .frequency = MHZ(128),
26 .frequency = MHZ(320),
31 .frequency = MHZ(64),
40 .frequency = MHZ(16),
45 .frequency = MHZ(16),
50 .frequency = MHZ(16),
66 .frequency = MHZ(16),
71 .frequency = MHZ(19),
76 .frequency = MHZ(16),
109 .frequency = MHZ(320),
[all …]
/Zephyr-latest/drivers/spi/
Dspi_esp32_spim.h17 #define SPI_MASTER_FREQ_9M (APB_CLK_FREQ/9) /* 8.89MHz */
18 #define SPI_MASTER_FREQ_10M (APB_CLK_FREQ/8) /* 10MHz */
19 #define SPI_MASTER_FREQ_11M (APB_CLK_FREQ/7) /* 11.43MHz */
20 #define SPI_MASTER_FREQ_13M (APB_CLK_FREQ/6) /* 13.33MHz */
21 #define SPI_MASTER_FREQ_16M (APB_CLK_FREQ/5) /* 16MHz */
22 #define SPI_MASTER_FREQ_20M (APB_CLK_FREQ/4) /* 20MHz */
23 #define SPI_MASTER_FREQ_26M (APB_CLK_FREQ/3) /* 26.67MHz */
24 #define SPI_MASTER_FREQ_40M (APB_CLK_FREQ/2) /* 40MHz */
25 #define SPI_MASTER_FREQ_80M (APB_CLK_FREQ/1) /* 80MHz */
/Zephyr-latest/soc/xlnx/zynq7000/xc7zxxx/
DKconfig.soc20 2 ARM Cortex-A9 cores up to 866 MHz, Artix-7 programmable logic,
27 2 ARM Cortex-A9 cores up to 866 MHz, Artix-7 programmable logic,
35 2 ARM Cortex-A9 cores up to 866 MHz, Artix-7 programmable logic,
52 up to 16 transceivers.
60 up to 16 transceivers.
68 up to 16 transceivers.
/Zephyr-latest/drivers/ieee802154/
DKconfig.mcr20a33 bool "32 MHz"
36 bool "16 MHz"
39 bool "8 MHz"
42 bool "4 MHz"
45 bool "1 MHz"
/Zephyr-latest/soc/nuvoton/npcx/
DKconfig51 bool "SPI flash max clock rate of 20 MHz"
54 bool "SPI flash max clock rate of 25 MHz"
57 bool "SPI flash max clock rate of 33 MHz"
61 bool "SPI flash max clock rate of 40 MHz"
64 bool "SPI flash max clock rate of 50 MHz"
165 bool "SPI flash size 16M Bytes"
167 The SPI flash size is 16M Bytes.
176 default 16 if NPCX_HEADER_FLASH_SIZE_16M
/Zephyr-latest/drivers/clock_control/
Dclock_stm32_ll_wb0.c73 /* When using HSI without PLL, the "16MHz" output is not actually 16MHz, since
75 * The CPU and MR_BLE must be running at 32MHz for MR_BLE to work with HSI.
78 "System clock frequency must be at least 32MHz to use LSI");
80 /* In PLL or Direct HSE mode, the clock is stable, so 16MHz can be used. */
82 "System clock frequency must be at least 16MHz to use LSI");
137 * LSI calibration counts the amount of 16MHz clock half-periods that in measure_lsi_frequency()
140 * @p fast_clock_cycles_elapsed is the number of 16MHz clock half-periods in measure_lsi_frequency()
148 * tCALIB = @p fast_clock_cycles_elapsed / (2 * 16MHz) in measure_lsi_frequency()
154 * ( @p fast_clock_cycles_elapsed / (2 * 16MHz) ) in measure_lsi_frequency()
164 * ( @p fast_clock_cycles_elapsed / (2 * 16MHz) ) in measure_lsi_frequency()
[all …]
/Zephyr-latest/boards/st/nucleo_u031r8/doc/
Dindex.rst36 They operate at a frequency of up to 56 MHz.
44 - 16 nA Shutdown mode (4 wake-up pins)
50 - 52 µA/MHz Run mode
55 - 32-bit Arm |reg| Cortex |reg|-M0+ CPU, frequency up to 56 MHz
63 - 1.13 DMIPS/MHz (Drystone 2.1)
64 - 134 CoreMark |reg| (2.4 CoreMark/MHz at 56 MHz)
80 - 4 to 48 MHz crystal oscillator
82 - Internal 16 MHz factory-trimmed RC (±1%)
84 - Internal multispeed 100 kHz to 48 MHz oscillator,
102 - 1x 16-bit advanced motor-control, 1x 32-bit and 3x 16-bit general purpose,
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/ethernet/
Dxlnx_gem.h28 #define XLNX_GEM_MDC_DIVIDER_8 0 /* cpu_1x or IOU_SWITCH_CLK < 20 MHz */
29 #define XLNX_GEM_MDC_DIVIDER_16 1 /* cpu_1x or IOU_SWITCH_CLK 20 - 40 MHz */
30 #define XLNX_GEM_MDC_DIVIDER_32 2 /* cpu_1x or IOU_SWITCH_CLK 40 - 80 MHz */
31 #define XLNX_GEM_MDC_DIVIDER_48 3 /* cpu_1x or IOU_SWITCH_CLK 80 - 120 MHz */
32 #define XLNX_GEM_MDC_DIVIDER_64 4 /* cpu_1x or IOU_SWITCH_CLK 120 - 160 MHz */
33 #define XLNX_GEM_MDC_DIVIDER_96 5 /* cpu_1x or IOU_SWITCH_CLK 160 - 240 MHz */
34 #define XLNX_GEM_MDC_DIVIDER_128 6 /* cpu_1x or IOU_SWITCH_CLK 240 - 320 MHz */
35 #define XLNX_GEM_MDC_DIVIDER_224 7 /* cpu_1x or IOU_SWITCH_CLK 320 - 540 MHz */
51 #define XLNX_GEM_AMBA_AHB_BURST_INCR16 16
/Zephyr-latest/soc/microchip/mec/
DKconfig37 bool "SPI flash clock rate of 12 MHz"
40 bool "SPI flash clock rate of 16 MHz"
43 bool "SPI flash clock rate of 24 MHz"
46 bool "SPI flash clock rate of 48 MHz"
65 bool "SPI flash operates full-duplex with frequency (< 25 MHz)"
122 bool "SPI flash size 16M Bytes"
124 The SPI flash size is 16M Bytes.
268 and main 96 MHz clock (MCK):
270 Allowed divider values: 1, 3, 4, 16, and 48.
/Zephyr-latest/boards/st/nucleo_l412rb_p/doc/
Dindex.rst28 - 24 MHz HSE
50 - 16 nA Shutdown mode (4 wakeup pins)
54 - 79 |micro| A/MHz run mode (LDO Mode)
55 - 28 |micro| A/MHz run mode (@3.3 V SMPS Mode)
61 …e| ) allowing 0-wait-state execution from Flash memory, frequency up to 80 MHz, MPU, 100DMIPS and …
64 - 1.25 DMIPS/MHz (Drystone 2.1)
65 - 273.55 CoreMark |reg| (3.42 CoreMark/MHz @ 80 MHz)
74 - 4 to 48 MHz crystal oscillator
76 - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%)
78 …- Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by LSE (better than |plusminus| 0…
[all …]

12345678910>>...19