Lines Matching +full:16 +full:mhz

73 		/* When using HSI without PLL, the "16MHz" output is not actually 16MHz, since
75 		 * The CPU and MR_BLE must be running at 32MHz for MR_BLE to work with HSI.
78 			"System clock frequency must be at least 32MHz to use LSI");
80 		/* In PLL or Direct HSE mode, the clock is stable, so 16MHz can be used. */
82 			"System clock frequency must be at least 16MHz to use LSI");
137 	 * LSI calibration counts the amount of 16MHz clock half-periods that  in measure_lsi_frequency()
140 	 * @p fast_clock_cycles_elapsed is the number of 16MHz clock half-periods  in measure_lsi_frequency()
148 	 * tCALIB = @p fast_clock_cycles_elapsed / (2 * 16MHz)  in measure_lsi_frequency()
154 	 *	   ( @p fast_clock_cycles_elapsed / (2 * 16MHz) )  in measure_lsi_frequency()
164 	 *	   ( @p fast_clock_cycles_elapsed / (2 * 16MHz) )  in measure_lsi_frequency()
166 	 *         (2 * 16MHz) * @p STM32_WB0_LSI_MEASURE_WINDOW_SIZE  in measure_lsi_frequency()
418 	 * If Direct HSE is enabled, the high-speed tree is clocked by HSE @ 32MHz.  in stm32_clock_control_get_subsys_rate()
419 	 * Otherwise, the high-speed tree is clocked by the RC64MPLL clock @ 64MHz.  in stm32_clock_control_get_subsys_rate()
423 	 * setting CLKSYSDIV = 1 results in 32MHz CLK_SYS, regardless of SYSCLK being 32 or 64MHZ.  in stm32_clock_control_get_subsys_rate()
436 	 * NOTE: the prescaler value must be interpreted as if source clock is 64MHz, regardless  in stm32_clock_control_get_subsys_rate()
593  * whether SYSCLK runs at 32MHz (Direct HSE) or 64MHz (RC64MPLL).
617 	case 16:  in kconfig_to_ll_prescaler()
618 		return LL_PRESCALER(16);  in kconfig_to_ll_prescaler()
623 	 * off RC64MPLL because CLK_SYS must be at least 1MHz  in kconfig_to_ll_prescaler()
713 	 *  - 1 wait state when CLK_SYS > 32MHz (i.e., 64MHz configuration)  in stm32_clock_control_init()
714 	 *  - 0 wait states otherwise (CLK_SYS <= 32MHz)  in stm32_clock_control_init()