Lines Matching +full:16 +full:mhz
11 #define SYSCLK_DEFAULT_IOSC_HZ MHZ(16)
30 /* the following configuration is based on Fin = 16 Mhz */
32 {100, PLL_CONF_VAL(1, 25, 2)}, /* 100 Mhz */
33 {50, PLL_CONF_VAL(1, 25, 3)}, /* 50 Mhz */
34 {150, PLL_CONF_VAL(4, 75, 1)}, /* 150 Mhz */
35 {75, PLL_CONF_VAL(4, 75, 2)}, /* 75 Mhz */
36 {25, PLL_CONF_VAL(2, 25, 3)}, /* 25 Mhz */
37 {72, PLL_CONF_VAL(8, 144, 2)}, /* 72 Mhz */
38 {144, PLL_CONF_VAL(8, 144, 1)}, /* 144 Mhz */
51 * 1 Mhz <= Fref <= 50 Mhz
52 * 200 Mhz <= Fvco <= 400 Mhz
94 /* config eflash clk, must be < 100 Mhz */ in arc_iot_pll_fout_config()
167 (sysconf_reg_ptr->SPI_MST_CLKDIV & 0xff00ffff) | (div << 16); in arc_iot_spi_master_clk_divisor()
181 (sysconf_reg_ptr->GPIO8B_DBCLK_DIV & 0xff00ffff) | (div << 16); in arc_iot_gpio8b_dbclk_div()
198 (sysconf_reg_ptr->GPIO4B_DBCLK_DIV & 0xff00ffff) | (div << 16); in arc_iot_gpio4b_dbclk_div()
241 (sysconf_reg_ptr->DVFS_CLKDIV & 0xff00ffff) | (div << 16); in arc_iot_dvfs_clk_divisor()