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/Zephyr-latest/dts/bindings/pinctrl/
Dnxp,s32ze-pinctrl.yaml102 0: FMAX_3318 = 208 MHz (at 1.8 V), 166 MHz (at 3.3 V)
103 4: FMAX_3318 = 166 MHz (at 1.8 V), 150 MHz (at 3.3 V)
104 5: FMAX_3318 = 150 MHz (at 1.8 V), 133 MHz (at 3.3 V)
105 6: FMAX_3318 = 133 MHz (at 1.8 V), 100 MHz (at 3.3 V)
106 7: FMAX_3318 = 100 MHz (at 1.8 V), 83 MHz (at 3.3 V)
108 0: FMAX_18 = 208 MHz
109 4: FMAX_18 = 150 MHz
110 5: FMAX_18 = 133 MHz
111 6: FMAX_18 = 100 MHz
112 7: FMAX_18 = 50 MHz
[all …]
Dnxp,mcux-rt-pinctrl.yaml17 nxp,speed = "100-mhz";
22 slow slew rate, and 100 MHZ speed.
142 - "50-mhz"
143 - "100-mhz"
144 - "150-mhz"
145 - "200-mhz"
148 00 SPEED_0_low_50MHz_ — low(50MHz)
149 01 SPEED_1_medium_100MHz_ — medium(100MHz)
150 10 SPEED_2_medium_150MHz_ — medium(150MHz)
151 11 SPEED_3_max_200MHz_ — max(200MHz)
Dnxp,imx8m-pinctrl.yaml105 00 SLOW — Slow Frequency Slew Rate (50Mhz)
106 01 MEDIUM — Medium Frequency Slew Rate (100Mhz)
107 10 FAST — Fast Frequency Slew Rate (150Mhz)
108 11 MAX — Max Frequency Slew Rate (200Mhz)
/Zephyr-latest/drivers/clock_control/
Dclock_stm32g4.c60 /* set power boost mode for sys clock greater than 150MHz */ in config_pll_sysclock()
61 if (sys_clock_hw_cycles_per_sec() >= MHZ(150)) { in config_pll_sysclock()
/Zephyr-latest/soc/xlnx/zynq7000/xc7zxxxs/
DKconfig.soc20 1 ARM Cortex-A9 core up to 766 MHz, Artix-7 programmable logic,
27 1 ARM Cortex-A9 core up to 766 MHz, Artix-7 programmable logic,
28 55k logic cells, 2.5Mb block RAM, 120 DSP slices, up to 150 I/O pins,
35 1 ARM Cortex-A9 core up to 766 MHz, Artix-7 programmable logic,
/Zephyr-latest/tests/drivers/spi/spi_loopback/
Doverlay-mcux-flexio-spi.overlay17 nxp,speed = "150-mhz";
29 nxp,speed = "150-mhz";
/Zephyr-latest/boards/udoo/udoo_neo_full/
Dudoo_neo_full-pinctrl.dtsi17 nxp,speed = "150-mhz";
/Zephyr-latest/dts/bindings/clock/
Despressif,esp32-rtc.yaml21 - 1: ESP32_RTC_FAST_CLK_SRC_RC_FAST - 8 MHz
31 - 0: ESP32_RTC_SLOW_CLK_SRC_RC_SLOW - 136 KHz (C3/S3) - 90 kHz (S2) - 150 kHz (ESP32)
33 - 2: ESP32_RTC_SLOW_CLK_SRC_RC_FAST_D256 - 17,5 MHz
/Zephyr-latest/soc/nxp/mcx/mcxn/
Dflash_clock_setup.c10 /* PLL0 is set to 150 MHz */ in flexspi_clock_set_freq()
/Zephyr-latest/soc/nxp/lpc/lpc55xxx/
DKconfig97 core clock value at it's highest frequency which clocks at 150MHz.
98 Note that flash programming operations are limited to 100MHz, and
/Zephyr-latest/soc/xlnx/zynq7000/xc7zxxx/
DKconfig.soc20 2 ARM Cortex-A9 cores up to 866 MHz, Artix-7 programmable logic,
27 2 ARM Cortex-A9 cores up to 866 MHz, Artix-7 programmable logic,
28 74k logic cells, 3.3Mb block RAM, 160 DSP slices, up to 150 I/O pins,
35 2 ARM Cortex-A9 cores up to 866 MHz, Artix-7 programmable logic,
/Zephyr-latest/soc/snps/arc_iot/
Dsysconf.c11 #define SYSCLK_DEFAULT_IOSC_HZ MHZ(16)
30 /* the following configuration is based on Fin = 16 Mhz */
32 {100, PLL_CONF_VAL(1, 25, 2)}, /* 100 Mhz */
33 {50, PLL_CONF_VAL(1, 25, 3)}, /* 50 Mhz */
34 {150, PLL_CONF_VAL(4, 75, 1)}, /* 150 Mhz */
35 {75, PLL_CONF_VAL(4, 75, 2)}, /* 75 Mhz */
36 {25, PLL_CONF_VAL(2, 25, 3)}, /* 25 Mhz */
37 {72, PLL_CONF_VAL(8, 144, 2)}, /* 72 Mhz */
38 {144, PLL_CONF_VAL(8, 144, 1)}, /* 144 Mhz */
51 * 1 Mhz <= Fref <= 50 Mhz
[all …]
/Zephyr-latest/soc/atmel/sam/common/
DKconfig31 The crystal used here can be from 3 to 20 MHz.
33 Says n here will use the internal fast RC oscillator running at 12 MHz.
73 and master clock (MCK) where the maximum value is 150MHz:
/Zephyr-latest/soc/atmel/sam/same70/
Dsoc.c36 /* Switch the main clock to the internal OSC with 12MHz */ in clock_init()
68 * rather than maximum supported 150 MHz at standard VDDIO=2.7V in clock_init()
80 * With main crystal running at 12 MHz, in clock_init()
81 * PLL = 12 * (24 + 1) / 1 = 300 MHz in clock_init()
84 * Processor Clock (HCLK)=300 MHz. in clock_init()
/Zephyr-latest/soc/atmel/sam/samv71/
Dsoc.c34 /* Switch the main clock to the internal OSC with 12MHz */ in clock_init()
66 * rather than maximum supported 150 MHz at standard VDDIO=2.7V in clock_init()
78 * With main crystal running at 12 MHz, in clock_init()
79 * PLL = 12 * (24 + 1) / 1 = 300 MHz in clock_init()
82 * Processor Clock (HCLK)=300 MHz. in clock_init()
/Zephyr-latest/boards/nxp/frdm_mcxn947/
Dboard.c27 /* Core clock frequency: 150MHz */
102 /* Enable FRO HF(48MHz) output */ in frdm_mcxn947_init()
135 /* Set up PLL1 for 80 MHz FlexCAN clock */ in frdm_mcxn947_init()
272 /* Drive CLKOUT from main clock, divided by 25 to yield 6MHz clock in frdm_mcxn947_init()
312 /* xtal = 20 ~ 30MHz */ in frdm_mcxn947_init()
342 * 0 <- 12MHz FRO in frdm_mcxn947_init()
354 /* Value here should not exceed 25MHZ when using lptmr */ in frdm_mcxn947_init()
355 CLOCK_SetupExtClocking(MHZ(24)); in frdm_mcxn947_init()
367 /* Enable 1MHz clock. */ in frdm_mcxn947_init()
374 /* Attach PLL0 clock to I3C, 150MHz / 6 = 25MHz. */ in frdm_mcxn947_init()
/Zephyr-latest/boards/st/nucleo_wl55jc/doc/
Dnucleo_wl55jc.rst12 (Arm® Cortex®-M4/M0+ at 48 MHz) in UFBGA73 package featuring:
15 - RF transceiver (150 MHz to 960 MHz frequency range) supporting LoRa®,
22 - 32 MHz HSE on-board oscillator
55 - Frequency range: 150 MHz to 960 MHz
72 execution from Flash memory, frequency up to 48 MHz, MPU
74 - 1.25 DMIPS/MHz (Dhrystone 2.1)
78 - Frequency up to 48 MHz, MPU
79 - 0.95 DMIPS/MHz (Dhrystone 2.1)
106 - 32 MHz crystal oscillator
109 - High-speed internal 16 MHz factory trimmed RC (± 1 %)
[all …]
/Zephyr-latest/boards/st/sensortile_box/doc/
Dindex.rst25 execution from Flash memory, frequency up to 120 MHz, MPU, 150
26 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
29 - 16 MHz crystal oscillator
96 driven by the PLL clock at 80MHz, driven by the 16MHz external oscillator.
97 The system clock can be boosted to 120MHz.
98 The internal AHB/APB1/APB2 AMBA buses are all clocked at 80MHz.
/Zephyr-latest/drivers/sensor/ti/tmp112/
Dtmp112.c80 /* the sensor supports two ranges -55 to 128 and -55 to 150 */ in tmp112_attr_set()
84 } else if (val->val1 == 150) { in tmp112_attr_set()
98 /* conversion rate in mHz */ in tmp112_attr_set()
/Zephyr-latest/boards/nxp/frdm_mcxn236/
Dboard.c23 /* Core clock frequency: 150MHz */
77 /* Enable FRO HF(48MHz) output */ in frdm_mcxn236_init()
103 /* Set up PLL1 for 80 MHz FlexCAN clock */ in frdm_mcxn236_init()
244 /* xtal = 20 ~ 30MHz */ in frdm_mcxn236_init()
277 * 0 <- 12MHz FRO in frdm_mcxn236_init()
289 /* Value here should not exceed 25MHZ when using lptmr */ in frdm_mcxn236_init()
290 CLOCK_SetupExtClocking(MHZ(24)); in frdm_mcxn236_init()
/Zephyr-latest/boards/raspberrypi/rpi_pico2/doc/
Dindex.rst16 - Dual Cortex-M33 or Hazard3 processors at up to 150MHz
/Zephyr-latest/drivers/wifi/nrf_wifi/
DKconfig.nrfwifi236 int "PCB loss for 5 GHz band (5150 MHz - 5350 MHz, Channel-32 - Channel-68)"
245 int "PCB loss for 5 GHz band (5470 MHz - 5730 MHz, Channel-96 - Channel-144)"
254 int "PCB loss for 5 GHz band (5730 MHz - 5895 MHz, Channel-149 - Channel-177)"
268 int "Antenna gain for 5 GHz band (5150 MHz - 5350 MHz)"
273 int "Antenna gain for 5 GHz band (5470 MHz - 5730 MHz)"
278 int "Antenna gain for 5 GHz band (5730 MHz - 5895 MHz)"
808 # By default, the limit is 250 in scan-only mode and 150 in regular mode.
813 def_int 150
/Zephyr-latest/drivers/sensor/maxim/max31875/
Dmax31875.c135 /* the sensor supports two ranges -50 to 128 and -50 to 150 */ in max31875_attr_set()
139 } else if (val->val1 == 150) { in max31875_attr_set()
152 /* conversion rate in mHz */ in max31875_attr_set()
/Zephyr-latest/soc/infineon/cat1a/psoc6_legacy/
Dsoc.c118 /* Set worst case memory wait states (! ultra low power, 150 MHz), will in init_cycfg_platform()
121 Cy_SysLib_SetWaitStates(false, 150); in init_cycfg_platform()
/Zephyr-latest/boards/st/nucleo_l4r5zi/doc/
Dindex.rst34 and 100 uA/MHz run mode)
37 execution from Flash memory, frequency up to 120 MHz, MPU, 150
38 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
41 - 4 to 48 MHz crystal oscillator
43 - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%)
45 - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by
47 - Internal 48 MHz with clock recovery
100 - 8- to 14-bit camera interface up to 32 MHz (black and white) or 10 MHz (color)
199 driven by the PLL clock at 80MHz, driven by a 16MHz high speed
200 internal oscillator. The clock can be boosted to 120MHz if boost mode

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