| /Zephyr-latest/dts/bindings/clock/ |
| D | st,stm32u5-msi-clock.yaml | 22 - 0 # range 0 around 48 MHz
23 - 1 # range 1 around 24 MHz
24 - 2 # range 2 around 16 MHz
25 - 3 # range 3 around 12 MHz
26 - 4 # range 4 around 4 MHz (reset value)
27 - 5 # range 5 around 2 MHz
28 - 6 # range 6 around 1.33 MHz
29 - 7 # range 7 around 1 MHz
30 - 8 # range 8 around 3.072 MHz
31 - 9 # range 9 around 1.536 MHz
[all …]
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| D | st,stm32c0-hsi-clock.yaml | 6 On STM32C0, HSI is a 48MHz fixed clock.
12 - 1 ==> HSISYS = 48MHZ
13 - 2 ==> HSISYS = 24MHZ
14 - 4 ==> HSISYS = 12MHZ
15 - 8 ==> HSISYS = 6MHZ
16 - 16 ==> HSISYS = 3MHZ
17 - 32 ==> HSISYS = 1.5MHz
18 - 64 ==> HSISYS = 0.75MHZ
19 - 128 ==> HSISYS = 0.375MHz
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| D | st,stm32l0-pll-clock.yaml | 8 input frequency from 2 to 24 MHz.
16 The PLL output frequency must not exceed 32 MHz.
45 - 96 MHz when the product is in Range 1
46 - 48 MHz when the product is in Range 2
47 - 24 MHz when the product is in Range 3
49 programmed to output a 96 MHz frequency (USBCLK = PLLVCO/2).
55 - 12
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| D | nuvoton,npcm-pcc.yaml | 14 clock-frequency = <DT_FREQ_M(96)>; /* OFMCLK runs at 96MHz */
15 core-prescaler = <1>; /* CORE_CLK runs at 96MHz */
16 apb1-prescaler = <8>; /* APB1_CLK runs at 12MHz */
17 apb2-prescaler = <1>; /* APB2_CLK runs at 96MHz */
18 apb3-prescaler = <1>; /* APB3_CLK runs at 96MHz */
19 apb6-prescaler = <1>; /* APB6_CLK runs at 96MHz */
20 fiu-prescaler = <1>; /* FIU_CLK runs at 96MHz */
21 i3c-prescaler = <1>; /* I3C_CLK runs at 96MHz */
38 100000000, 100 MHz
39 96000000, 96 MHz
[all …]
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| /Zephyr-latest/soc/nxp/lpc/lpc51u68/ |
| D | soc.c | 28 /* Attach 12 MHz clock to flexcomm0 */ in soc_early_init_hook()
32 /* attach 12 MHz clock for flexcomm4 */ in soc_early_init_hook()
37 /* attach 12MHz clock to flexcomm5 */ in soc_early_init_hook()
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| /Zephyr-latest/samples/sensor/fdc2x1x/ |
| D | README.rst | 12 to read the 12-Bit and 28-Bit, as well as the 2-Channel and 4-Channel versions
63 ch0: 5.318888 MHz ch1: 5.150293 MHz
66 ch0: 5.318819 MHz ch1: 5.150307 MHz
69 ch0: 5.318822 MHz ch1: 5.150200 MHz
72 ch0: 5.318752 MHz ch1: 5.150265 MHz
78 Sample Output: 4-Channel, 12-Bit (FDC2114)
83 ch0: 4.966171 MHz ch1: 4.946465 MHz ch2: 4.985879 MHz ch3: 4.907051 MHz
86 ch0: 4.966171 MHz ch1: 4.946465 MHz ch2: 4.985879 MHz ch3: 4.907051 MHz
89 ch0: 4.966171 MHz ch1: 4.946465 MHz ch2: 4.985879 MHz ch3: 4.907051 MHz
92 ch0: 4.966171 MHz ch1: 4.946465 MHz ch2: 4.985879 MHz ch3: 4.907051 MHz
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| /Zephyr-latest/soc/atmel/sam/sam3x/ |
| D | soc.c | 30 /* Switch the main clock to the internal OSC with 12MHz */ in clock_init()
62 * rather than maximum supported 84 MHz at standard VDDCORE=1.8V in clock_init()
75 * With main crystal running at 12 MHz, in clock_init()
76 * PLL = 12 * (6 + 1) / 1 = 84 MHz in clock_init()
79 * Processor Clock (HCLK) = 84 MHz. in clock_init()
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| /Zephyr-latest/dts/arm/nuvoton/npcm/ |
| D | npcm4.dtsi | 27 clock-frequency = <DT_FREQ_M(96)>; /* OFMCLK runs at 96MHz */
28 core-prescaler = <1>; /* CORE_CLK runs at 96MHz */
29 apb1-prescaler = <8>; /* APB1_CLK runs at 12MHz */
30 apb2-prescaler = <1>; /* APB2_CLK runs at 96MHz */
31 apb3-prescaler = <1>; /* APB3_CLK runs at 96MHz */
32 ahb6-prescaler = <1>; /* APB6_CLK runs at 96MHz */
33 fiu-prescaler = <1>; /* FIU_CLK runs at 96MHz */
34 i3c-prescaler = <1>; /* I3C_CLK runs at 96MHz */
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| /Zephyr-latest/drivers/modem/ |
| D | Kconfig.hl7800 | 79 bool "Band 1 (2000MHz)"
82 Enable Band 1 (2000MHz)
85 bool "Band 2 (1900MHz)"
88 Enable Band 2 (1900MHz)
91 bool "Band 3 (1800MHz)"
94 Enable Band 3 (1800MHz)
97 bool "Band 4 (1700MHz)"
100 Enable Band 4 (1700MHz)
103 bool "Band 5 (850MHz)"
106 Enable Band 5 (850MHz)
[all …]
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| /Zephyr-latest/soc/ene/kb1200/ |
| D | soc.c | 31 /* AHB/APB clock select 96MHz/48MHz */ in clock_init()
34 /* AHB/APB clock select 48MHz/24MHz */ in clock_init()
37 /* AHB/APB clock select 24MHz/12MHz */ in clock_init()
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| /Zephyr-latest/boards/st/stm32g081b_eval/ |
| D | stm32g081b_eval.dts | 146 zephyr,resolution = <12>;
155 zephyr,resolution = <12>;
164 * UCPD is fed directly from HSI which is @ 16MHz. The ucpd_clk goes to
167 * designed to work in freq ranges of 6 <--> 18 MHz, however recommended
168 * range is 9 <--> 18 MHz.
170 * +-------+ @ 16 MHz +-------+ @ ~600 kHz +-----------+
177 * 1. hbit_clk ~= 600 kHz: 16 MHz / 600 kHz = 26.67
178 * 2. tTransitionWindow - 12 to 20 uSec
195 * UCPD is fed directly from HSI which is @ 16MHz. The ucpd_clk goes to
198 * designed to work in freq ranges of 6 <--> 18 MHz, however recommended
[all …]
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| /Zephyr-latest/soc/atmel/sam/same70/ |
| D | soc.c | 36 /* Switch the main clock to the internal OSC with 12MHz */ in clock_init()
68 * rather than maximum supported 150 MHz at standard VDDIO=2.7V in clock_init()
80 * With main crystal running at 12 MHz, in clock_init()
81 * PLL = 12 * (24 + 1) / 1 = 300 MHz in clock_init()
84 * Processor Clock (HCLK)=300 MHz. in clock_init()
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| /Zephyr-latest/soc/atmel/sam/samv71/ |
| D | soc.c | 34 /* Switch the main clock to the internal OSC with 12MHz */ in clock_init()
66 * rather than maximum supported 150 MHz at standard VDDIO=2.7V in clock_init()
78 * With main crystal running at 12 MHz, in clock_init()
79 * PLL = 12 * (24 + 1) / 1 = 300 MHz in clock_init()
82 * Processor Clock (HCLK)=300 MHz. in clock_init()
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| /Zephyr-latest/soc/nxp/lpc/lpc54xxx/ |
| D | soc.c | 59 * Switch to FRO 12MHz first to ensure we can change voltage without in clock_init()
78 /* Attach 12 MHz clock to FLEXCOMM0 */ in clock_init()
82 /* attach 12 MHz clock to FLEXCOMM4 */ in clock_init()
87 /* Attach 12 MHz clock to FLEXCOMM5 */ in clock_init()
106 /* Initialize FRO/system clock to 48 MHz */ in nxp_lpc54114_init()
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| /Zephyr-latest/boards/shields/mikroe_eth_click/boards/ |
| D | lpcxpresso55s69_lpc55s69_cpu0.overlay | 14 <&gpio1 12 GPIO_ACTIVE_LOW>,
23 /* Errata B7/1 specifies min 8Mhz, 20MHz max according to RM */
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| /Zephyr-latest/boards/nxp/mimxrt1010_evk/ |
| D | mimxrt1010_evk-pinctrl.dtsi | 12 /* ADC Channels 1 and 2, exposed as pins 10 and 12 on J26 of EVK */
19 nxp,speed = "100-mhz";
29 nxp,speed = "100-mhz";
42 nxp,speed = "100-mhz";
53 nxp,speed = "100-mhz";
64 nxp,speed = "100-mhz";
70 nxp,speed = "100-mhz";
81 nxp,speed = "100-mhz";
93 nxp,speed = "100-mhz";
99 nxp,speed = "100-mhz";
[all …]
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| /Zephyr-latest/soc/atmel/sam/sam4l/ |
| D | soc.h | 73 * Internal 80 MHz RC oscillator
74 * Internal 4-8-12 MHz RCFAST oscillator
75 * Internal 1 MHz RC oscillator
91 * 80 MHz RC oscillator
92 * 4-8-12 MHz RC oscillator
93 * 1 MHz RC oscillator
146 #define SYSCLK_ADCIFE 12
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| /Zephyr-latest/tests/drivers/flash/common/boards/ |
| D | nrf52840dk_spi_nor_wp_hold.overlay | 16 <NRF_PSEL(SPIM_MISO, 0, 12)>;
24 <NRF_PSEL(SPIM_MISO, 0, 12)>;
42 spi-max-frequency = <8000000>; // chip supports 80Mhz, SPI0 supports 8MHz
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| D | nrf52840dk_spi_nor.overlay | 16 <NRF_PSEL(SPIM_MISO, 0, 12)>;
24 <NRF_PSEL(SPIM_MISO, 0, 12)>;
42 spi-max-frequency = <8000000>; // chip supports 80Mhz, SPI0 supports 8MHz
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| /Zephyr-latest/boards/st/stm32g071b_disco/ |
| D | stm32g071b_disco.dts | 39 gpios = <&gpioc 12 GPIO_ACTIVE_HIGH>;
86 gpios = <&gpiob 12 GPIO_ACTIVE_LOW>;
160 * UCPD is fed directly from HSI which is @ 16MHz. The ucpd_clk goes to
163 * designed to work in freq ranges of 6 <--> 18 MHz, however recommended
164 * range is 9 <--> 18 MHz.
166 * +-------+ @ 16 MHz +-------+ @ ~600 kHz +-----------+
173 * 1. hbit_clk ~= 600 kHz: 16 MHz / 600 kHz = 26.67
174 * 2. tTransitionWindow - 12 to 20 uSec
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| /Zephyr-latest/soc/nxp/lpc/lpc55xxx/ |
| D | soc.c | 41 /*Should be in the range of 12MHz to 32MHz */
97 /* Set up FRO to the 12 MHz, to ensure we can change the clock freq */ in clock_init()
99 /* Switch to FRO 12MHz first to ensure we can change the clock */ in clock_init()
106 /* Setting the Core Clock to either 96MHz or in the case of using PLL, 144MHz */ in clock_init()
134 /* Enable FRO HF(SystemCoreClock) output (Default expected value 96MHz) */ in clock_init()
196 /* attach 12 MHz clock to FLEXCOMM4 */ in clock_init()
217 /* Attach 12 MHz clock to HSLSPI */ in clock_init()
222 /* Enable 1 MHz FRO clock for WWDT */ in clock_init()
381 /* Initialize FRO/system clock to 96 MHz */ in nxp_lpc55xxx_init()
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| /Zephyr-latest/soc/microchip/mec/ |
| D | Kconfig | 37 bool "SPI flash clock rate of 12 MHz"
40 bool "SPI flash clock rate of 16 MHz"
43 bool "SPI flash clock rate of 24 MHz"
46 bool "SPI flash clock rate of 48 MHz"
52 default 12 if MCHP_MEC_HEADER_SPI_FREQ_MHZ_12
65 bool "SPI flash operates full-duplex with frequency (< 25 MHz)"
268 and main 96 MHz clock (MCK):
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| /Zephyr-latest/boards/st/nucleo_u031r8/doc/ |
| D | index.rst | 23 - USB VBUS or external source(3.3V, 5V, 7 - 12V)
36 They operate at a frequency of up to 56 MHz.
50 - 52 µA/MHz Run mode
55 - 32-bit Arm |reg| Cortex |reg|-M0+ CPU, frequency up to 56 MHz
63 - 1.13 DMIPS/MHz (Drystone 2.1)
64 - 134 CoreMark |reg| (2.4 CoreMark/MHz at 56 MHz)
72 - 12-Kbyte SRAM with hardware parity check
80 - 4 to 48 MHz crystal oscillator
82 - Internal 16 MHz factory-trimmed RC (±1%)
84 - Internal multispeed 100 kHz to 48 MHz oscillator,
[all …]
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| /Zephyr-latest/tests/drivers/pinctrl/gd32/boards/ |
| D | gd32f403z_eval.overlay | 52 slew-rate = "max-speed-2mhz";
56 slew-rate = "max-speed-10mhz";
59 pinmux = <GD32_PINMUX_AFIO('A', 12, ALTERNATE, NORMP)>;
60 slew-rate = "max-speed-50mhz";
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| /Zephyr-latest/boards/st/nucleo_l412rb_p/doc/ |
| D | index.rst | 22 - USB VBUS or external source(3.3V, 5V, 7 - 12V)
28 - 24 MHz HSE
54 - 79 |micro| A/MHz run mode (LDO Mode)
55 - 28 |micro| A/MHz run mode (@3.3 V SMPS Mode)
61 …e| ) allowing 0-wait-state execution from Flash memory, frequency up to 80 MHz, MPU, 100DMIPS and …
64 - 1.25 DMIPS/MHz (Drystone 2.1)
65 - 273.55 CoreMark |reg| (3.42 CoreMark/MHz @ 80 MHz)
74 - 4 to 48 MHz crystal oscillator
76 - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%)
78 …- Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by LSE (better than |plusminus| 0…
[all …]
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