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/Zephyr-latest/dts/bindings/timer/
Dnuclei,systimer.yaml30 For example, the CPU clock frequency is 108MHz, and the system timer
31 uses 27MHz, which is the CPU clock divided by 4.
45 that CPU clock frequency divided by (2^2=)4, or 27MHz.
/Zephyr-latest/soc/gd/gd32/gd32vf103/
DKconfig.defconfig.gd32vf10311 # The CPU frequency is set to the maximum value of 108MHz by default.
/Zephyr-latest/boards/gd/gd32f350r_eval/doc/
Dindex.rst10 to 108-MHz with flash accesses zero wait states, 128kB of Flash, 16kB of
/Zephyr-latest/boards/gd/gd32vf103c_starter/doc/
Dindex.rst10 to 108 MHz with flash accesses zero wait states, 128 KiB of Flash, 32 KiB of
/Zephyr-latest/boards/gd/gd32vf103v_eval/doc/
Dindex.rst10 to 108 MHz with flash accesses zero wait states, 128 KiB of Flash, 32 KiB of
/Zephyr-latest/boards/st/nucleo_l496zg/doc/
Dindex.rst35 - Ultra-low-power with FlexPowerControl (down to 108 nA Standby mode and 91 uA/MHz run mode)
36 … |reg| 32-bit Cortex |reg|-M4 CPU with FPU, frequency up to 80 MHz, 100DMIPS/1.25DMIPS/MHz (Dhryst…
39 - 4 to 48 MHz crystal oscillator
41 - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%)
43 - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by
167 as well as main PLL clock. By default System clock is driven by PLL clock at 80MHz,
168 driven by 16MHz high speed internal oscillator.
/Zephyr-latest/boards/st/stm32l496g_disco/doc/
Dindex.rst48 - Ultra-low-power with FlexPowerControl (down to 108 nA Standby mode and 91
49 |micro| A/MHz run mode)
50 - Core: ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU, frequency up to 80 MHz,
51 100DMIPS/1.25DMIPS/MHz (Dhrystone 2.1)
54 - 4 to 48 MHz crystal oscillator
56 - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%)
58 - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by
60 - Internal 48 MHz with clock recovery
181 as well as the main PLL clock. By default the System clock is driven by the PLL clock at 80MHz,
182 driven by 16MHz high speed internal oscillator.
/Zephyr-latest/boards/st/nucleo_l4a6zg/doc/
Dindex.rst35 - Ultra-low-power with FlexPowerControl (down to 108 nA Standby mode and 91 uA/MHz run mode)
36 … |reg| 32-bit Cortex |reg|-M4 CPU with FPU, frequency up to 80 MHz, 100DMIPS/1.25DMIPS/MHz (Dhryst…
39 - 4 to 48 MHz crystal oscillator
41 - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%)
43 - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by
162 as well as main PLL clock. By default, system clock is driven by PLL at 80MHz, which is
163 driven by 16MHz high speed internal oscillator (HSI). High speed external oscillator
/Zephyr-latest/boards/st/nucleo_wl55jc/doc/
Dnucleo_wl55jc.rst12 (Arm® Cortex®-M4/M0+ at 48 MHz) in UFBGA73 package featuring:
15 - RF transceiver (150 MHz to 960 MHz frequency range) supporting LoRa®,
22 - 32 MHz HSE on-board oscillator
55 - Frequency range: 150 MHz to 960 MHz
63 and the Japanese ARIB STD-T30, T-67, T-108
72 execution from Flash memory, frequency up to 48 MHz, MPU
74 - 1.25 DMIPS/MHz (Dhrystone 2.1)
78 - Frequency up to 48 MHz, MPU
79 - 0.95 DMIPS/MHz (Dhrystone 2.1)
106 - 32 MHz crystal oscillator
[all …]
/Zephyr-latest/boards/st/nucleo_l552ze_q/doc/
Dnucleol552ze_q.rst37 They operate at a frequency of up to 110 MHz.
39 - Ultra-low-power with FlexPowerControl (down to 108 nA Standby mode and 62 uA/MHz run mode)
43 - 1.5 DMPIS/MHz (Drystone 2.1)
44 - 442 CoreMark |reg| (4.02 CoreMark |reg| /MHZ)
61 - 4 to 48 MHz crystal oscillator
63 - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%)
65 - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by
266 110MHz, driven by 4MHz medium speed internal oscillator.
/Zephyr-latest/boards/st/stm32l562e_dk/doc/
Dindex.rst50 They operate at a frequency of up to 110 MHz.
52 - Ultra-low-power with FlexPowerControl (down to 108 nA Standby mode and 62 uA/MHz run mode)
56 - 1.5 DMPIS/MHz (Drystone 2.1)
57 - 442 CoreMark |reg| (4.02 CoreMark |reg| /MHZ)
77 - 4 to 48 MHz crystal oscillator
79 - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%)
81 - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by
268 110MHz, driven by 4MHz medium speed internal oscillator.
/Zephyr-latest/boards/st/stm32f746g_disco/
Dstm32f746g_disco.dts237 * Note: SDRAM_CLK_MHZ = HCLK_MHZ / 2 (108 MHz)
/Zephyr-latest/boards/st/stm32f7508_dk/
Dstm32f7508_dk.dts233 * Note: SDRAM_CLK_MHZ = HCLK_MHZ / 2 (108 MHz)
/Zephyr-latest/drivers/audio/
Dtlv320dac310x.c346 /* calculate MCLK divider to get ~1MHz */ in codec_configure_clocks()
442 107, 108, 110, 113, 116, 120, 125, 128, 132, 138, 144 in codec_set_output_volume()
/Zephyr-latest/dts/arm/nxp/
Dnxp_rt10xx.dtsi123 interrupts = <108 0>;
977 * = (24MHz * (32 + 77 / 100)) / 1 = 786.48 MHz
985 /* The maximum input frequency into the SAI mclk input is 300MHz
Dnxp_rt11xx.dtsi207 * of 24MHz. The PLL features a loop divider and
209 * as Fout = 24MHz * (clock-mult / clock-div)
243 interrupts = <108 0>, <109 0>;