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Searched +full:0 +full:xffffffe0 (Results 1 – 8 of 8) sorted by relevance

/Zephyr-latest/dts/riscv/
Dneorv32.dtsi19 #size-cells = <0>;
21 cpu0: cpu@0 {
24 reg = <0>;
35 interrupt-map-mask = <0x0 0xffffffff>;
37 0 0 &intc 0 16
38 0 1 &intc 0 17
39 0 2 &intc 0 18
40 0 3 &intc 0 19
41 0 4 &intc 0 20
42 0 5 &intc 0 21
[all …]
/Zephyr-latest/dts/bindings/gpio/
Dambiq,gpio.yaml21 gpio-map-mask = <0xffffffe0 0xffffffc0>;
22 gpio-map-pass-thru = <0x1f 0x3f>;
24 0x00 0x0 &gpio0_31 0x0 0x0
25 0x20 0x0 &gpio32_63 0x0 0x0
26 0x40 0x0 &gpio64_95 0x0 0x0
27 0x60 0x0 &gpio96_127 0x0 0x0
29 reg = <0x40010000>;
32 #size-cells = <0>;
35 gpio0_31: gpio0_31@0 {
39 reg = <0>;
[all …]
/Zephyr-latest/dts/arm/ambiq/
Dambiq_apollo4p.dtsi15 #clock-cells = <0>;
21 #size-cells = <0>;
23 cpu0: cpu@0 {
25 reg = <0>;
32 reg = <0xe0000000 0x1000>;
68 reg = <0x10000000 0x10000>;
75 reg = <0x10010000 0x2B0000>;
83 reg = <0x00018000 0x1e8000>;
91 reg = <0x00018000 0x1e8000>;
97 reg = <0x40021000 0x400>;
[all …]
Dambiq_apollo4p_blue.dtsi14 #clock-cells = <0>;
30 #size-cells = <0>;
32 cpu0: cpu@0 {
34 reg = <0>;
40 reg = <0xe0000000 0x1000>;
49 reg = <0x10000000 0x10000>;
56 reg = <0x10010000 0x2B0000>;
64 reg = <0x00018000 0x1e8000>;
72 reg = <0x00018000 0x1e8000>;
78 reg = <0x40021000 0x400>;
[all …]
Dambiq_apollo3_blue.dtsi15 #clock-cells = <0>;
21 #size-cells = <0>;
23 cpu0: cpu@0 {
25 reg = <0>;
32 reg = <0xe0000000 0x1000>;
66 reg = <0x10000000 0x10000>;
73 reg = <0x10010000 0x50000>;
79 flash: flash-controller@0 {
81 reg = <0x00000000 0x100000>;
87 flash0: flash@0 {
[all …]
Dambiq_apollo3p_blue.dtsi15 #clock-cells = <0>;
21 #size-cells = <0>;
23 cpu0: cpu@0 {
25 reg = <0>;
32 reg = <0xe0000000 0x1000>;
66 reg = <0x10000000 0x10000>;
73 reg = <0x10010000 0xB0000>;
78 reg = <0x52000000 0x2000000>;
84 reg = <0x54000000 0x2000000>;
90 reg = <0x56000000 0x2000000>;
[all …]
/Zephyr-latest/dts/xtensa/espressif/esp32/
Desp32_common.dtsi27 #size-cells = <0>;
29 cpu0: cpu@0 {
32 reg = <0>;
77 interrupts = <ETH_MAC_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
88 #size-cells = <0>;
99 reg = <0x40070000 DT_SIZE_K(192)>;
105 reg = <0x3ffe0000 DT_SIZE_K(128)>;
111 reg = <0x3ffae000 DT_SIZE_K(200)>;
117 reg = <0x3ffe5230 0x400>;
122 reg = <0x3ffe5630 0x4000>;
[all …]
/Zephyr-latest/dts/xtensa/espressif/esp32s3/
Desp32s3_common.dtsi30 #size-cells = <0>;
32 cpu0: cpu@0 {
35 reg = <0>;
91 reg = <0x40370000 DT_SIZE_K(32)>;
97 reg = <0x3fc88000 DT_SIZE_K(416)>;
103 reg = <0x3fcf0000 DT_SIZE_K(64)>;
109 reg = <0x3fce5000 0x400>;
114 reg = <0x3fce5400 0x4000>;
119 reg = <0x3fce9400 0x8>;
122 shared-memory-size = <0x400>;
[all …]