Lines Matching +full:0 +full:xffffffe0
21 gpio-map-mask = <0xffffffe0 0xffffffc0>;
22 gpio-map-pass-thru = <0x1f 0x3f>;
24 0x00 0x0 &gpio0_31 0x0 0x0
25 0x20 0x0 &gpio32_63 0x0 0x0
26 0x40 0x0 &gpio64_95 0x0 0x0
27 0x60 0x0 &gpio96_127 0x0 0x0
29 reg = <0x40010000>;
32 #size-cells = <0>;
35 gpio0_31: gpio0_31@0 {
39 reg = <0>;
40 interrupts = <56 0>;
48 reg = <0x80>;
49 interrupts = <57 0>;
57 reg = <0x100>;
58 interrupts = <58 0>;
66 reg = <0x180>;
67 interrupts = <59 0>;
73 provides the base register address 0x40010000. It has four "ambiq,gpio-bank"
78 the address of pin 20 of gpio32_63@80 node is (0x40010000 + 0x80 + (20 << 2))
79 = 0x400100D0 and the real GPIO pin number of this pin in soc is (20 + 32)