Home
last modified time | relevance | path

Searched +full:0 +full:x4 (Results 1 – 25 of 336) sorted by relevance

12345678910>>...14

/Zephyr-latest/dts/riscv/
Driscv32-litex-vexriscv.dtsi22 #size-cells = <0>;
23 cpu0: cpu@0 {
27 reg = <0>;
39 reg = <0xe0000000 0x4
40 0xe0000004 0x4
41 0xe0000008 0x4>;
48 #address-cells = <0>;
51 reg = <0xbc0 0x4 0xfc0 0x4>;
59 reg = <0xe0001800 0x4
60 0xe0001804 0x4
[all …]
/Zephyr-latest/samples/modules/canopennode/objdict/
DCO_OD.c30 /*1000*/ 0x0000L,
31 /*1005*/ 0x0080L,
32 /*1006*/ 0x0000L,
33 /*1007*/ 0x0000L,
35 /*1009*/ { '3', '.', '0', '0' },
36 /*100a*/ { '3', '.', '0', '0' },
37 /*1012*/ 0x0000L,
38 /*1014*/ 0x0080L,
39 /*1015*/ 0x64,
40 /*1016*/ { 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/pinctrl/silabs/
Dxg21-pinctrl.h16 #define SILABS_DBUS_ACMP0_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 4, 1, 0, 1)
18 #define SILABS_DBUS_ACMP1_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 7, 1, 0, 1)
20 #define SILABS_DBUS_CMU_CLKOUT0(port, pin) SILABS_DBUS(port, pin, 10, 1, 0, 2)
23 #define SILABS_DBUS_CMU_CLKIN0(port, pin) SILABS_DBUS(port, pin, 10, 0, 0, 1)
25 #define SILABS_DBUS_PTI_DCLK(port, pin) SILABS_DBUS(port, pin, 17, 1, 0, 1)
29 #define SILABS_DBUS_I2C0_SCL(port, pin) SILABS_DBUS(port, pin, 22, 1, 0, 1)
32 #define SILABS_DBUS_I2C1_SCL(port, pin) SILABS_DBUS(port, pin, 26, 1, 0, 1)
35 #define SILABS_DBUS_LETIMER0_OUT0(port, pin) SILABS_DBUS(port, pin, 30, 1, 0, 1)
38 #define SILABS_DBUS_MODEM_ANT0(port, pin) SILABS_DBUS(port, pin, 34, 1, 0, 1)
42 #define SILABS_DBUS_MODEM_DIN(port, pin) SILABS_DBUS(port, pin, 34, 0, 0, 4)
[all …]
Dxg24-pinctrl.h16 #define SILABS_DBUS_ACMP0_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 4, 1, 0, 1)
18 #define SILABS_DBUS_ACMP1_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 7, 1, 0, 1)
20 #define SILABS_DBUS_CMU_CLKOUT0(port, pin) SILABS_DBUS(port, pin, 10, 1, 0, 2)
23 #define SILABS_DBUS_CMU_CLKIN0(port, pin) SILABS_DBUS(port, pin, 10, 0, 0, 1)
25 #define SILABS_DBUS_EUSART0_CS(port, pin) SILABS_DBUS(port, pin, 21, 1, 0, 1)
30 #define SILABS_DBUS_EUSART0_CTS(port, pin) SILABS_DBUS(port, pin, 21, 0, 0, 2)
32 #define SILABS_DBUS_EUSART1_CS(port, pin) SILABS_DBUS(port, pin, 29, 1, 0, 1)
37 #define SILABS_DBUS_EUSART1_CTS(port, pin) SILABS_DBUS(port, pin, 29, 0, 0, 2)
39 #define SILABS_DBUS_PTI_DCLK(port, pin) SILABS_DBUS(port, pin, 37, 1, 0, 1)
43 #define SILABS_DBUS_I2C0_SCL(port, pin) SILABS_DBUS(port, pin, 42, 1, 0, 1)
[all …]
Dxg23-pinctrl.h16 #define SILABS_DBUS_ACMP0_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 16, 1, 0, 1)
18 #define SILABS_DBUS_ACMP1_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 19, 1, 0, 1)
20 #define SILABS_DBUS_CMU_CLKOUT0(port, pin) SILABS_DBUS(port, pin, 22, 1, 0, 2)
23 #define SILABS_DBUS_CMU_CLKIN0(port, pin) SILABS_DBUS(port, pin, 22, 0, 0, 1)
25 #define SILABS_DBUS_EUSART0_CS(port, pin) SILABS_DBUS(port, pin, 33, 1, 0, 1)
30 #define SILABS_DBUS_EUSART0_CTS(port, pin) SILABS_DBUS(port, pin, 33, 0, 0, 2)
32 #define SILABS_DBUS_EUSART1_CS(port, pin) SILABS_DBUS(port, pin, 41, 1, 0, 1)
37 #define SILABS_DBUS_EUSART1_CTS(port, pin) SILABS_DBUS(port, pin, 41, 0, 0, 2)
39 #define SILABS_DBUS_EUSART2_CS(port, pin) SILABS_DBUS(port, pin, 49, 1, 0, 1)
44 #define SILABS_DBUS_EUSART2_CTS(port, pin) SILABS_DBUS(port, pin, 49, 0, 0, 2)
[all …]
Dxg22-pinctrl.h16 #define SILABS_DBUS_CMU_CLKOUT0(port, pin) SILABS_DBUS(port, pin, 4, 1, 0, 2)
19 #define SILABS_DBUS_CMU_CLKIN0(port, pin) SILABS_DBUS(port, pin, 4, 0, 0, 1)
21 #define SILABS_DBUS_PTI_DCLK(port, pin) SILABS_DBUS(port, pin, 15, 1, 0, 1)
25 #define SILABS_DBUS_I2C0_SCL(port, pin) SILABS_DBUS(port, pin, 20, 1, 0, 1)
28 #define SILABS_DBUS_I2C1_SCL(port, pin) SILABS_DBUS(port, pin, 24, 1, 0, 1)
31 #define SILABS_DBUS_LETIMER0_OUT0(port, pin) SILABS_DBUS(port, pin, 28, 1, 0, 1)
34 #define SILABS_DBUS_EUART0_RTS(port, pin) SILABS_DBUS(port, pin, 32, 1, 0, 2)
36 #define SILABS_DBUS_EUART0_CTS(port, pin) SILABS_DBUS(port, pin, 32, 0, 0, 1)
37 #define SILABS_DBUS_EUART0_RX(port, pin) SILABS_DBUS(port, pin, 32, 0, 0, 3)
39 #define SILABS_DBUS_MODEM_ANT0(port, pin) SILABS_DBUS(port, pin, 38, 1, 0, 1)
[all …]
Dxg27-pinctrl.h16 #define SILABS_DBUS_ACMP0_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 4, 1, 0, 1)
18 #define SILABS_DBUS_CMU_CLKOUT0(port, pin) SILABS_DBUS(port, pin, 7, 1, 0, 2)
21 #define SILABS_DBUS_CMU_CLKIN0(port, pin) SILABS_DBUS(port, pin, 7, 0, 0, 1)
23 #define SILABS_DBUS_EUSART0_CS(port, pin) SILABS_DBUS(port, pin, 19, 1, 0, 1)
28 #define SILABS_DBUS_EUSART0_CTS(port, pin) SILABS_DBUS(port, pin, 19, 0, 0, 2)
30 #define SILABS_DBUS_PTI_DCLK(port, pin) SILABS_DBUS(port, pin, 27, 1, 0, 1)
34 #define SILABS_DBUS_I2C0_SCL(port, pin) SILABS_DBUS(port, pin, 32, 1, 0, 1)
37 #define SILABS_DBUS_I2C1_SCL(port, pin) SILABS_DBUS(port, pin, 36, 1, 0, 1)
40 #define SILABS_DBUS_LETIMER0_OUT0(port, pin) SILABS_DBUS(port, pin, 40, 1, 0, 1)
43 #define SILABS_DBUS_MODEM_ANT0(port, pin) SILABS_DBUS(port, pin, 44, 1, 0, 1)
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/pinctrl/renesas/
Dpinctrl-ra.h10 #define RA_PORT_NUM_POS 0
11 #define RA_PORT_NUM_MASK 0xf
14 #define RA_PIN_NUM_MASK 0xf
16 #define RA_PSEL_HIZ_JTAG_SWD 0x0
17 #define RA_PSEL_AGT 0x1
18 #define RA_PSEL_GPT0 0x2
19 #define RA_PSEL_GPT1 0x3
20 #define RA_PSEL_SCI_0 0x4
21 #define RA_PSEL_SCI_2 0x4
22 #define RA_PSEL_SCI_4 0x4
[all …]
/Zephyr-latest/dts/arm/ambiq/
Dambiq_apollo4p.dtsi15 #clock-cells = <0>;
21 #size-cells = <0>;
23 cpu0: cpu@0 {
25 reg = <0>;
32 reg = <0xe0000000 0x1000>;
68 reg = <0x10000000 0x10000>;
75 reg = <0x10010000 0x2B0000>;
83 reg = <0x00018000 0x1e8000>;
91 reg = <0x00018000 0x1e8000>;
97 reg = <0x40021000 0x400>;
[all …]
Dambiq_apollo4p_blue.dtsi14 #clock-cells = <0>;
30 #size-cells = <0>;
32 cpu0: cpu@0 {
34 reg = <0>;
40 reg = <0xe0000000 0x1000>;
49 reg = <0x10000000 0x10000>;
56 reg = <0x10010000 0x2B0000>;
64 reg = <0x00018000 0x1e8000>;
72 reg = <0x00018000 0x1e8000>;
78 reg = <0x40021000 0x400>;
[all …]
/Zephyr-latest/drivers/ethernet/
Deth_lan865x.c27 uint32_t ctl = 0; in lan865x_mac_rxtx_control()
113 for (i = 0; !ctx->reset && i < LAN865X_RESET_TIMEOUT; i++) { in lan865x_wait_for_reset()
122 return 0; in lan865x_wait_for_reset()
138 gpio_pin_set_dt(&cfg->reset, 0); in lan865x_gpio_reset()
150 if (ret < 0) { in lan865x_check_spi()
159 ctx->chip_id = (val >> 4) & 0xFFFF; in lan865x_check_spi()
174 oa_tc6_reg_write(ctx->tc6, 0x000400D8, addr); in lan865x_read_indirect_reg()
175 oa_tc6_reg_write(ctx->tc6, 0x000400DA, 0x02); in lan865x_read_indirect_reg()
177 oa_tc6_reg_read(ctx->tc6, 0x000400D9, &val); in lan865x_read_indirect_reg()
187 { .mms = 0x1, .address = 0x00, .value = 0x0000 },
[all …]
Deth_stellaris_priv.h17 #define REG_MACRIS (REG_BASE(dev) + 0x000)
18 #define REG_MACIM (REG_BASE(dev) + 0x004)
19 #define REG_MACRCTL (REG_BASE(dev) + 0x008)
20 #define REG_MACTCTL (REG_BASE(dev) + 0x00C)
21 #define REG_MACDATA (REG_BASE(dev) + 0x010)
22 #define REG_MACIA0 (REG_BASE(dev) + 0x014)
23 #define REG_MACIA1 (REG_BASE(dev) + 0x018)
24 #define REG_MACNP (REG_BASE(dev) + 0x034)
25 #define REG_MACTR (REG_BASE(dev) + 0x038)
28 #define BIT_MACRCTL_RSTFIFO 0x10
[all …]
Deth_smsc91x_priv.h11 /* All Banks, Offset 0xe: Bank Select Register */
12 #define BSR 0xe
13 #define BSR_BANK_MASK GENMASK(2, 0) /* Which bank is currently selected */
14 #define BSR_IDENTIFY 0x33
17 /* Bank 0, Offset 0x0: Transmit Control Register */
18 #define TCR 0x0
19 #define TCR_TXENA 0x0001 /* Enable/disable transmitter */
20 #define TCR_PAD_EN 0x0080 /* Pad TX frames to 64 bytes */
22 /* Bank 0, Offset 0x02: EPH status register */
23 #define EPHSR 0x2
[all …]
/Zephyr-latest/arch/arm64/core/
Dswitch.S37 mrs x4, sp_el0
46 stp x29, x4, [x1, #_thread_offset_to_callee_saved_x29_sp_el0]
52 mov x4, sp
53 stp x4, lr, [x1, #_thread_offset_to_callee_saved_sp_elx_lr]
56 mrs x4, tpidrro_el0
57 lsr x2, x4, #TPIDRROEL0_EXC_SHIFT
62 bic x4, x4, #TPIDRROEL0_EXC_DEPTH
63 orr x4, x4, x2, lsl #TPIDRROEL0_EXC_SHIFT
64 msr tpidrro_el0, x4
99 ldp x29, x4, [x0, #_thread_offset_to_callee_saved_x29_sp_el0]
[all …]
Dsmccc-call.S20 \instr #0
21 ldr x4, [sp]
22 stp x0, x1, [x4, __arm_smccc_res_t_a0_a1_OFFSET]
23 stp x2, x3, [x4, __arm_smccc_res_t_a2_a3_OFFSET]
24 stp x4, x5, [x4, __arm_smccc_res_t_a4_a5_OFFSET]
25 stp x6, x7, [x4, __arm_smccc_res_t_a6_a7_OFFSET]
Duserspace.S29 mov x0, #0
30 mov x4, #0
46 mov x4, #-1
47 mov x0, #0
74 mrs x4, PAR_EL1
75 tbnz x4, #0, abv_fail
81 mov x0, #0
98 ldp x4, x5, [sp, ___esf_t_x4_x5_OFFSET]
/Zephyr-latest/include/zephyr/dt-bindings/sensor/
Dlsm6dsv16x.h10 #define LSM6DSV16X_DT_FS_2G 0
16 #define LSM6DSV16X_DT_FS_125DPS 0x0
17 #define LSM6DSV16X_DT_FS_250DPS 0x1
18 #define LSM6DSV16X_DT_FS_500DPS 0x2
19 #define LSM6DSV16X_DT_FS_1000DPS 0x3
20 #define LSM6DSV16X_DT_FS_2000DPS 0x4
21 #define LSM6DSV16X_DT_FS_4000DPS 0xc
24 #define LSM6DSV16X_DT_ODR_OFF 0x0
25 #define LSM6DSV16X_DT_ODR_AT_1Hz875 0x1
26 #define LSM6DSV16X_DT_ODR_AT_7Hz5 0x2
[all …]
/Zephyr-latest/soc/intel/alder_lake/
Dsoc_gpio.h20 #define REG_PAD_OWNER_BASE 0x0020
21 #define REG_GPI_INT_STS_BASE 0x0100
22 #define PAD_CFG0_PMODE_MASK (0x0F << 10)
24 #define REG_PAD_BASE_ADDR 0x000C
25 #define REG_GPI_INT_EN_BASE 0x0120
26 #define REG_PAD_HOST_SW_OWNER 0x0B0
27 #define PAD_BASE_ADDR_MASK 0xfff
38 ((((pin_offset / 8) + 1) + (raw_pin / 8)) * 0x4) : \
40 (((pin_offset / 8) + (raw_pin / 8)) * 0x4); \
47 (cfg->group_index * 0x4)
[all …]
/Zephyr-latest/soc/intel/elkhart_lake/
Dsoc_gpio.h20 #define REG_PAD_OWNER_BASE 0x0020
21 #define REG_GPI_INT_STS_BASE 0x0100
22 #define PAD_CFG0_PMODE_MASK (0x0F << 10)
24 #define REG_PAD_BASE_ADDR 0x000C
25 #define REG_GPI_INT_EN_BASE 0x0120
26 #define REG_PAD_HOST_SW_OWNER 0x0B0
27 #define PAD_BASE_ADDR_MASK 0xfff
38 ((((pin_offset / 8) + 1) + (raw_pin / 8)) * 0x4) : \
40 (((pin_offset / 8) + (raw_pin / 8)) * 0x4); \
47 (cfg->group_index * 0x4)
[all …]
/Zephyr-latest/soc/intel/raptor_lake/
Dsoc_gpio.h20 #define REG_PAD_OWNER_BASE 0x00A0
21 #define REG_GPI_INT_STS_BASE 0x0200
22 #define REG_GPI_INT_EN_BASE 0x0220
23 #define REG_PAD_HOST_SW_OWNER 0x150
27 #define REG_PAD_OWNER_BASE 0x0020
28 #define REG_GPI_INT_STS_BASE 0x0100
29 #define REG_GPI_INT_EN_BASE 0x0120
30 #define REG_PAD_HOST_SW_OWNER 0x0B0
33 #define PAD_CFG0_PMODE_MASK (0x07 << 10)
34 #define PAD_BASE_ADDR_MASK 0xfff
[all …]
/Zephyr-latest/tests/drivers/coredump/coredump_api/boards/
Dqemu_riscv32.overlay13 memory-regions = <0x85000000 0x4>,
14 <0x85000004 0x4>;
22 memory-regions = <0x86000000 0xC>;
29 memory-regions = <0x0 0x4>;
/Zephyr-latest/dts/arm/nuvoton/npcx/
Dnpcx-alts-map.dtsi12 /* SCFG DEVALT 0 */
14 alts = <&scfg 0x00 0x0 0>;
17 alts = <&scfg 0x00 0x3 1>;
21 alts = <&scfg 0x00 0x7 1>;
26 alts = <&scfg 0x01 0x0 0>;
29 alts = <&scfg 0x01 0x2 0>;
32 alts = <&scfg 0x01 0x3 0>;
35 alts = <&scfg 0x01 0x4 1>;
38 alts = <&scfg 0x01 0x5 0>;
41 alts = <&scfg 0x01 0x6 0>;
[all …]
/Zephyr-latest/soc/litex/litex_vexriscv/
Dsoc.h29 | sys_read8(addr + 0x4); in litex_read16()
41 | (sys_read8(addr + 0x4) << 16) in litex_read32()
42 | (sys_read8(addr + 0x8) << 8) in litex_read32()
43 | sys_read8(addr + 0xc); in litex_read32()
55 | ((uint64_t)sys_read8(addr + 0x4) << 48) in litex_read64()
56 | ((uint64_t)sys_read8(addr + 0x8) << 40) in litex_read64()
57 | ((uint64_t)sys_read8(addr + 0xc) << 32) in litex_read64()
58 | ((uint64_t)sys_read8(addr + 0x10) << 24) in litex_read64()
59 | ((uint64_t)sys_read8(addr + 0x14) << 16) in litex_read64()
60 | ((uint64_t)sys_read8(addr + 0x18) << 8) in litex_read64()
[all …]
/Zephyr-latest/boards/nxp/imx8ulp_evk/
Dimx8ulp_evk_mimx8ud7_adsp-pinctrl.dtsi9 pinmux = <0x298c0158 0x4 0x298c09e0 0x3 0x298c0158>;
13 pinmux = <0x298c015c 0x4 0x298c09dc 0x3 0x298c015c>;
/Zephyr-latest/dts/arm/nuvoton/npcx/npcx4/
Dnpcx4-alts-map.dtsi15 /* SCFG DEVALT 0 */
17 alts = <&scfg 0x00 0x4 0>;
20 alts = <&scfg 0x00 0x6 0>;
25 alts = <&scfg 0x02 0x7 0>;
30 alts = <&scfg 0x05 0x1 0>;
33 alts = <&scfg 0x05 0x7 0>;
38 alts = <&scfg 0x0E 0x6 0>;
41 alts = <&scfg 0x0E 0x7 0>;
46 alts = <&scfg 0x0F 0x5 0>;
49 alts = <&scfg 0x0F 0x6 0>;
[all …]

12345678910>>...14