1 /* 2 * Copyright (c) 2024-2025 Renesas Electronics Corporation 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef __ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_RA_PINCTRL_H__ 8 #define __ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_RA_PINCTRL_H__ 9 10 #define RA_PORT_NUM_POS 0 11 #define RA_PORT_NUM_MASK 0xf 12 13 #define RA_PIN_NUM_POS 4 14 #define RA_PIN_NUM_MASK 0xf 15 16 #define RA_PSEL_HIZ_JTAG_SWD 0x0 17 #define RA_PSEL_ADC 0x0 18 #define RA_PSEL_DAC 0x0 19 #define RA_PSEL_ACMPHS 0x0 20 #define RA_PSEL_AGT 0x1 21 #define RA_PSEL_GPT0 0x2 22 #define RA_PSEL_GPT1 0x3 23 #define RA_PSEL_SCI_0 0x4 24 #define RA_PSEL_SCI_2 0x4 25 #define RA_PSEL_SCI_4 0x4 26 #define RA_PSEL_SCI_6 0x4 27 #define RA_PSEL_SCI_8 0x4 28 #define RA_PSEL_SCI_1 0x5 29 #define RA_PSEL_SCI_3 0x5 30 #define RA_PSEL_SCI_5 0x5 31 #define RA_PSEL_SCI_7 0x5 32 #define RA_PSEL_SCI_9 0x5 33 #define RA_PSEL_SPI 0x6 34 #define RA_PSEL_I2C 0x7 35 #define RA_PSEL_CLKOUT_RTC 0x9 36 #define RA_PSEL_ACMPHS_VCOUT 0x9 37 #define RA_PSEL_CAC_ADC 0xa 38 #define RA_PSEL_CAC_DAC 0xa 39 #define RA_PSEL_BUS 0xb 40 #define RA_PSEL_CANFD 0x10 41 #define RA_PSEL_QSPI 0x11 42 #define RA_PSEL_SSIE 0x12 43 #define RA_PSEL_USBFS 0x13 44 #define RA_PSEL_USBHS 0x14 45 #define RA_PSEL_SDHI 0x15 46 #define RA_PSEL_ETH_MII 0x16 47 #define RA_PSEL_ETH_RMII 0x17 48 #define RA_PSEL_GLCDC 0x19 49 #define RA_PSEL_OSPI 0x1c 50 51 #define RA_PSEL_POS 8 52 #define RA_PSEL_MASK 0x1f 53 54 #define RA_MODE_POS 13 55 #define RA_MODE_MASK 0x1 56 57 #define RA_PSEL(psel, port_num, pin_num) \ 58 (1 << RA_MODE_POS | psel << RA_PSEL_POS | port_num << RA_PORT_NUM_POS | \ 59 pin_num << RA_PIN_NUM_POS) 60 61 #endif /* __ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_RA_PINCTRL_H__ */ 62
