1 /* 2 * Copyright (c) 2023, Intel Corporation 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 /** 8 * @file 9 * @brief GPIO macros for the Raptor Lake SoC 10 * 11 * This header file is used to specify the GPIO macros for 12 * the Raptor Lake SoC. 13 */ 14 15 #ifndef __SOC_GPIO_H_ 16 #define __SOC_GPIO_H_ 17 18 #if defined(CONFIG_BOARD_INTEL_RPL_S_CRB) 19 #define GPIO_INTEL_NR_SUBDEVS 13 20 #define REG_PAD_OWNER_BASE 0x00A0 21 #define REG_GPI_INT_STS_BASE 0x0200 22 #define REG_GPI_INT_EN_BASE 0x0220 23 #define REG_PAD_HOST_SW_OWNER 0x150 24 25 #elif defined(CONFIG_BOARD_INTEL_RPL_P_CRB) 26 #define GPIO_INTEL_NR_SUBDEVS 11 27 #define REG_PAD_OWNER_BASE 0x0020 28 #define REG_GPI_INT_STS_BASE 0x0100 29 #define REG_GPI_INT_EN_BASE 0x0120 30 #define REG_PAD_HOST_SW_OWNER 0x0B0 31 #endif 32 33 #define PAD_CFG0_PMODE_MASK (0x07 << 10) 34 #define PAD_BASE_ADDR_MASK 0xfff 35 36 #define GPIO_REG_BASE(reg_base) \ 37 (reg_base & ~PAD_BASE_ADDR_MASK) 38 39 #define GPIO_PAD_BASE(reg_base) \ 40 (reg_base & PAD_BASE_ADDR_MASK) 41 42 #define GPIO_PAD_OWNERSHIP(raw_pin, pin_offset) \ 43 (pin_offset % 8) ? \ 44 REG_PAD_OWNER_BASE + \ 45 ((((pin_offset / 8) + 1) + (raw_pin / 8)) * 0x4) : \ 46 REG_PAD_OWNER_BASE + \ 47 (((pin_offset / 8) + (raw_pin / 8)) * 0x4); \ 48 49 #define GPIO_OWNERSHIP_BIT(raw_pin) ((raw_pin % 8) * 4) 50 51 #define GPIO_RAW_PIN(pin, pin_offset) pin 52 53 #define GPIO_INTERRUPT_BASE(cfg) \ 54 (cfg->group_index * 0x4) 55 56 #define GPIO_BASE(cfg) \ 57 (cfg->group_index * 0x4) 58 59 #define PIN_OFFSET 0x10 60 61 #endif /* __SOC_GPIO_H_ */ 62
