1 /* 2 * Copyright (c) 2021-2023, Intel Corporation 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 /** 8 * @file 9 * @brief GPIO macros for the Alder Lake SoC 10 * 11 * This header file is used to specify the GPIO macros for 12 * the Alder Lake SoC. 13 */ 14 15 #ifndef __SOC_GPIO_H_ 16 #define __SOC_GPIO_H_ 17 18 #define GPIO_INTEL_NR_SUBDEVS 10 19 20 #define REG_PAD_OWNER_BASE 0x0020 21 #define REG_GPI_INT_STS_BASE 0x0100 22 #define PAD_CFG0_PMODE_MASK (0x0F << 10) 23 24 #define REG_PAD_BASE_ADDR 0x000C 25 #define REG_GPI_INT_EN_BASE 0x0120 26 #define REG_PAD_HOST_SW_OWNER 0x0B0 27 #define PAD_BASE_ADDR_MASK 0xfff 28 29 #define GPIO_REG_BASE(reg_base) \ 30 (reg_base & ~PAD_BASE_ADDR_MASK) 31 32 #define GPIO_PAD_BASE(reg_base) \ 33 (reg_base & PAD_BASE_ADDR_MASK) 34 35 #define GPIO_PAD_OWNERSHIP(raw_pin, pin_offset) \ 36 (pin_offset % 8) ? \ 37 REG_PAD_OWNER_BASE + \ 38 ((((pin_offset / 8) + 1) + (raw_pin / 8)) * 0x4) : \ 39 REG_PAD_OWNER_BASE + \ 40 (((pin_offset / 8) + (raw_pin / 8)) * 0x4); \ 41 42 #define GPIO_OWNERSHIP_BIT(raw_pin) ((raw_pin % 8) * 4) 43 44 #define GPIO_RAW_PIN(pin, pin_offset) pin 45 46 #define GPIO_INTERRUPT_BASE(cfg) \ 47 (cfg->group_index * 0x4) 48 49 #define GPIO_BASE(cfg) \ 50 (cfg->group_index * 0x4) 51 52 #define PIN_OFFSET 0x10 53 54 #endif /* __SOC_GPIO_H_ */ 55
