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/Zephyr-latest/dts/bindings/sensor/
Dti,tmp116.yaml15 default: 0x200
20 - 0 # TMP116_DT_ODR_15_5_MS
21 - 0x80 # TMP116_DT_ODR_125_MS
22 - 0x100 # TMP116_DT_ODR_250_MS
23 - 0x180 # TMP116_DT_ODR_500_MS
24 - 0x200 # TMP116_DT_ODR_1000_MS
25 - 0x280 # TMP116_DT_ODR_4000_MS
26 - 0x300 # TMP116_DT_ODR_8000_MS
27 - 0x380 # TMP116_DT_ODR_16000_MS
/Zephyr-latest/include/zephyr/dt-bindings/sensor/
Dtmp116.h19 #define TMP116_DT_ODR_15_5_MS 0
20 #define TMP116_DT_ODR_125_MS 0x80
21 #define TMP116_DT_ODR_250_MS 0x100
22 #define TMP116_DT_ODR_500_MS 0x180
23 #define TMP116_DT_ODR_1000_MS 0x200
24 #define TMP116_DT_ODR_4000_MS 0x280
25 #define TMP116_DT_ODR_8000_MS 0x300
26 #define TMP116_DT_ODR_16000_MS 0x380
/Zephyr-latest/dts/arm/atmel/
Dsamr21.dtsi17 ranges = <0x41004400 0x41004400 0x180>;
21 reg = <0x41004500 0x80>;
32 reg = <0x41004500 0x80>;
Dsamr34.dtsi23 ranges = <0x40002800 0x40002800 0x180>;
27 reg = <0x40002900 0x80>;
45 #size-cells = <0>;
47 dipo = <0>;
51 pinctrl-0 = <&sercom4_default>;
54 lora: sx1276@0 {
56 reg = <0>;
66 <&portb 0 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>; /* DIO5 */
Dsamc2x.dtsi16 adc-0 = &adc0;
22 sercom-0 = &sercom0;
27 tcc-0 = &tcc0;
40 #size-cells = <0>;
42 cpu0: cpu@0 {
44 reg = <0>;
56 reg = <0x0080A00C 0x4>,
57 <0x0080A040 0x4>,
58 <0x0080A044 0x4>,
59 <0x0080A048 0x4>;
[all …]
/Zephyr-latest/soc/intel/intel_adsp/common/include/
Dadsp-vectors.h13 #define MEM_VECBASE_LIT_SIZE 0x178
48 #define VECTOR_TBL_SIZE 0x1000
51 #define MEM_VECT_LIT_SIZE 0x8
52 #define MEM_VECT_TEXT_SIZE 0x38
54 #define MEM_ERROR_TEXT_SIZE 0x180
55 #define MEM_ERROR_LIT_SIZE 0x8
/Zephyr-latest/soc/intel/intel_adsp/ace/
Dpower_down.S12 .word 0x80000000 // IPC_DIPCTDR_BUSY
29 #define IPC_HOST_BASE 0x00073000
52 dpfl pfl_reg, 0
56 ipfl pfl_reg, 0
64 movi u32_ipc_response_mask, 0x20000000
85 l32i pfl_reg, p_ipc_regs, 0
120 * temp_reg0 = temp_reg0 | 0x80000000;
122 * *(p_ipc_regs + 0x180) = 0x0;
123 * *(p_ipc_regs + 0x10) = temp_reg0;
128 l32i temp_reg0, p_ipc_regs, 0
[all …]
/Zephyr-latest/arch/mips/core/
Dprep_c.c25 mips_cp0_status_int_mask = 0; in interrupt_init()
27 ebase = 0x80000000; in interrupt_init()
29 memcpy((void *)(ebase + 0x180), __isr_vec, 0x80); in interrupt_init()
/Zephyr-latest/include/zephyr/dt-bindings/reset/
Dstm32mp1_reset.h24 #define STM32_RESET_BUS_AHB2_SET 0x998
25 #define STM32_RESET_BUS_AHB2_CLR 0x99C
26 #define STM32_RESET_BUS_AHB3_SET 0x9A0
27 #define STM32_RESET_BUS_AHB3_CLR 0x9A4
28 #define STM32_RESET_BUS_AHB4_SET 0x9A8
29 #define STM32_RESET_BUS_AHB4_CLR 0x9AC
30 #define STM32_RESET_BUS_AHB5_SET 0x190
31 #define STM32_RESET_BUS_AHB5_CLR 0x194
32 #define STM32_RESET_BUS_AHB6_SET 0x198
33 #define STM32_RESET_BUS_AHB6_CLR 0x19C
[all …]
/Zephyr-latest/soc/amd/acp_6_0/adsp/
Dmemory.h12 #define PLATFORM_PRIMARY_CORE_ID 0
14 #define IRAM_BASE 0x7F000000
15 #define IRAM_SIZE 0x60000
17 #define IRAM_RESERVE_HEADER_SPACE 0x400
19 #define MEM_RESET_TEXT_SIZE 0x400
20 #define MEM_RESET_LIT_SIZE 0x8
21 #define XCHAL_RESET_VECTOR_PADDR_IRAM 0x7F000000
22 #define XCHAL_WINDOW_VECTORS_PADDR_IRAM 0x7F000400
26 #define MEM_VECBASE_LIT_SIZE 0x178
27 #define MEM_WIN_TEXT_SIZE 0x178
[all …]
/Zephyr-latest/dts/bindings/gpio/
Dambiq,gpio.yaml21 gpio-map-mask = <0xffffffe0 0xffffffc0>;
22 gpio-map-pass-thru = <0x1f 0x3f>;
24 0x00 0x0 &gpio0_31 0x0 0x0
25 0x20 0x0 &gpio32_63 0x0 0x0
26 0x40 0x0 &gpio64_95 0x0 0x0
27 0x60 0x0 &gpio96_127 0x0 0x0
29 reg = <0x40010000>;
32 #size-cells = <0>;
35 gpio0_31: gpio0_31@0 {
39 reg = <0>;
[all …]
/Zephyr-latest/include/zephyr/drivers/interrupt_controller/
Dgic.h23 #define GIC_DIST_BASE DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 0)
24 #define GIC_CPU_BASE DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 1)
31 * 0x000 Distributor Control Register
35 #define GICD_CTLR (GIC_DIST_BASE + 0x0)
38 * 0x004 Interrupt Controller Type Register
42 #define GICD_TYPER (GIC_DIST_BASE + 0x4)
45 * 0x008 Distributor Implementer Identification Register
49 #define GICD_IIDR (GIC_DIST_BASE + 0x8)
52 * 0x080 Interrupt Group Registers
56 #define GICD_IGROUPRn (GIC_DIST_BASE + 0x80)
[all …]
Dloapic.h18 #define LOAPIC_ID 0x020 /* Local APIC ID Reg */
19 #define LOAPIC_VER 0x030 /* Local APIC Version Reg */
20 #define LOAPIC_TPR 0x080 /* Task Priority Reg */
21 #define LOAPIC_APR 0x090 /* Arbitration Priority Reg */
22 #define LOAPIC_PPR 0x0a0 /* Processor Priority Reg */
23 #define LOAPIC_EOI 0x0b0 /* EOI Reg */
24 #define LOAPIC_LDR 0x0d0 /* Logical Destination Reg */
25 #define LOAPIC_DFR 0x0e0 /* Destination Format Reg */
26 #define LOAPIC_SVR 0x0f0 /* Spurious Interrupt Reg */
27 #define LOAPIC_ISR 0x100 /* In-service Reg */
[all …]
/Zephyr-latest/soc/intel/intel_adsp/ace/include/
Dadsp_memory.h24 #define ROM_JUMP_ADDR (LP_SRAM_BASE + 0x10)
45 #define IMR_BOOT_LDR_MANIFEST_OFFSET 0x42000
46 #define IMR_BOOT_LDR_MANIFEST_SIZE 0x6000
49 #define IMR_BOOT_LDR_TEXT_ENTRY_SIZE 0x180
52 #define IMR_BOOT_LDR_LIT_SIZE 0x40
56 #define IMR_BOOT_LDR_TEXT_SIZE 0x1C00
59 #define IMR_BOOT_LDR_DATA_OFFSET 0x49000
61 #define IMR_BOOT_LDR_DATA_SIZE 0xA8000
63 #define IMR_BOOT_LDR_BSS_OFFSET 0x110000
65 #define IMR_BOOT_LDR_BSS_SIZE 0x40000
[all …]
/Zephyr-latest/samples/subsys/canbus/isotp/src/
Dmain.c10 const struct isotp_fc_opts fc_opts_8_0 = {.bs = 8, .stmin = 0};
11 const struct isotp_fc_opts fc_opts_0_5 = {.bs = 0, .stmin = 5};
14 .std_id = 0x80,
20 .std_id = 0x180,
27 .std_id = 0x01,
33 .std_id = 0x101,
77 received_len = 0; in rx_8_0_thread()
81 if (rem_len < 0) { in rx_8_0_thread()
116 if (received_len < 0) { in rx_0_5_thread()
121 rx_buffer[received_len] = '\0'; in rx_0_5_thread()
[all …]
/Zephyr-latest/dts/riscv/openisa/
Drv32m1.dtsi22 #size-cells = <0>;
23 cpu@0 {
27 reg = <0>;
40 reg = <0x20000000 0x30000>;
45 reg = <0x09000000 0x20000>;
62 reg = <0x4002b000 0x200>;
68 reg = <0x41027000 0x200>;
74 #address-cells = <0>;
77 reg = <0xe0041000 0x88>;
82 #address-cells = <0>;
[all …]
/Zephyr-latest/include/zephyr/arch/x86/
Dintel_vtd.h15 #define VTD_VER_REG 0x000 /* Version */
16 #define VTD_CAP_REG 0x008 /* Capability */
17 #define VTD_ECAP_REG 0x010 /* Extended Capability */
18 #define VTD_GCMD_REG 0x018 /* Global Command */
19 #define VTD_GSTS_REG 0x01C /* Global Status */
20 #define VTD_RTADDR_REG 0x020 /* Root Table Address */
21 #define VTD_CCMD_REG 0x028 /* Context Command */
22 #define VTD_FSTS_REG 0x034 /* Fault Status */
23 #define VTD_FECTL_REG 0x038 /* Fault Event Control */
24 #define VTD_FEDATA_REG 0x03C /* Fault Event Data */
[all …]
/Zephyr-latest/soc/nuvoton/npcx/common/
Dregisters.c11 NPCX_REG_SIZE_CHECK(cdcg_reg, 0x116);
12 NPCX_REG_OFFSET_CHECK(cdcg_reg, HFCBCD, 0x010);
13 NPCX_REG_OFFSET_CHECK(cdcg_reg, HFCBCD2, 0x014);
14 NPCX_REG_OFFSET_CHECK(cdcg_reg, LFCGCTL, 0x100);
15 NPCX_REG_OFFSET_CHECK(cdcg_reg, LFCGCTL2, 0x114);
18 NPCX_REG_SIZE_CHECK(pmc_reg, 0x025);
19 NPCX_REG_OFFSET_CHECK(pmc_reg, ENIDL_CTL, 0x003);
20 NPCX_REG_OFFSET_CHECK(pmc_reg, PWDWN_CTL1, 0x008);
21 NPCX_REG_OFFSET_CHECK(pmc_reg, PWDWN_CTL7, 0x024);
24 NPCX_REG_SIZE_CHECK(scfg_reg, 0x02f);
[all …]
/Zephyr-latest/drivers/dai/intel/ssp/
Dssp_regs_v3.h11 #define SSCR0 0x00
12 #define SSCR1 0x04
13 #define SSSR 0x08
14 #define SSITR 0x0C
15 #define SSTO 0x28
16 #define SSPSP 0x2C
17 #define SSTSS 0x38
18 #define SSCR2 0x40
19 #define SSPSP2 0x44
21 #define SSIOC 0x4C
[all …]
Dssp_regs_v1.h11 #define SSCR0 0x00
12 #define SSCR1 0x04
13 #define SSSR 0x08
14 #define SSITR 0x0C
15 #define SSTO 0x28
16 #define SSPSP 0x2C
17 #define SSTSS 0x38
18 #define SSCR2 0x40
19 #define SSPSP2 0x44
20 #define SSIOC 0x4C
[all …]
Dssp_regs_v2.h11 #define SSCR0 0x00
12 #define SSCR1 0x04
13 #define SSSR 0x08
14 #define SSITR 0x0C
15 #define SSTO 0x28
16 #define SSPSP 0x2C
17 #define SSTSS 0x38
18 #define SSCR2 0x40
19 #define SSPSP2 0x44
21 #define SSIOC 0x4C
[all …]
/Zephyr-latest/soc/espressif/common/include/
D_soc_inthandlers.h124 if (mask & 0x7f) { in _xtensa_handle_one_int1()
125 if (mask & 0x7) { in _xtensa_handle_one_int1()
126 if (mask & BIT(0)) { in _xtensa_handle_one_int1()
127 mask = BIT(0); in _xtensa_handle_one_int1()
128 irq = 0; in _xtensa_handle_one_int1()
142 if (mask & 0x18) { in _xtensa_handle_one_int1()
167 if (mask & 0x780) { in _xtensa_handle_one_int1()
168 if (mask & 0x180) { in _xtensa_handle_one_int1()
192 if (mask & 0x3000) { in _xtensa_handle_one_int1()
217 return 0; in _xtensa_handle_one_int1()
[all …]
/Zephyr-latest/soc/nxp/imxrt/
Dflexspi_nor_config.h15 #define FLEXSPI_CFG_BLK_TAG (0x42464346UL)
16 #define FLEXSPI_CFG_BLK_VERSION (0x56010400UL)
21 #define CMD_INDEX_READ 0
26 #define CMD_LUT_SEQ_IDX_READ 0
31 #define CMD_SDR 0x01
32 #define CMD_DDR 0x21
33 #define RADDR_SDR 0x02
34 #define RADDR_DDR 0x22
35 #define CADDR_SDR 0x03
36 #define CADDR_DDR 0x23
[all …]
/Zephyr-latest/soc/espressif/esp32/
Dmcuboot.ld33 IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000
100 . = 0x0;
102 . = 0x180;
104 . = 0x1c0;
106 . = 0x200;
108 . = 0x240;
110 . = 0x280;
112 . = 0x2c0;
114 . = 0x300;
116 . = 0x340;
[all …]
/Zephyr-latest/soc/espressif/esp32s2/
Dmcuboot.ld32 IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000
94 . = 0x0;
96 . = 0x180;
98 . = 0x1c0;
100 . = 0x200;
102 . = 0x240;
104 . = 0x280;
106 . = 0x2c0;
108 . = 0x300;
110 . = 0x340;
[all …]

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