Lines Matching +full:0 +full:x180
23 #define GIC_DIST_BASE DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 0)
24 #define GIC_CPU_BASE DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 1)
31 * 0x000 Distributor Control Register
35 #define GICD_CTLR (GIC_DIST_BASE + 0x0)
38 * 0x004 Interrupt Controller Type Register
42 #define GICD_TYPER (GIC_DIST_BASE + 0x4)
45 * 0x008 Distributor Implementer Identification Register
49 #define GICD_IIDR (GIC_DIST_BASE + 0x8)
52 * 0x080 Interrupt Group Registers
56 #define GICD_IGROUPRn (GIC_DIST_BASE + 0x80)
59 * 0x100 Interrupt Set-Enable Registers
63 #define GICD_ISENABLERn (GIC_DIST_BASE + 0x100)
66 * 0x180 Interrupt Clear-Enable Registers
70 #define GICD_ICENABLERn (GIC_DIST_BASE + 0x180)
73 * 0x200 Interrupt Set-Pending Registers
77 #define GICD_ISPENDRn (GIC_DIST_BASE + 0x200)
80 * 0x280 Interrupt Clear-Pending Registers
84 #define GICD_ICPENDRn (GIC_DIST_BASE + 0x280)
87 * 0x300 Interrupt Set-Active Registers
91 #define GICD_ISACTIVERn (GIC_DIST_BASE + 0x300)
95 * 0x380 Interrupt Clear-Active Registers
98 #define GICD_ICACTIVERn (GIC_DIST_BASE + 0x380)
102 * 0x400 Interrupt Priority Registers
106 #define GICD_IPRIORITYRn (GIC_DIST_BASE + 0x400)
109 * 0x800 Interrupt Processor Targets Registers
113 #define GICD_ITARGETSRn (GIC_DIST_BASE + 0x800)
116 * 0xC00 Interrupt Configuration Registers
120 #define GICD_ICFGRn (GIC_DIST_BASE + 0xc00)
123 * 0xF00 Software Generated Interrupt Register
127 #define GICD_SGIR (GIC_DIST_BASE + 0xf00)
136 * 0x0000 CPU Interface Control Register
140 #define GICC_CTLR (GIC_CPU_BASE + 0x0)
143 * 0x0004 Interrupt Priority Mask Register
147 #define GICC_PMR (GIC_CPU_BASE + 0x4)
150 * 0x0008 Binary Point Register
154 #define GICC_BPR (GIC_CPU_BASE + 0x8)
157 * 0x000C Interrupt Acknowledge Register
161 #define GICC_IAR (GIC_CPU_BASE + 0xc)
164 * 0x0010 End of Interrupt Register
168 #define GICC_EOIR (GIC_CPU_BASE + 0x10)
176 #define GICC_CTLR_ENABLEGRP0 BIT(0)
197 #define GICD_SGIR_TGTFILT_CPULIST GICD_SGIR_TGTFILT(0b00)
198 #define GICD_SGIR_TGTFILT_ALLBUTREQ GICD_SGIR_TGTFILT(0b01)
199 #define GICD_SGIR_TGTFILT_REQONLY GICD_SGIR_TGTFILT(0b10)
203 #define GICD_SGIR_CPULIST_MASK 0xff
216 /* GICD_TYPER.ITLinesNumber 0:4 */
217 #define GICD_TYPER_ITLINESNUM_MASK 0x1f
220 #define GICD_TYPER_IDBITS(typer) ((((typer) >> 19) & 0x1f) + 1)
225 #define GIC_SGI_INT_BASE 0
245 /* GIC idle priority : value '0xff' will allow all interrupts */
246 #define GIC_IDLE_PRIO 0xff
248 /* Priority levels 0:255 */
249 #define GIC_PRI_MASK 0xff
252 * '0xa0'is used to initialize each interrupt default priority.
254 * Any value '0x80' to '0xff' will work for both NS and S state.
258 #define GIC_INT_DEF_PRI_X4 0xa0a0a0a0
353 * @param sgi_id SGI ID 0 to 15