Lines Matching +full:0 +full:x180

12 #define PLATFORM_PRIMARY_CORE_ID 0
14 #define IRAM_BASE 0x7F000000
15 #define IRAM_SIZE 0x60000
17 #define IRAM_RESERVE_HEADER_SPACE 0x400
19 #define MEM_RESET_TEXT_SIZE             0x400
20 #define MEM_RESET_LIT_SIZE              0x8
21 #define XCHAL_RESET_VECTOR_PADDR_IRAM   0x7F000000
22 #define XCHAL_WINDOW_VECTORS_PADDR_IRAM 0x7F000400
26 #define MEM_VECBASE_LIT_SIZE 0x178
27 #define MEM_WIN_TEXT_SIZE    0x178
30 #define MEM_VECT_LIT_SIZE  0x7
31 #define MEM_VECT_TEXT_SIZE 0x37
33 #define XCHAL_INTLEVEL2_VECTOR_PADDR_IRAM (XCHAL_VECBASE_RESET_PADDR_IRAM + 0x180)
35 #define XCHAL_INTLEVEL3_VECTOR_PADDR_IRAM (XCHAL_VECBASE_RESET_PADDR_IRAM + 0x1C0)
37 #define XCHAL_INTLEVEL4_VECTOR_PADDR_IRAM (XCHAL_VECBASE_RESET_PADDR_IRAM + 0x200)
39 #define XCHAL_INTLEVEL5_VECTOR_PADDR_IRAM (XCHAL_VECBASE_RESET_PADDR_IRAM + 0x240)
41 #define XCHAL_INTLEVEL6_VECTOR_PADDR_IRAM (XCHAL_VECBASE_RESET_PADDR_IRAM + 0x280)
43 #define XCHAL_INTLEVEL7_VECTOR_PADDR_IRAM (XCHAL_VECBASE_RESET_PADDR_IRAM + 0x2C0)
45 #define XCHAL_KERNEL_VECTOR_PADDR_IRAM (XCHAL_VECBASE_RESET_PADDR_IRAM + 0x300)
47 #define XCHAL_USER_VECTOR_PADDR_IRAM (XCHAL_VECBASE_RESET_PADDR_IRAM + 0x340)
49 #define XCHAL_DOUBLEEXC_VECTOR_PADDR_IRAM (XCHAL_VECBASE_RESET_PADDR_IRAM + 0x3C0)
57 #define IDT_SIZE               0x2000
59 #define IRAM_BASE              0x7F000000
60 #define IRAM_SIZE              0x60000    /* 384K */
61 #define SRAM0_BASE             0x9FF00000 /* Scratch mem */
62 #define SRAM1_BASE             0x60006000
63 #define SRAM1_SIZE             0x80000 /* 256K Data Mem */
64 #define DRAM0_BASE             0xE0000000
65 #define DRAM0_SIZE             0x20000 /* 128K ,to use for heap mem */
67 #define DMA0_SIZE              0x4
68 #define PU_REGISTER_BASE       (0x9FD00000 - 0x01240000)
69 #define ACP_I2S_RX_RINGBUFADDR 0x1242000
73 #define DAI_SIZE               0x4
78 #define UUID_ENTRY_ELF_BASE    0x1FFFA000
80 	0x6000 /* Log buffer  base need to be updated properly, these are used in linker scripts   \
82 #define LOG_ENTRY_ELF_BASE    0x20000000
83 #define LOG_ENTRY_ELF_SIZE    0x2000000
85 #define EXT_MANIFEST_ELF_SIZE 0x2000000 /* Stack configuration */
86 #define SOF_STACK_SIZE        0x1000
91 #define SRAM_OUTBOX_SIZE      0x400
92 #define SRAM_OUTBOX_OFFSET    0
94 #define SRAM_INBOX_SIZE       0x400
97 #define SRAM_DEBUG_SIZE       0x400
100 #define SRAM_EXCEPT_SIZE      0x400
103 #define SRAM_STREAM_SIZE      0x400
106 #define SRAM_TRACE_SIZE       0x400
112 #define HEAP_RT_COUNT8        0
127 #define HEAP_SYSTEM_SIZE      0xE000
138 #define HEAP_BUFFER_SIZE                 (0xF000)
139 #define HEAP_BUFFER_BLOCK_SIZE           0x180
146 #define SOF_MEM_VECT_LIT_SIZE            0x7
147 #define SOF_MEM_VECT_TEXT_SIZE           0x37
149 #define SOF_MEM_RESET_TEXT_SIZE          0x400
150 #define SOF_MEM_RESET_LIT_SIZE           0x8
151 #define SOF_MEM_VECBASE_LIT_SIZE         0x178
152 #define SOF_MEM_WIN_TEXT_SIZE            0x178
153 #define SOF_MEM_RO_SIZE                  0x8
156 #define is_uncached(address)             0