Lines Matching +full:0 +full:x180
11 #define SSCR0 0x00
12 #define SSCR1 0x04
13 #define SSSR 0x08
14 #define SSITR 0x0C
15 #define SSTO 0x28
16 #define SSPSP 0x2C
17 #define SSTSS 0x38
18 #define SSCR2 0x40
19 #define SSPSP2 0x44
20 #define SSIOC 0x4C
21 #define SSGFS 0x50
22 #define SSDR 0x10 /* Not PTL */
23 #define SSTSA 0x30 /* Not PTL */
24 #define SSRSA 0x34 /* Not PTL */
30 #define SSCR0_DSIZE(x) DAI_INTEL_SSP_SET_BITS(3, 0, (x) - 1)
31 #define SSCR0_DSIZE_GET(x) (((x) & DAI_INTEL_SSP_MASK(3, 0)) + 1)
33 #define SSCR0_MOT DAI_INTEL_SSP_SET_BITS(5, 4, 0)
51 #define SSCR1_RIE BIT(0)
100 #define SSPSP_SCMODE(x) DAI_INTEL_SSP_SET_BITS(1, 0, x)
109 #define SSPSP_DMYSTOP_MASK DAI_INTEL_SSP_MASK(SSPSP_DMYSTOP_BITS - 1, 0)
113 #define SSPSP2 0x44
114 #define SSPSP2_FEP_MASK 0xff
116 #define SSCR3 0x48
117 #define SSIOC 0x4C
121 #define SSTSA_SSTSA(x) DAI_INTEL_SSP_SET_BITS(7, 0, x)
122 #define SSTSA_GET(x) ((x) & DAI_INTEL_SSP_MASK(7, 0))
126 #define SSRSA_SSRSA(x) DAI_INTEL_SSP_SET_BITS(7, 0, x)
127 #define SSRSA_GET(x) ((x) & DAI_INTEL_SSP_MASK(7, 0))
131 #define SSCR3_FRM_MST_EN BIT(0)
149 #define SSCR5_FRM_POLARITY(x) DAI_INTEL_SSP_SET_BIT(0, x)
156 #define SFIFOL_TFL(x) ((x) & 0xFFFF)
162 #define SSCR3_TFL_MASK DAI_INTEL_SSP_MASK(5, 0)
164 #define SSCR3_TFL_VAL(scr3_val) (((scr3_val) >> 0) & DAI_INTEL_SSP_MASK(5, 0))
165 #define SSCR3_RFL_VAL(scr3_val) (((scr3_val) >> 8) & DAI_INTEL_SSP_MASK(5, 0))
174 #define SSMIDyCS_RXEN BIT(0)
177 #define SSMIDyCS_RFL_VAL(rfl_val) (((rfl_val) >> 16) & DAI_INTEL_SSP_MASK(7, 0))
186 #define SSMIDyTSA_RTSA DAI_INTEL_SSP_MASK(63, 0)
187 #define SSMIDyTSA_SRTSA(x) DAI_INTEL_SSP_MASK(63, 0, x)
190 #define SSMODyCS_TXEN BIT(0)
193 #define SSMIDyCS_TFL_VAL(rfl_val) (((rfl_val) >> 16) & DAI_INTEL_SSP_MASK(7, 0))
199 #define SSMODyTSA_TTSA DAI_INTEL_SSP_MASK(63, 0)
200 #define SSMODyTSA_STTSA(x) DAI_INTEL_SSP_MASK(63, 0, x)
208 #define SSP_CLK_MCLK_ES_REQ BIT(0)
213 #define I2SLCTL_OFFSET 0x04
215 #define I2SLCTL_SPA(x) BIT(0 + x)
219 #define SHIM_CLKCTL 0x78
225 #define MN_MDIVCTRL 0x100
228 #define MN_MDIVR(x) (0x180 + (x) * 0x4)
230 #define MN_MDIVCTRL 0x0
231 #define MN_MDIVR(x) (0x80 + (x) * 0x4)
241 #define MN_MDIV_M_VAL(x) (0x100 + (x) * 0x8 + 0x0)
244 #define MN_MDIV_N_VAL(x) (0x100 + (x) * 0x8 + 0x4)
250 #define MN_SOURCE_CLKS_MASK 0x3